CN1664903A - Mixed latch trigger - Google Patents
Mixed latch trigger Download PDFInfo
- Publication number
- CN1664903A CN1664903A CN2004100264701A CN200410026470A CN1664903A CN 1664903 A CN1664903 A CN 1664903A CN 2004100264701 A CN2004100264701 A CN 2004100264701A CN 200410026470 A CN200410026470 A CN 200410026470A CN 1664903 A CN1664903 A CN 1664903A
- Authority
- CN
- China
- Prior art keywords
- type transistor
- data
- node
- flip flop
- nmos type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
- G11C27/02—Sample-and-hold arrangements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0294—Details of sampling or holding circuits arranged for use in a driver for data electrodes
Landscapes
- Logic Circuits (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
This invention discloses one LCD driver circuit mixture locking trigger, which comprises one positive impulse generator, one trigger unit and one buffer unit, wherein the trigger unit comprises one sample unit and one keep unit; due to the positive impulse generator, the sample unit uses six to seven transistors to make the invention of simple structure and low power. The invention can make the trigger data transmission capacity larger by one time without changing the clock frequency through double edge trigger means.
Description
[technical field]
The invention relates to a kind of trigger, particularly about a kind of mixing latched flip flop.
[background technology]
Current thin film transistor liquid crystal display (TFT-LCD) (TFT-LCD) becomes the standard output device of various digital products gradually, but needs the suitable driving circuit of design to guarantee its steady operation.
Usually, liquid crystal display drive circuit can be divided into two parts, i.e. source electrode drive circuit and gate driver circuit.Source electrode drive circuit is used to control the GTG of each pixel cell of TFT-LCD, and gate driver circuit then is used to control the scanning of each pixel cell.Two kinds of driving circuits are all used shift register as core circuit, and latch and trigger are the common selections as shift register.Trigger has the numerous species type, for example set-reset flip-floop, JK flip-flop, d type flip flop and T trigger.Wherein, d type flip flop is most commonly used in the shift register.Therefore, d type flip flop also the Chang Zuowei core circuit be used for the TFT-LCD driving circuit.
But the d type flip flop of prior art has many shortcomings, penetrates cycle and clock signal skew as length, and for this reason, industry is invented a kind of mixing latched flip flop, and (Hybrid LatchFlip-Flop is HLFF) to address these problems.
" ISSCC technical papers summary " 1996 annual 138-139 pages or leaves disclose a kind of mixing latched flip flop as shown in Figure 1, and the mixing latched flip flop 100 of the prior art comprises counter-rotating unit 110, a trigger element 130 and a buffer unit 150, a clock input node 101, a data input pin 103 and a data output end 105.This trigger element 130 comprises a data sampling unit 140 and a holding unit 149.
This counter-rotating unit 110 comprises one first phase inverter 111, one second phase inverter 112 and one the 3rd phase inverter 113.Wherein, the input end of this first phase inverter 111 is connected with clock signal node 101, the output terminal of this first phase inverter 111 connects the input end of this second phase inverter 112, the output terminal of this second phase inverter 112 connects the input end of the 3rd phase inverter 113, and the output terminal of the 3rd phase inverter 113 connects this trigger element 130.
This data sampling unit 140 comprises 4 positive channel metal semiconductor PMOS (Positive-Channel Metal Oxide Semiconductor) transistor npn npn (i.e. one first pmos type transistor 131, one second pmos type transistor 132, one the 3rd pmos type transistor 133 and one the 4th pmos type transistor 134) and 6 negative channel metal semiconductor N MOS (Negative-Channel Metal Oxide Semiconductor) transistor npn npn (i.e. one first nmos type transistor 141, one second nmos type transistor 142, one the 3rd nmos type transistor 143, one the 4th nmos type transistor 144, one the 5th nmos type transistor 145 and one the 6th nmos type transistor 146), wherein, this first, two, three, four pmos type transistors 131,132,133,134 source electrode all connects a power supply node 104 (being source voltage VDD node).The grid of this first pmos type transistor 131, the grid of first nmos type transistor, 141 grids and the 4th nmos type transistor 144 all is connected the grid of clock signal input terminal 101, the second pmos type transistors 132 and the grid of second nmos type transistor 142 all is connected this data input pin 103.The data output end of the 3rd phase inverter 113 connects the grid of the 3rd nmos type transistor 143, the grid of the 6th nmos type transistor 146 and the grid of the 3rd pmos type transistor 133.The drain electrode of the first pmos type transistor 131 connects the drain electrode of first nmos type transistor 141, the drain electrode of the second pmos type transistor 132, the drain electrode of the 3rd pmos type transistor 133, the grid of the 4th pmos type transistor 134, the grid of the 5th nmos type transistor 145 respectively.The source electrode of first nmos type transistor 141 connects the drain electrode of second nmos type transistor 142.The source electrode of second nmos type transistor connects the drain electrode of the 3rd nmos type transistor.The drain electrode of the 4th pmos type transistor 134 connects the drain electrode of the 4th nmos type transistor 144.The source electrode of the 4th nmos type transistor 144 connects the drain electrode of the utmost point to the five nmos type transistors 145.The source electrode of the 5th nmos type transistor connects the drain electrode of the 6th nmos type transistor 146.The source electrode of the 3rd nmos type transistor 143 and the 6th nmos type transistor 146 is ground connection (zero volt) all.
This holding unit 149 comprises one the 4th phase inverter 147 and one the 5th phase inverter 148.Wherein, the input end of the 4th phase inverter 147 is connected the drain electrode of the 4th pmos type transistor 134 with the output terminal of the 5th phase inverter 148, and the output terminal of the 4th phase inverter 147 and the input end of the 5th phase inverter 148 are connected buffer unit 150 simultaneously.
This buffer unit 150 comprises a hex inverter 151.Wherein, hex inverter 151 input ends connect the output terminal of the 4th phase inverter 147, and hex inverter 151 output terminals connect data output end 105.
During work, provide a clock signal to clock signal input terminal 101, when the clock signal was low-voltage, first nmos type transistor 141 and the 4th nmos type transistor 144 were closed, and the first pmos type transistor 131 is opened.The low-voltage of three phase inverter change over clock signals becomes high voltage in the counter-rotating unit 110, and this high voltage is opened the 3rd nmos type transistor 143 and the 6th nmos type transistor 146, and the 3rd pmos type transistor 133 is closed.Node V as shown in Figure 1 then
1Voltage be charged high voltage VDD, this voltage is closed the 4th pmos type transistor 134, keeps the magnitude of voltage of data output end 105 constant.
When rising edge clock signal arrives, first nmos type transistor 141 and the 4th nmos type transistor 144 are opened, the 3rd nmos type transistor 143 and the 6th nmos type transistor 146 postpone opening a period of time, and this a period of time is by decision time delay of counter-rotating unit 110.Tentation data input end 103 is low-voltage at this moment, and then the second pmos type transistor 132 is opened node V
1Be charged high voltage VDD, the 5th nmos type transistor 145 is opened, and the 4th pmos type transistor 134 closes, and the 4th pmos type transistor 134 source electrodes are zero volt by the 4th, the 5th and the 6th nmos type transistor 144,145 and the discharge of 146 ground connection.Another kind of situation, tentation data input end 103 is high voltage at this moment, and second nmos type transistor 142 is opened, and the second pmos type transistor 132 is closed V
1Node is zero volt by the 4th, the 5th and the 6th nmos type transistor 144,145 and the discharge of 146 ground connection, because of V
1Be low-voltage then the 5th nmos type transistor 145 close, pmos type transistor 134 is opened, and the drain electrode output HIGH voltage of the 4th pmos type transistor 134 is to holding unit 149, in the above-mentioned time period, this trigger element 130 is considered as opening, and the data of data input pin 103 can be sampled and latch.In case the CKDB of node shown in Fig. 1 transfers low-voltage to be low-voltage after, V
1Weaken with being connected of data input pin, this trigger element 130 is considered as closing closed state.The first pmos type transistor 131 is opened all the time and is kept node V behind the clock negative edge
1Voltage be high voltage VDD, the data of data input pin 103 can not be sampled.
Shown in Figure 2 is the working timing figure that mixes latched flip flop among Fig. 1, wherein the voltage waveforms figure at data input pin 103, clock signal input terminal 101 and data output end 105 places in V (D), V (CLOCK) and V (Q) the difference representative graph 1.As depicted in figs. 1 and 2, data output end 105 is in T
nBefore time low-voltage, the rising edge clock time T
nTime place, data input pin 103 is high voltages, and the high voltage of data input pin 103 is sampled and exports, and data output end 105 changes high voltage into from low-voltage.T
N+1Before time, data input pin 103 is low-voltages, and data output end 105 is high voltages, T
N+1The time, the low-voltage of data input pin is sampled and exports, and data output end 105 changes low-voltage into from high voltage.T
N+2Preceding data input pin 103 is low-voltages, and data output end 105 is both low-voltage, T
N+2The time, the low-voltage of data input pin 103 is sampled, and data output end 105 remains low-voltage.T
N+3Preceding data input pin 103 is high voltages, and data output end 105 is low-voltages, T
N+3The time, the high voltage of data input pin 103 is sampled, and data output end 105 changes high voltage into, T from low-voltage
N+4Preceding data input pin 103 is high voltages, and data output end 105 is both high voltage, T
N+4The time, the high voltage of data input pin 103 is sampled, and data output end 105 remains high voltage.T
N+5Preceding data input pin 103 is low-voltages, and data output end 105 is high voltages, T
N+5The time, the low-voltage of data input pin 103 is sampled, and data output end 105 changes low-voltage into from high voltage.
But, when this mixing latched flip flop is used for liquid crystal display drive circuit, each column electrode and row electrode all need use one to mix latched flip flop 100 respectively, and prior art mixing latched flip flop 100 contained number of transistors are more, cause the power consumption of control circuit for liquid crystal display (LCD) driver too high, in order to adapt to the needs of TFT-LCD low-power consumption Drive and Control Circuit, the mixing latched flip flop that is used for TFT-LCD needs less power consumption.Promptly need a circuit with mixing that latched flip flop 100 has said function but power consumption is less.
[summary of the invention]
Mix the high problem of latched flip flop power consumption in the prior art for solving.The object of the present invention is to provide a kind of mixing latched flip flop with more low-power consumption.
The technical scheme of technical solution problem of the present invention provides a kind of mixing latched flip flop, comprise a clock signal input part, a positive pulse generator, a trigger element, a buffer unit, a data input pin and a data output end, this trigger element comprises a sampling unit and a holding unit.This clock signal input terminal is connected with this positive pulse generator, this positive pulse generator is connected with this sampling unit, this sampling unit is connected with this holding unit, this holding unit is connected with this buffer unit, this data input pin is connected with this sampling unit, and this data output end is connected with buffer.
This positive pulse generator can be rising edge flip-over type, negative edge flip-over type or two along flip-over type, and this sampling unit comprises seven transistors or six transistors.
Compared to prior art, because mixing latched flip flop of the present invention has adopted the positive pulse generator, sampling unit in this mixing latched flip flop can only adopt six or seven transistors, mix the number of transistors of the sampling unit of latched flip flop lacks than prior art, though this positive pulse generator comprises the counter-rotating unit than the mixing latched flip flop of prior art more transistor is arranged, can discrete pulse generator and trigger element but adopted after the trigger action mode, make this positive pulse generator become omnibus circuit in liquid crystal display drive circuit, this positive pulse generator comprises that more multiple transistor can not increase power consumption.Therefore mixing latched flip flop of the present invention has been realized than the prior art purpose of low-power consumption more.
In addition, if employing is two along triggering, does not change clock frequency and just can improve the twice of the data transmission capacity of the present invention's mixing latched flip flop to prior art mixing latched flip flop data transmission capacity.
[description of drawings]
Fig. 1 is the circuit diagram that prior art is mixed latched flip flop.
Fig. 2 is the working timing figure that prior art is mixed latched flip flop.
Fig. 3 is the piecemeal synoptic diagram of the present invention's mixing latched flip flop.
Fig. 4 is the first embodiment circuit diagram that mixes the positive pulse generator of latched flip flop among Fig. 3.
Fig. 5 is the second embodiment circuit diagram that mixes the positive pulse generator of latched flip flop among Fig. 3.
Fig. 6 is the 3rd embodiment circuit diagram that mixes the positive pulse generator of latched flip flop among Fig. 3.
Fig. 7 is the first embodiment circuit diagram of the trigger element of the present invention's mixing latched flip flop.
Fig. 8 is the second embodiment circuit diagram of the trigger element of the present invention's mixing latched flip flop.
Fig. 9 is the 3rd an embodiment circuit diagram of the trigger element of the present invention's mixing latched flip flop.
Figure 10 is the 4th an embodiment circuit diagram of the trigger element of the present invention's mixing latched flip flop.
Figure 11 is the working timing figure of Fig. 3 the present invention mixing latched flip flop.
Figure 12 is the circuit diagram that the present invention's mixing latched flip flop is used for liquid crystal display-driving.
[embodiment]
See also Fig. 3, it is the structured flowchart of mixing latched flip flop 300 of the present invention, this mixing latched flip flop 300 comprises a clock signal input part 301, a positive pulse generator 310, a trigger element 330, a buffer unit 350, a data input pin 303 and a data output end 305, and this trigger element comprises a sampling unit 340 and a holding unit 349 for 330 yuan.
This clock signal input terminal 301 is connected with this positive pulse generator 310, this positive pulse generator 310 is connected to this sampling unit 340 by node 302, this sampling unit 340 is connected to this holding unit 349 by node 304, this holding unit is connected to buffer unit 350 by node 306, this data input pin 303 is connected with this sampling unit 340, and this data output end 305 is connected with buffer unit 350.
This positive pulse generator 310 can change the clock signal that receives into positive pulse signal then from clock signal input terminal 301 receive clock signals.This positive pulse signal offers trigger element 330 by node 302.In the trigger element 330, sampling unit 340 receives data-signal by data input pin 303, and receive positive pulse signal from positive pulse generator 310, sampling unit 340 is in the data-signal of each positive pulse peak value moment sampled data input end 303, i.e. in each positive pulse peak value moment, the number of it is believed that is a high voltage in full, this sampling unit is exported a high voltage, on the contrary, if data-signal is a low-voltage, then this sampling unit is exported a low-voltage.Data after the sampling are input to holding unit 349 by node 304.Before the data sampling, this holding unit 349 keeps from the sampled result of sampling unit 340 inputs, and exports these sampled result to buffer unit 350 from node 306 next time.Buffer unit 350 postpones and amplifies this sampled result, provide one more high driving ability to subsequent conditioning circuit.Clearly, this mixing latched flip flop 300 can be realized the basic function of general trigger, promptly according to clock signal sampled data signal and output data signal.The positive pulse generation unit of this mixing latched flip flop can comprise three kinds of embodiments among the present invention, and trigger element can comprise four kinds of embodiments.
Seeing also Fig. 4, is that this positive pulse generator 410 of the first embodiment circuit diagram that mixes the positive pulse generator of latched flip flop among Fig. 3 comprises one first phase inverter 411, one second phase inverter 412, one the 3rd phase inverter 413, one the 4th phase inverter 414 and Sheffer stroke gate 415.The input end of first phase inverter 411 connects clock signal input terminal 401, and its output terminal connects the input end of second phase inverter 412.The output terminal of second phase inverter connects the input end of the 3rd phase inverter 413, the output terminal of the 3rd phase inverter 413 connects an input end of Sheffer stroke gate 415, another input end of Sheffer stroke gate 415 connects clock signal input terminal 401, the output terminal of Sheffer stroke gate 415 connects the input end of the 4th phase inverter 414, the output terminal connected node 402 of the 4th phase inverter 414.The clock signal that first phase inverter 411 and second phase inverter 412 postpone from clock signal input terminal, the 3rd phase inverter 413 postpones and reverses from the clock signal of clock signal input terminal 401.Be node 401 clock signal by first phase inverter 411, second phase inverter 412 and the 3rd phase inverter 413 postpones and counter-rotating after be input to an input end of Sheffer stroke gate 415, the clock signal of node 401 is input to another input end of Sheffer stroke gate 415 simultaneously.Be that rising edge of clock signal or negative edge are by an input end of direct input nand gate 415, this rising edge or negative edge are delayed and are reversed to another input end that is input to Sheffer stroke gate 415 behind negative edge or the rising edge, after receiving rising edge clock at every turn, before the negative edge that postpones, Sheffer stroke gate 415 outputs one negative voltage gets up then to form negative pulse continuously.This negative pulse is inverted to positive pulse after through the 4th phase inverter 414, and outputs to node 402.But after receiving the clock negative edge, before the rising edge of delay, and no pulse produces at every turn.
Seeing also Fig. 5, is the second embodiment circuit diagram that mixes the positive pulse generator of latched flip flop among Fig. 3.This positive pulse generator 510 comprises one first phase inverter 511, one second phase inverter 512, one the 3rd phase inverter 513, one the 4th phase inverter 514 and or door 516.The input end of first phase inverter 511 connects clock signal input terminal 501, and its output terminal connects the input end of second phase inverter 512.The output terminal of second phase inverter 512 connects the input end of the 3rd phase inverter 513, the output terminal connection of the 3rd phase inverter 513 or an input end of door 516, or another input end of door 516 connects clock signal input terminal 501, or the output terminal of door 516 connects the input end of the 4th phase inverter 514, the output terminal connected node 502 of the 4th phase inverter 514.The clock signal that first phase inverter 511 and second phase inverter 512 postpone from clock signal input terminal, the 3rd phase inverter 513 postpones and reverses from the clock signal of clock signal input terminal 501.Be node 501 clock signal by first phase inverter 511, second phase inverter 512 and the 3rd phase inverter 513 postpones and counter-rotating after be input to or an input end of door 516, the clock signal of node 501 is input to or another input end of door 516 simultaneously.Be that rising edge of clock signal or negative edge are directly imported or a door input end of 516, this rising edge or negative edge are delayed and are reversed to and be input to behind negative edge or the rising edge or another input end of door 516, after receiving the clock negative edge at every turn, before the rising edge that postpones, or door 516 outputs one negative voltage, get up continuously then to form negative pulse.This negative pulse is inverted to positive pulse after through the 4th phase inverter 514, and outputs to node 502.But after receiving rising edge clock, before the negative edge of delay, and no pulse produces at every turn.
Seeing also Fig. 6, is the 3rd embodiment circuit diagram that mixes the positive pulse generator of latched flip flop among Fig. 3.It should be noted that: this embodiment adopts two behind flip-over type positive pulse generator, the frequency that need the not change clock capacity of data transmission that just can double.This positive pulse generator 610 comprises one first phase inverter 611, one second phase inverter 612, one the 3rd phase inverter 613, one the 4th phase inverter 614 and XOR gate 617.The input end of first phase inverter 611 connects clock signal input terminal 601, and its output terminal connects the input end of second phase inverter 612.The output terminal of second phase inverter 612 connects the input end of the 3rd phase inverter 613, the output terminal of the 3rd phase inverter 613 connects an input end of XOR gate 617, another input end of XOR gate 617 connects clock signal input terminal 601, the output terminal of XOR gate 617 connects the input end of the 4th phase inverter 614, the output terminal connected node 602 of the 4th phase inverter 614.The clock signal that first phase inverter 611 and second phase inverter 612 postpone from clock signal input terminal, the 3rd phase inverter 613 postpones and reverses from the clock signal of clock signal input terminal 601.Be node 601 clock signal by first phase inverter 611, second phase inverter 612 and the 3rd phase inverter 613 postpones and counter-rotating after be input to an input end of XOR gate 617, the clock signal of node 601 is input to another input end of XOR gate 617 simultaneously.Rising edge of clock signal or negative edge are directly imported an input end of XOR gate 617, this rising edge or negative edge are delayed and are inverted to another input end that is input to XOR gate 617 behind negative edge or the rising edge, after receiving the clock negative edge at every turn, before the rising edge that postpones, after receiving rising edge clock at every turn, before the negative edge that postpones, XOR gate 617 is all exported a negative voltage, gets up then to form negative pulse continuously.This negative pulse is inverted to positive pulse after through the 4th phase inverter 614, and outputs to node 602.
Seeing also Fig. 7, is the first embodiment circuit diagram of trigger element in Fig. 3 mixing latched flip flop and the circuit diagram of buffer unit.Trigger element 730 comprises a sampling unit 740 and a holding unit 749 as shown in Figure 7.This sampling unit 740 comprises three pmos type transistors (i.e. the first pmos type transistor 731, the second pmos type transistor 732 and the 3rd pmos type transistor 733) and four NMOS transistor npn npn (i.e. first nmos type transistor 741, second nmos type transistor 742, the 3rd nmos type transistor 743 and the 4th nmos type transistor 744).This holding unit 749 comprises the 5th phase inverter 747 and hex inverter 748.
The source electrode of the source electrode of this first pmos type transistor 731, the source electrode of the second pmos type transistor 732 and the 3rd pmos type transistor 733 all is connected to power vd D.The grid of the grid of the grid of the first pmos type transistor 731, second nmos type transistor 742 and the 4th nmos type transistor 744 is connected node 702 all.The grid of the grid of first nmos type transistor 741 and the second pmos type transistor 732 all is connected data input pin 703.The drain electrode of the grid of the grid of the drain electrode of the drain electrode of the first pmos type transistor 731, the second pmos type transistor 732, the 3rd pmos type transistor 733, the 3rd nmos type transistor 743 and first nmos type transistor 741 is connected node V all
7The source electrode of first nmos type transistor 741 connects the drain electrode of second nmos type transistor 742.The source electrode of the 3rd nmos type transistor 743 connects the drain electrode of the 4th nmos type transistor 744.The source electrode of the source electrode of second nmos type transistor 742 and the 4th nmos type transistor 744 is ground connection (zero volt) all.The drain electrode of the drain electrode of the 3rd pmos type transistor 733 and the 3rd nmos type transistor 743 is all passed through node 704 and is connected holding unit 749.The first pmos type transistor 731, the second pmos type transistor 732, first nmos type transistor 741 and second nmos type transistor 742 constitute a Sheffer stroke gate (not indicating).Node 702 and data input pin 703 are two of this Sheffer stroke gate (not indicating), node V
7It is the output terminal of this Sheffer stroke gate (not indicating).Suppose that node 702 is low-voltages, no matter data input pin 703 is low-voltage or high voltage, node V
7All be high voltage, the 3rd pmos type transistor 733 is closed, and the 3rd nmos type transistor 743 is opened.Because of hypothesis node 702 is low-voltages, the 4th nmos type transistor 744 is closed, and the data of holding unit 749 are constant as a result.In addition, suppose that node 702 is high voltages, when data input pin 703 is low-voltage, V
7Node is a high voltage.Node 702 is high voltages, and data input pin 703 V when being high voltage
7Node is a low-voltage.If V
7Node is a high voltage, the 3rd pmos type transistor 733 is closed, the 3rd nmos type transistor 743 is opened, because of hypothesis node 702 is high voltages, the 4th nmos type transistor 744 is opened, holding unit 749 discharges over the ground by node 704, the 3rd nmos type transistor 743 and the 4th nmos type transistor 744, and this just is equal to output one low-voltage to holding unit 749.On the other hand, if V
7Node is a low-voltage, and the 3rd pmos type transistor 733 is opened, and the 3rd nmos type transistor 743 is closed, and so just exports a high voltage to holding unit 749.The result is triggered by rising edge clock, and the data of data input pin are sampled.The data that are sampled are input to holding unit 749 from sampling unit 740 through node 704.Before next data was sampled, holding unit 749 counter-rotatings also kept this sampled data, and this sampled data is input to buffer unit 750 through node 706 then.
This buffer unit 750 comprises one the 7th phase inverter 751, and these phase inverter 751 counter-rotatings are through the counter-rotating sampled data of trigger element 730 and node 706 inputs.So the data when this sampled data just reverts to crude sampling are then with original sampled data input end 705.Promptly this buffer unit 750 is for output signal provides a buffer memory, and provides higher driving force for subsequent conditioning circuit.
Seeing also Fig. 8, is the second embodiment circuit diagram of trigger element in Fig. 3 mixing latched flip flop and the circuit diagram of buffer unit.Trigger element 830 comprises a sampling unit 840, one holding units 849 as shown in Figure 8.This sampling unit 840 comprises three pmos type transistors (i.e. the first pmos type transistor 831, the second pmos type transistor 832 and the 3rd pmos type transistor 833) and four NMOS transistor npn npn (i.e. first nmos type transistor 841, second nmos type transistor 842, the 3rd nmos type transistor 843 and the 4th nmos type transistor 844).This holding unit 849 comprises the 5th phase inverter 847 and hex inverter 848.
The source electrode of the source electrode of this first pmos type transistor 831, the source electrode of the second pmos type transistor 832 and pmos type transistor 833 all is connected to power vd D.The grid of the grid of the first pmos type transistor 831 and second nmos type transistor 842 all is connected data input pin 803.The grid of the grid of the grid of first nmos type transistor 848, the second pmos type transistor 832 and the 3rd nmos type transistor 843 is connected node 802 all.The drain electrode of the grid of the grid of the drain electrode of the drain electrode of the first pmos type transistor 831, the second pmos type transistor 832, the 3rd pmos type transistor 833, the 4th nmos type transistor 844 and first nmos type transistor 841 is connected node V all
8The source electrode of first nmos type transistor 841 connects the drain electrode of second nmos type transistor 842.The source electrode of the 3rd nmos type transistor 843 connects the drain electrode of the 4th nmos type transistor 844.The source electrode of the source electrode of second nmos type transistor and the 4th nmos type transistor 844 is ground connection (zero volt) all.The drain electrode of the drain electrode of the 3rd pmos type transistor 833 and the 3rd nmos type transistor 843 is all passed through node 804 and is connected holding unit 849.The first pmos type transistor 831, the second pmos type transistor 832, first nmos type transistor 841 and second nmos type transistor, 842 formations, one Sheffer stroke gate (indicating) node 802 and data input pin 803 are two of this Sheffer stroke gate (indicating), node V
8It is the output terminal of this Sheffer stroke gate (not indicating).Suppose that node 802 is low-voltages, no matter data input pin 803 is low-voltage or high voltage, node V
8All be high voltage, the 3rd pmos type transistor 833 is closed, and the 4th nmos type transistor 844 is opened.Because of hypothesis node 802 is low-voltages, the 3rd nmos type transistor 843 is closed, and the data of holding unit 849 remain unchanged as a result.In addition, suppose that node 802 is high voltages, when data input pin 803 is low-voltage, V
8Node is a high voltage, and node 802 is high voltages, and data input pin 803 V when being high voltage
8Node is a low-voltage.If V
8Node is a high voltage, the 3rd pmos type transistor 833 is closed, the 4th nmos type transistor 844 is opened, because of node 802 is high voltages, the 3rd nmos type transistor 843 is opened, it is zero volt that holding unit 849 discharges over the ground by node 804, the 3rd nmos type transistor 843 and the 4th nmos type transistor 844, and this just is equal to output one low-voltage to holding unit 849.On the other hand, if V
8Node is a low-voltage, and the 3rd pmos type transistor 833 is opened, and the 4th nmos type transistor 844 is closed, and so just exports a high voltage to holding unit 849.Promptly triggered by rising edge clock, the data of data input pin 803 are sampled, and the data that are sampled are input to holding unit 849 by sampling unit 840 through node 804.Before next data was sampled, holding unit 849 counter-rotatings also kept this sampled data, and this sampled data is input to buffer unit 850 through node 806 then.
This buffer unit 850 comprises one the 7th phase inverter 851, and these phase inverter 851 counter-rotatings are from the counter-rotating sampled data of trigger element 830 through node 806 inputs.So the data when this sampled data just reverts to crude sampling are input to node 805 with original sampled data then.Promptly this buffer unit 850 is for output signal provides a buffer memory, and provides higher driving force for subsequent conditioning circuit.
Sampling unit 840 comprises that seven MOS transistor npn npns are very tangible in more than describing.Because trigger action type mixing latched flip flop of the present invention uses positive pulse signal to drive sampling process, the voltage most time of node 802 is low-voltages, V
8The node majority is a high voltage.Therefore for most applications, only adopt the first pmos type transistor 838 just enough, and be better than adopting simultaneously the first pmos type transistor 838 and the second pmos type transistor 832, also can reduce the required number of transistors of trigger element in the present invention's mixing latched flip flop.
Please refer to Fig. 9, is the 3rd embodiment circuit diagram of trigger element in Fig. 3 mixing latched flip flop and the circuit diagram of buffer unit.This trigger element 930 shown in Fig. 9 comprises a sampling unit 940, one holding units 949.This sampling unit 940 comprises two pmos type transistors (i.e. the first pmos type transistor 931 and the second pmos type transistor 932) and four NMOS transistor npn npn (i.e. first nmos type transistor 941, second nmos type transistor 942, the 3rd nmos type transistor 943 and the 4th nmos type transistor 944).This holding unit 949 comprises the 5th phase inverter 947 and hex inverter 948.
The source electrode of this first pmos type transistor 931 and the second pmos type transistor 932 is connected to power vd D.The grid of the grid of the grid of the first pmos type transistor 931, first nmos type transistor 941 and the 3rd nmos type transistor 943 is connected node 902 all.The grid of second nmos type transistor 942 connects data input pin 903.The drain electrode of the grid of the grid of the drain electrode of the first pmos type transistor 931, the second pmos type transistor 932, the 4th nmos type transistor 944 and first nmos type transistor 941 is connected node V all
9The source electrode of first nmos type transistor 941 connects the drain electrode of second nmos type transistor 942.The source electrode of the 3rd nmos type transistor 943 connects the drain electrode of the 4th nmos type transistor 944.The source electrode of the source electrode of second nmos type transistor and the 4th nmos type transistor 944 is ground connection (zero volt) all.The drain electrode of the drain electrode of the second pmos type transistor 932 and the 3rd nmos type transistor 943 is all passed through node 904 and is connected holding unit 949.When node 902 was low-voltage, the first pmos type transistor 931 was opened, and first nmos type transistor 941 is closed, and the 3rd nmos type transistor 943 is closed V
9By continuing charging is high voltage.Because of V
9Be high voltage, the second pmos type transistor 932 is closed, and the 4th NOMS transistor npn npn 944 is opened.The data of holding unit 949 remain unchanged as a result.When node 902 changes were high voltage, the first pmos type transistor 931 was closed, and first nmos type transistor 941 is opened, and the 3rd nmos type transistor 943 is opened, and supposed that this moment, data input pin was a low-voltage, and second nmos type transistor is closed, and considers node V
9Also keep high voltage, the 4th NOMS transistor is held open a period of time, and to discharge over the ground by node 904, the 3rd nmos type transistor 943 and the 4th NOMS transistor npn npn 944 be zero volt to the data of holding unit 949 as a result.This equivalence is arrived voltage holding unit 949 for output one low-voltage.Tentation data input end 903 is high voltages, and the 2nd NOMS transistor npn npn 942 is opened node V
9Discharging over the ground by a NOMS transistor npn npn 941 and the 2nd NOMS transistor npn npn 942 is zero volt, therefore the 4th NOMS transistor npn npn 944 is closed, the second pmos type transistor 932 is opened, and node 904 becomes high voltage and outputs to holding unit 949 by 932 chargings of the second pmos type transistor.Promptly triggered by rising edge clock, the data of data input pin 903 are sampled, and the data that are sampled are input to holding unit 949 by sampling unit 940 through node 904.Before next data was sampled, holding unit 949 counter-rotatings also kept this sampled data, and this sampled data is input to buffer unit 950 through node 906 then.
This buffer unit 950 comprises one the 7th phase inverter 951, and these phase inverter 951 counter-rotatings are through the counter-rotating sampled data of trigger element 930 and node 906 inputs.So the data when this sampled data just reverts to crude sampling are then with original sampled data input end 905.Promptly this buffer unit 950 is for output signal provides a buffer memory, and provides higher driving force for subsequent conditioning circuit.
Please refer to Figure 10, is the 4th embodiment circuit diagram of trigger element in Fig. 3 mixing latched flip flop and the circuit diagram of buffer unit.This trigger element 1030 comprises a sampling unit 1040, one holding units 1049 as shown in Figure 10.This sampling unit 1040 comprises two pmos type transistors (i.e. the first pmos type transistor 1031 and the second pmos type transistor 1032) and four NMOS transistor npn npn (i.e. first nmos type transistor 1041, second nmos type transistor 1042, the 3rd nmos type transistor 1043 and the 4th nmos type transistor 1044).This holding unit 1049 comprises the 5th phase inverter 1047 and hex inverter 1048.
The source electrode of this first pmos type transistor 1031 and the second pmos type transistor 1032 is connected to power vd D.The grid of the grid of the first pmos type transistor 1031 and second nmos type transistor 1042 all is connected data input pin 1003.The grid connected node 1002 of the grid of first nmos type transistor 1041 and the 4th nmos type transistor 1044.The drain electrode of the grid of the grid of the drain electrode of the first pmos type transistor 1031, the second pmos type transistor 1032, the 3rd nmos type transistor 1043 and first nmos type transistor 1041 is connected node V all
10The source electrode of first nmos type transistor 1041 connects the drain electrode of second nmos type transistor 1042.The source electrode of the 3rd nmos type transistor 1043 connects the drain electrode of the 4th nmos type transistor 1044.The source electrode of the source electrode of second nmos type transistor and the 4th nmos type transistor 1044 is ground connection (zero volt) all.The drain electrode of the drain electrode of the second pmos type transistor 1032 and the 3rd nmos type transistor 1043 is all passed through node 1004 and is connected holding unit 1049.Suppose that node 1002 is low-voltages, first nmos type transistor 1041 is closed, and the 4th nmos type transistor 1044 is closed, if data input pin 1003 is low-voltages, the first pmos type transistor 1031 is opened, and second nmos type transistor 1042 is closed joint, some V
10Continued to be charged to high voltage.Because V
10Be high voltage, the second pmos type transistor 1032 is closed, and the 3rd NOMS transistor npn npn 1043 is opened.The data of holding unit 1049 are constant as a result.If data input pin 1003 is high voltages, the first pmos type transistor is closed, and second nmos type transistor 1042 is opened.Because first nmos type transistor 1041 is closed node V
10Still keep high voltage.V
10Be high voltage then the second pmos type transistor 1032 close, the data of holding unit 1049 are constant as a result.No matter promptly the voltage of data input pin is high or low voltage, the data of holding unit 1049 are constant.Suppose that when node 1002 becomes high voltage by low-voltage first nmos type transistor 1041 is opened, the 4th nmos type transistor 1044 is opened.If data input pin 1003 is low-voltages, the first pmos type transistor 1031 is opened, and second nmos type transistor 1042 is closed joint, some V
10Continued to be charged to high voltage.Because V
10Be high voltage, the second pmos type transistor 1032 is closed, and the 3rd NOMS transistor npn npn 1043 is opened.Therefore the 4th nmos type transistor 1044 is also for opening the time, and discharge over the ground by node 1004, the 3rd nmos type transistor 1043 and the 4th NOMS transistor npn npn 1044 be zero to lie prostrate to the data of holding unit 1049 as a result.This equivalence is arrived voltage holding unit 1049 for output one low-voltage.If data input pin 1003 is high voltages, the first pmos type transistor is closed, and second nmos type transistor 1042 is opened.Because first nmos type transistor 1041 is for opening node V
10Discharging over the ground by a NOMS transistor npn npn 1041 and the 2nd NOMS transistor npn npn 1042 is zero volt, and therefore the 4th NOMS transistor npn npn 1044 is closed, and the second pmos type transistor 1032 is opened, and output HIGH voltage is to holding unit 1049.Promptly triggered by rising edge clock, the data of data input pin 1003 are sampled, and the data that are sampled are input to holding unit 1049 by sampling unit 1040 through node 1004.Before next data was sampled, holding unit 1049 counter-rotatings also kept this sampled data, and this sampled data is input to buffer unit 1050 through node 1006 then.
This buffer unit 1050 comprises one the 7th phase inverter 1051, and these phase inverter 1051 counter-rotatings are from the counter-rotating sampled data of trigger element 1030 through node 1006 inputs.So the data when this sampled data just reverts to crude sampling are then with original sampled data input end 1005.Promptly this buffer unit 1050 is for output signal provides a buffer memory, and provides higher driving force for subsequent conditioning circuit.
Describe more than that sampling unit 940 and 1040 only comprises six MOS transistor npn npns in the embodiments of the present invention.Compare, the sampling unit 140 that prior art shown in Figure 1 is mixed latched flip flop comprises ten MOS transistor npn npns, though the number of transistors that positive pulse generator 310 needs in the present invention's mixing latched flip flop is mixed the required number of transistors in counter-rotating unit in the latched flip flop 110 more than prior art shown in Figure 1.Can discrete pulse generator and trigger element but adopted after the trigger action mode, make this positive pulse generator in liquid crystal display drive circuit, become omnibus circuit, with reference to Figure 12 as can be known this positive pulse generation unit be omnibus circuit in liquid crystal display drive circuit, this positive pulse generator comprises that more multiple transistor can not increase power consumption.Therefore mixing latched flip flop of the present invention has been realized than the prior art purpose of low-power consumption more.In addition, if employing is two along triggering, does not change clock frequency and just can improve the twice of the data transmission capacity of the present invention's mixing latched flip flop to prior art mixing latched flip flop data transmission capacity.
Please refer to Figure 11 now, is the working timing figure of the present invention's mixing latched flip flop 300." V (D) " is the data-signal mode chart of data input pin 303 as shown in figure 11; " V (CLOCK) " is the clock signal mode chart of clock signal input terminal 301; " V (CLK) " is the pulse signal wave mode figure of node 302; " V (Q) " is the output signal mode chart of data output end 305." V (CLK) " mode chart shown in this Figure 11 is produced by pulse producer 410 shown in Figure 4.Clock T
nBefore, V (CLK) and V (CLK) they are low-voltages, suppose that V (Q) is a low-voltage, T
nThe time, a rising edge appears in V (CLK), therefore produces one first positive pulse V (CLK), and data-signal V (D) is sampled.Because of T
nThe time V (D is a high voltage, and V (Q) also changes high voltage into.T
N+1The time, another rising edge appears in V (CLK), therefore produces one second positive pulse V (CLK), and data-signal V (D) is sampled.Because of T
N+1The time V (D) be low-voltage, V (Q) also changes low-voltage into.Equally, because of T
N+2The time V (D) be low-voltage, V (Q) still remains low-voltage, because of T
N+3The time V (D) be high voltage, V (Q) also changes high voltage into, because of T
N+4The time V (D) be high voltage, V (Q) still remains high voltage, because of T
N+5The time V (D) be low-voltage, V (Q) also changes low-voltage into.Clearly, this mixing latched flip flop 300 can be realized the basic function of general trigger.Promptly according to clock signal sampled data signal and output data signal.
Claims (8)
1. one kind is mixed latched flip flop, comprising:
One clock signal input part;
One positive pulse generator, this positive pulse generator is connected with this clock signal input terminal, and this clock signal input terminal provides clock signal to this positive pulse generator;
One trigger element, this trigger element comprise a sampling unit and a holding unit, and this holding unit is connected with sampling unit, and this sampling unit is connected with this positive pulse generator simultaneously, and this positive pulse generator provides pulse signal to this trigger element;
One buffer unit, this buffer unit is connected with this holding unit;
One data input pin, this data input pin is connected with this sampling unit, and this data input pin provides data-signal to this trigger element;
One data output end, this data output end is connected with buffer, output signal.
2. mixing latched flip flop as claimed in claim 1 is characterized in that: this positive pulse generator is the rising edge flip-over type.
3. mixing latched flip flop as claimed in claim 1 is characterized in that: this positive pulse generator is the negative edge flip-over type.
4. mixing latched flip flop as claimed in claim 1 is characterized in that: this positive pulse generator is two along hair style.
5. mixing latched flip flop as claimed in claim 1 is characterized in that: this sampling unit comprises seven transistors.
6. mixing latched flip flop as claimed in claim 5 is characterized in that: this sampling unit comprises three pmos type transistors and four NMOS transistor npn npn.
7. mixing latched flip flop as claimed in claim 1 is characterized in that: this sampling unit comprises six transistors.
8. mixing latched flip flop as claimed in claim 7 is characterized in that: this sampling unit comprises two pmos type transistors and four NMOS transistor npn npn.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100264701A CN100483944C (en) | 2004-03-06 | 2004-03-06 | Mixed latch trigger |
| US11/075,119 US7180351B2 (en) | 2004-03-06 | 2005-03-07 | Hybrid latch flip-flop |
| US11/074,446 US7180350B2 (en) | 2004-03-06 | 2005-03-07 | Hybrid latch flip-flop |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100264701A CN100483944C (en) | 2004-03-06 | 2004-03-06 | Mixed latch trigger |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1664903A true CN1664903A (en) | 2005-09-07 |
| CN100483944C CN100483944C (en) | 2009-04-29 |
Family
ID=34892282
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100264701A Expired - Fee Related CN100483944C (en) | 2004-03-06 | 2004-03-06 | Mixed latch trigger |
Country Status (2)
| Country | Link |
|---|---|
| US (2) | US7180351B2 (en) |
| CN (1) | CN100483944C (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105871359A (en) * | 2016-04-22 | 2016-08-17 | 宁波大学 | Pulse trigger based on FinFET device |
| CN105958975A (en) * | 2016-04-22 | 2016-09-21 | 宁波大学 | Pulse D trigger based on Fin FET devices |
| CN105958974A (en) * | 2016-04-22 | 2016-09-21 | 宁波大学 | TSPC trigger based on Fin FET devices |
| CN106961259A (en) * | 2016-01-11 | 2017-07-18 | 中芯国际集成电路制造(上海)有限公司 | D type flip flop |
| CN110391797A (en) * | 2019-06-20 | 2019-10-29 | 广东工业大学 | A kind of d type flip flop circuit based on IGZO TFT |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100483944C (en) * | 2004-03-06 | 2009-04-29 | 鸿富锦精密工业（深圳）有限公司 | Mixed latch trigger |
| TWI308424B (en) * | 2006-04-07 | 2009-04-01 | Innolux Display Corp | Clock-pulse generator and shift register |
| FR2905043B1 (en) * | 2006-08-16 | 2008-11-21 | St Microelectronics Sa | TEMPORALLY SELF-ADJUSTING STATUS-SIZED BISTABLE CIRCUIT AND FLIP-FLOP ROCKET USING SUCH A BISTABLE CIRCUIT |
| US7746137B2 (en) * | 2007-08-28 | 2010-06-29 | Qualcomm Incorporated | Sequential circuit element including a single clocked transistor |
| US20090167368A1 (en) * | 2007-12-27 | 2009-07-02 | Chan Hong H | Pre-driver circuit having a post-boost circuit |
| US7714627B1 (en) * | 2008-11-21 | 2010-05-11 | National Yunlin University Of Science And Technology | Double-triggered logic circuit |
| US8063685B1 (en) | 2010-08-08 | 2011-11-22 | Freescale Semiconductor, Inc. | Pulsed flip-flop circuit |
| US20130063404A1 (en) * | 2011-09-13 | 2013-03-14 | Abbas Jamshidi Roudbari | Driver Circuitry for Displays |
| CN102684647B (en) * | 2012-05-11 | 2014-12-24 | 清华大学 | Sampling pulse type trigger |
| US9564881B2 (en) | 2015-05-22 | 2017-02-07 | Qualcomm Incorporated | Area-efficient metal-programmable pulse latch design |
| US9979394B2 (en) | 2016-02-16 | 2018-05-22 | Qualcomm Incorporated | Pulse-generator |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5126594A (en) * | 1991-07-17 | 1992-06-30 | Motorola, Inc. | Voltage spike detection circuit for use in detecting clock edge transitions within a serial communication system |
| JP3557640B2 (en) * | 1993-12-14 | 2004-08-25 | ソニー株式会社 | Synchronous circuit |
| CN1155785A (en) * | 1995-11-07 | 1997-07-30 | Sgs-汤姆森微电子有限公司 | Flip-flop circuit |
| US5672990A (en) * | 1996-01-26 | 1997-09-30 | United Microelectronics Corporation | Edge-trigger pulse generator |
| US5771240A (en) * | 1996-11-14 | 1998-06-23 | Hewlett-Packard Company | Test systems for obtaining a sample-on-the-fly event trace for an integrated circuit with an integrated debug trigger apparatus and an external pulse pin |
| JP3111936B2 (en) * | 1997-09-10 | 2000-11-27 | 日本電気株式会社 | Synchronous circuit |
| GB0013790D0 (en) * | 2000-06-06 | 2000-07-26 | Texas Instruments Ltd | Improvements in or relating to flip-flop design |
| JP2002300010A (en) * | 2001-03-29 | 2002-10-11 | Toshiba Corp | Semiconductor storage device |
| US6707331B1 (en) * | 2002-07-19 | 2004-03-16 | Xilinx, Inc. | High speed one-shot circuit with optional correction for process shift |
| JP3897671B2 (en) * | 2002-09-30 | 2007-03-28 | 三菱電機株式会社 | Status system signal processing circuit |
| US6937079B1 (en) * | 2003-07-28 | 2005-08-30 | University Of Louisiana At Lafayette | Single-transistor-clocked flip-flop |
| CN100483944C (en) * | 2004-03-06 | 2009-04-29 | 鸿富锦精密工业（深圳）有限公司 | Mixed latch trigger |
-
2004
- 2004-03-06 CN CNB2004100264701A patent/CN100483944C/en not_active Expired - Fee Related
-
2005
- 2005-03-07 US US11/075,119 patent/US7180351B2/en not_active Expired - Fee Related
- 2005-03-07 US US11/074,446 patent/US7180350B2/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106961259A (en) * | 2016-01-11 | 2017-07-18 | 中芯国际集成电路制造(上海)有限公司 | D type flip flop |
| CN105871359A (en) * | 2016-04-22 | 2016-08-17 | 宁波大学 | Pulse trigger based on FinFET device |
| CN105958975A (en) * | 2016-04-22 | 2016-09-21 | 宁波大学 | Pulse D trigger based on Fin FET devices |
| CN105958974A (en) * | 2016-04-22 | 2016-09-21 | 宁波大学 | TSPC trigger based on Fin FET devices |
| CN105958975B (en) * | 2016-04-22 | 2019-03-05 | 宁波大学 | A kind of pulse-type D flip-flop based on FinFET |
| CN105958974B (en) * | 2016-04-22 | 2019-03-05 | 宁波大学 | A kind of TSPC trigger based on FinFET |
| CN105871359B (en) * | 2016-04-22 | 2019-04-16 | 宁波大学 | A kind of pulse trigger based on FinFET |
| CN110391797A (en) * | 2019-06-20 | 2019-10-29 | 广东工业大学 | A kind of d type flip flop circuit based on IGZO TFT |
| CN110391797B (en) * | 2019-06-20 | 2023-04-18 | 广东工业大学 | D trigger circuit based on IGZO TFT |
Also Published As
| Publication number | Publication date |
|---|---|
| US7180351B2 (en) | 2007-02-20 |
| US20050195007A1 (en) | 2005-09-08 |
| US7180350B2 (en) | 2007-02-20 |
| CN100483944C (en) | 2009-04-29 |
| US20050195008A1 (en) | 2005-09-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1664903A (en) | Mixed latch trigger | |
| CN102779478B (en) | Shift register unit and driving method, shift register as well as display device thereof | |
| CN108389539B (en) | Shifting register unit, driving method, grid driving circuit and display device | |
| CN100388334C (en) | Pulse output circuit, shift register and display device | |
| CN205050536U (en) | Shift register unit, shift register and display device | |
| CN106847225A (en) | Display device and gate driving circuit and driver element | |
| CN101308705B (en) | Shift register and shift registering apparatus | |
| CN114038385B (en) | Gate driver and display device | |
| CN1260888C (en) | Level drift circuit and active matrix driver | |
| CN111986609B (en) | Gate drive circuit and display device | |
| CN106847162B (en) | Gate driving unit, driving method, gate driving circuit and display device | |
| WO2021120449A1 (en) | Goa device and display panel | |
| CN106023901B (en) | Shift register cell, driving method, gate driving circuit and display device | |
| CN101303838B (en) | Systems for displaying images by utilizing vertical shift register circuit to generate non-overlapped output signals | |
| CN105321491B (en) | Gate driving circuit and the liquid crystal display using gate driving circuit | |
| CN1097344C (en) | CMOS driver circuit | |
| CN106683617B (en) | Shifting register unit, array substrate and display device | |
| CN1917017A (en) | Emission driver for organic light emitting display device | |
| CN106710513B (en) | Grid scanning circuit and display panel | |
| CN2727897Y (en) | Mixed latching trigger | |
| CN103050104B (en) | Decoding scanning driving device | |
| CN2750410Y (en) | Mixed latching trigger | |
| WO2023207806A1 (en) | Shift register, gate driving circuit and display apparatus | |
| CN1664904A (en) | Mixed latch trigger | |
| CN206340328U (en) | Shift register cell, gate driving circuit and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090429 Termination date: 20160306 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |