CN1655333A - Multiple chip packaging arrangement - Google Patents
Multiple chip packaging arrangement Download PDFInfo
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- CN1655333A CN1655333A CN 200410005515 CN200410005515A CN1655333A CN 1655333 A CN1655333 A CN 1655333A CN 200410005515 CN200410005515 CN 200410005515 CN 200410005515 A CN200410005515 A CN 200410005515A CN 1655333 A CN1655333 A CN 1655333A
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- Prior art keywords
- chipset
- chip
- hole
- pin
- packaging structure
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- 238000004806 packaging method and process Methods 0.000 title claims description 106
- 239000004020 conductor Substances 0.000 claims abstract description 47
- 238000009413 insulation Methods 0.000 claims abstract 5
- 239000000853 adhesive Substances 0.000 claims description 45
- 230000001070 adhesive effect Effects 0.000 claims description 45
- 239000002184 metal Substances 0.000 claims description 17
- 230000002093 peripheral effect Effects 0.000 claims description 17
- 230000004888 barrier function Effects 0.000 claims description 14
- 229910000679 solder Inorganic materials 0.000 abstract 4
- 239000011248 coating agent Substances 0.000 description 8
- 238000000576 coating method Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- 239000000758 substrate Substances 0.000 description 7
- 238000004026 adhesive bonding Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 2
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- Lead Frames For Integrated Circuits (AREA)
Abstract
This invention relates to multiple chips sealed structure, which comprises several chips, one wire rack and several conductive materials. The chip surface has several solder pads and the chip hole passes the solder pad and the insulation layer is coated on the inner wall of the chip hole besides solder pad. The chips are orderly added with two sets of chips with several chip sets hole. The wire rack has several lead legs with two lead leg relative surfaces, which are relative to the connection surface of each chip set. The conductive materials are filled in all chips set hole to connect each chip solder pad and the lead legs.
Description
[technical field]
The invention relates to a kind of emitted semiconductor assembly package structure, and particularly relevant for a kind of multichip packaging structure.
[background technology]
With present semiconductor packaging, can use an adhesive body to coat a plurality of chips usually, to reach capacity or the multi-purpose demand more than the twice, promptly so-called multichip packaging structure.For instance, the memory chip of two 8MB capacity in conjunction with encapsulation, can be obtained the encapsulating structure of a 16MB capacity, not need directly to go to make the single-chip of 16MB capacity.
Please refer to Fig. 1, it illustrates and is United States Patent (USP) case No.5, the profile of 323,060 disclosed multichip packaging structures.In Fig. 1, multichip packaging structure 10 comprises substrate 11, chip 12a, 12b and 12c, adhesion layer 13a and 13b, lead 14a, 14b, 15a, 15b, 16a and 16b and adhesive body 17.The non-acting surface system of chip 12a and the front gluing of substrate 11, and the non-acting surface of chip 12b is the middle body gluing by the acting surface of adhesion layer 13a and chip 12a, and the non-acting surface of chip 12c is the middle body gluing by the acting surface of adhesion layer 13b and chip 12b.Lead 14a and 14b are in order to the front of the weld pad and the substrate 11 of the peripheral part of the acting surface of electrical chip 12a, lead 15a and 15b are in order to the weld pad of the peripheral part of the acting surface of electric connection chip 12b and the front of substrate 11, and lead 16a and 16b are in order to the weld pad of the peripheral part of the acting surface of electric connection chip 12c and the front of substrate 11.In addition, adhesive body 17 is in order to front, chip 12a～12c and the lead 14a～16b of the substrate 11 of covered section.
It should be noted that, working space based on the routing of lead 14a～16b is considered, the thickness of adhesion layer 13a and 13b must reach greatly, and adhesive body 17 necessary coated wire 14a～16b, causes integral thickness, width and the volume of multichip packaging structure 10 to increase many.In addition, because chip 12a～12c is arranged on the front of substrate 11, and the front of adhesive body 17 must be higher than the highest turning point of acting surface and lead 16a and the 16b of chip 12c, loss is to extraneous effectively for the heat that causes chip 12a～12c to be produced, and the radiating effect that influences multichip packaging structure 10 is very huge.
[summary of the invention]
In view of this, purpose of the present invention is providing a kind of multichip packaging structure exactly.The chip through hole of its chip runs through the design of weld pad, allows electric conducting material be filled in the chipset through hole of chip of institute's storehouse, makes the weld pad of these chips and the effect that pin reaches electric connection.Can save the consideration and the cost of routing on the one hand, and effectively shorten chip and chip or pin electric connection approach, improve whole electric characteristics; Can dwindle integral thickness, width and the volume of multichip packaging structure on the other hand.
According to purpose of the present invention, a kind of multichip packaging structure is proposed, comprise several chips, a lead frame, several first electric conducting materials and several second electric conducting materials.Each chip has a relative acting surface and a non-acting surface, several chip through holes and several insulating barriers, and the peripheral part of each acting surface has several weld pads.In each chip, each weld pad and non-acting surface are run through in each chip through hole system, and each series of strata that insulate is coated on the inwall of each the chip through hole beyond each weld pad.The chip system of part sticks together in regular turn and is stacked into one first chipset, and the chip system of another part sticks together in regular turn and is stacked into one second chipset.First chipset has one first relative joint face and one first disconnected, and second chipset has one second relative joint face and one second disconnected.The chip through hole of a chip of two adjacent chips system connects accordingly with the chip through hole of another chip arbitrarily, and the chip through hole of first chipset and second chipset forms several first chipset through holes and several second chipset through holes respectively.First joint face and first disconnected are run through in first chipset through hole system, and second joint face and second disconnected are run through in second chipset through hole system.Lead frame has several pins, and each pin has relative one first pin surface and one second pin surface.Each first pin surface and each second pin surface system are attached to first joint face and second joint face respectively, and correspond respectively to each first chipset through hole and each second chipset through hole.Each first electric conducting material system is filled in each first chipset through hole, and the weld pad of each chip of the chipset of winning is electrically connected with pin accordingly.Each second electric conducting material system is filled in each second chipset through hole, makes the weld pad of each chip of second chipset electrically connect with pin accordingly.
According to a further object of the present invention, a kind of multichip packaging structure is proposed, comprise a lead frame, a chipset, several electric conducting materials.Lead frame has several pins, and each pin has a pin surface.Chipset has several chips, and each chip has several chip through holes, several insulating barriers and a relative acting surface and a non-acting surface.In each chip, the peripheral part of acting surface has several weld pads, and each weld pad and non-acting surface are run through in each chip through hole system, and each series of strata that insulate is coated on the inwall of each the chip through hole beyond each weld pad.These chips stick together storehouse in regular turn, make chipset have a relative joint face and one disconnected.The chip through hole of a chip of two adjacent chips system connects accordingly with the chip through hole of another chip arbitrarily, and these chip through holes of chipset form several chipset through holes.Joint face and disconnected are run through in chipset through hole system, and joint face system is attached to each pin surface, and the chipset through hole is corresponding to pin.Each electric conducting material system is filled in each chipset through hole, makes the weld pad of each chip electrically connect with pin accordingly.
[description of drawings]
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:
It is United States Patent (USP) case No.5 that Fig. 1 illustrates, the profile of 323,060 disclosed multichip packaging structures.
It is profile according to the multichip packaging structure of embodiments of the invention one that Fig. 2 A illustrates.
Fig. 2 B illustrates the profile of the chip that is Fig. 2 A.
Fig. 2 C illustrates the vertical view of the chip that is Fig. 2 B.
Fig. 2 D illustrates the vertical view of the chipset, lead frame and the electric conducting material that are Fig. 2 A.
It is profile according to the multichip packaging structure of embodiments of the invention two that Fig. 2 E illustrates.
It is profile according to the multichip packaging structure of embodiments of the invention three that Fig. 2 F illustrates.
It is profile according to the multichip packaging structure of embodiments of the invention four that Fig. 2 G illustrates.
It is profile according to the multichip packaging structure of embodiments of the invention five that Fig. 2 H illustrates.
It is profile according to the multichip packaging structure of embodiments of the invention six that Fig. 3 A illustrates.
It is profile according to the multichip packaging structure of embodiments of the invention seven that Fig. 3 B illustrates.
It is profile according to the multichip packaging structure of embodiments of the invention eight that Fig. 3 C illustrates.
It is profile according to the multichip packaging structure of embodiments of the invention nine that Fig. 4 A illustrates.
Fig. 4 B illustrates the profile of first chip that is Fig. 4 A.
Fig. 4 C illustrates the handstand profile of second chip that is Fig. 4 A.
It is profile according to the multichip packaging structure of embodiments of the invention ten that Fig. 4 D illustrates.
It is profile according to the multichip packaging structure of embodiments of the invention 11 that Fig. 4 E illustrates.
It is profile according to the multichip packaging structure of embodiments of the invention 12 that Fig. 4 F illustrates.
It is profile according to the multichip packaging structure of embodiments of the invention 13 that Fig. 5 A illustrates.
Fig. 5 B illustrates the profile of the chip that is Fig. 5 A.
It is profile according to the multichip packaging structure of embodiments of the invention 14 that Fig. 5 C illustrates.
[embodiment]
Embodiment one
Please refer to Fig. 2 A, it illustrates is profile according to the multichip packaging structure of embodiments of the invention one.In Fig. 2 A, multichip packaging structure 20a comprises a lead frame 29a, an adhesive body 32a, several electric conducting materials and several chips, as 4 chips 22, two first electric conducting materials 27 and two second electric conducting materials 28.Shown in Fig. 2 B and Fig. 2 C, each chip 22 has a relative acting surface 22a and a non-acting surface 22b, several chip through hole 22c and several insulating barriers 22d, and the peripheral part of the acting surface 22a of each chip 22 has several weld pads 22e.Each weld pad 22e and non-acting surface 22b are run through in each chip through hole 22c system of each chip 22, and each insulating barrier 22d system of each chip 22 coats on the inwall of each the chip through hole 22c beyond each weld pad 22e.Refer again to Fig. 2 A, two chips 22 are to stick together in regular turn to be stacked into one first chipset 23a, and two chips 22 are to stick together in regular turn to be stacked into one second chipset 23b in addition.The first chipset 23a has one first relative joint face 24a and first disconnected 24b, and the second chipset 23b has one second relative joint face 25a and second disconnected 25b.In the first chipset 23a and the second chipset 23b, the chip through hole 22c of a chip 22 of two neighbouring chips 22 system connects accordingly with the chip through hole 22c of another chip 22 arbitrarily.These chip through holes 22c of the first chipset 23a forms several first chipset through holes 26a, and these chip through holes 22c of the second chipset 23b forms several second chipset through holes 26b.The first joint face 24a and first disconnected 24b are run through in these first chipset through holes 26a system, and the second joint face 25a and second disconnected 25b are run through in these second chipset through holes 26b system.
Refer again to Fig. 2 A and Fig. 2 D, each first electric conducting material 27 is to be filled among each first chipset through hole 26a, and the weld pad 22e of each chip 22 of the chipset 23a that wins is electrically connected with pin 21a accordingly.In addition, each second electric conducting material 28 is to be filled among each second chipset through hole 26b, makes the weld pad 22e of each chip 22 of the second chipset 23b electrically connect with pin 21a accordingly.It should be noted that first electric conducting material 27 and second electric conducting material 28 can be same kind of electric conducting material.In addition, adhesive body 32a is in order to coat the pin 21a of the first chipset 23a, the second chipset 23b and part.The first chipset 23a and second chipset 23b system can only not limit to electrically connecting with same pin by corresponding electric conducting material and different pin electric connections.
Embodiment two
Please refer to Fig. 2 E, it illustrates is profile according to the multichip packaging structure of embodiments of the invention two.In Fig. 2 E, what the multichip packaging structure 20b of present embodiment was different with the multichip packaging structure 20a of embodiment one is in the structure of lead frame 29b, and all the other identical members continue to continue to use identical label, and repeat no more.Each pin 21a of lead frame 29b has a pin through hole 21d, each pin through hole 21d is corresponding to each first chipset through hole 26a and each second chipset through hole 26b, and feasible each first electric conducting material 27 or each second electric conducting material 28 are and are filled among each pin through hole 21d.
Embodiment three
Please refer to Fig. 2 F, it illustrates is profile according to the multichip packaging structure of embodiments of the invention three.In Fig. 2 F, what the multichip packaging structure 20c of present embodiment was different with the multichip packaging structure 20a of embodiment one is in the structure of lead frame 29c.First pin surface 21b of each pin 21a of lead frame 29c and second pin surface 21c have conductive projection 30a and 30b respectively, each conductive projection 30a system embeds among each first chipset through hole 26a, and electrically connect with each first electric conducting material 27, be positioned effect on the lead frame 29c to increase by the first chipset 23a.In addition, each conductive projection 30b embeds among each second chipset through hole 26b, and electrically connects with each second electric conducting material 28, is positioned effect on the lead frame 29c to increase by the second chipset 23b.It should be noted that conductive projection 30a and 30b are metal coupling.
Embodiment four
Please refer to Fig. 2 G, it illustrates is profile according to the multichip packaging structure of embodiments of the invention four.In Fig. 2 G, what the multichip packaging structure 20d of present embodiment was different with the multichip packaging structure 20a of embodiment one is in the structure of lead frame 29d.First pin surface 21b of each pin 21a of lead frame 29d and second pin surface 21c have coat of metal 31a and 31b respectively, in order to increase the effect that the first chipset 23a and the second chipset 23b and lead frame 29d electrically connect respectively.
Embodiment five
Please refer to Fig. 2 H, it illustrates is profile according to the multichip packaging structure of embodiments of the invention five.In Fig. 2 H, what the multichip packaging structure 20e of present embodiment was different with the multichip packaging structure 20a of embodiment one is in the structure of lead frame 29e.Lead frame 29e more comprises a chip supporting seat 21e, chip supporting seat 21e has one first relative commissure and one second commissure, first commissure system is attached to the first joint face 24a of the first chipset 23a, and second commissure system is attached to the second joint face 25a of the second chipset 23b.
Embodiment six
Please refer to Fig. 3 A, it illustrates is profile according to the multichip packaging structure of embodiments of the invention six.In Fig. 3 A, the multichip packaging structure 30a of present embodiment is different with the multichip packaging structure 20a of embodiment one is in coating mode in adhesive body 32b.Because the weld pad 22e of the chip 22 of the superiors of the first chipset 23a is not exposed in the external world, so the pin 21a of the first chipset 23a, the second chipset 23b of adhesive body 32b covered section and part, first disconnected 24b of the first chipset 23a be exposed to adhesive body 32b outside.Thus, can increase the radiating effect of multichip packaging structure 30a.In the present embodiment, lead frame 29a system can have designs such as pin through hole, conductive projection, the coat of metal or chip supporting seat.
Embodiment seven
Please refer to Fig. 3 B, it illustrates is profile according to the multichip packaging structure of embodiments of the invention seven.In Fig. 3 B, the multichip packaging structure 30b of present embodiment is different with the multichip packaging structure 30a of embodiment six is in coating mode in adhesive body 32c.Because the weld pad 22e of the undermost chip 22 of the second chipset 23b is not exposed in the external world, so adhesive body 32c coats the second chipset 23b of the first chipset 23a, part and the pin 21a of part, second disconnected 25b of the second chipset 23b be exposed to adhesive body 32c outside.In the present embodiment, lead frame 29a system can have designs such as pin through hole, conductive projection, the coat of metal or chip supporting seat.
Embodiment eight
Please refer to Fig. 3 C, it illustrates is profile according to the multichip packaging structure of embodiments of the invention eight.In Fig. 3 C, the multichip packaging structure 30c of present embodiment is different with the multichip packaging structure 30a of embodiment six is in coating mode in adhesive body 32d.The pin 21a of second chipset 23b of the first chipset 23a of adhesive body 32d covered section, part and part, first disconnected 24b and second disconnected 25b system be exposed to adhesive body 32d outside.In the present embodiment, lead frame 29a system can have designs such as pin through hole, conductive projection, the coat of metal or chip supporting seat.
Embodiment nine
Please refer to Fig. 4 A, it illustrates is profile according to the multichip packaging structure of embodiments of the invention nine.In Fig. 4 A, multichip packaging structure 40a comprises a lead frame 49, one first chipset 43a, one second chipset 43b, several first electric conducting materials 47, several second electric conducting materials 48 and an adhesive body 52a.Lead frame 49 has several pins 41a, and each pin 41a has relative one first pin surface 41b and one second pin surface 41c.
The first chipset 43a has several first chips 42a, and shown in Fig. 4 B, each first chip 42a has one first relative acting surface 42i and one first non-acting surface 42j, several first chips through hole 42k and several first insulating barriers 42c.In each first chip 42a, the peripheral part of the first acting surface 42i has several first weld pads 42e, each the first weld pad 42e and first non-acting surface 42j are run through in each first chip through hole 42k system, and each first insulating barrier 42c system coats on the inwall of each the first chip through hole 42k beyond each first weld pad 42e.
Refer again to Fig. 4 A, the first chip 42a sticks together storehouse in regular turn, makes the chipset 43a that wins have one first relative joint face 44a and first disconnected 44b.The first chip through hole 42k of the one first chip 42a of 2 first adjacent chip 42a system connects accordingly with the first chip through hole 42k of another first chip 42a arbitrarily.The first chip through hole 42k of the first chipset 43a forms several first chipset through holes 46a, and the first joint face 44a and first disconnected 44b are run through in first chipset through hole 46a system.The peripheral part system of the first joint face 44a is attached to each first pin surface 41b, and each first chipset through hole 46a system is corresponding to each pin 41a.
The second chipset 43b has several second chips 42b, and the size of the second chip 42b is different with the size of the first chip 42a.Shown in Fig. 4 C, each second chip 42b has one second relative acting surface 42m and one second non-acting surface 42n, several second chips through hole 42p and several second insulating barriers 42d.In each second chip 42b, the peripheral part of the second acting surface 42m has several second weld pads 42f, each the second weld pad 42f and second non-acting surface 42n are run through in each second chip through hole 42p system, and each second insulating barrier 42d system coats on the inwall of each the second chip through hole 42p beyond each second weld pad 42f.
Refer again to Fig. 4 A, the second chip 42b sticks together storehouse in regular turn, makes the second chipset 43b have one second relative joint face 45a and second disconnected 45b.The second chip through hole 42p of the one second chip 42b of 2 second adjacent chip 42b system connects accordingly with the second chip through hole 42p of another second chip 42b arbitrarily.The second chip through hole 42p of the second chipset 43b forms several second chipset through holes 46b, and the second joint face 45a and second disconnected 45b are run through in second chipset through hole 46b system.The peripheral part system of the second joint face 45a is attached to each second pin surface 41c, and each second chipset through hole 46b system is corresponding to each pin 41a.
Each first electric conducting material 47 is to be filled among each first chipset through hole 46a, makes the first weld pad 42e of each first chip 42a electrically connect with pin 41a accordingly.Each second electric conducting material 48 is respectively to be filled among each second chipset through hole 46b, makes the second weld pad 42f of each second chip 42b electrically connect with pin 41a accordingly.In addition, adhesive body 52a is in order to coat the pin 41a of the first chipset 43a, the second chipset 43b and part.
In the present embodiment, lead frame 49 is the designs such as pin through hole, conductive projection or the coat of metal that can have corresponding to the first chipset through hole 46a, and lead frame 49 is the designs such as pin through hole, conductive projection or the coat of metal that can have corresponding to the second chipset through hole 46b, and lead frame 49 is the design that can have the chip supporting seat.
Embodiment ten
Please refer to Fig. 4 D, it illustrates is profile according to the multichip packaging structure of embodiments of the invention ten.In Fig. 4 D, the multichip packaging structure 40b of present embodiment is different with the multichip packaging structure 40a of embodiment nine is in coating mode in adhesive body 52b.The first chipset 43a of adhesive body 52b covered section, the second chipset 43b and the part pin 41a, first disconnected 44b of the first chipset 43a be exposed to adhesive body 52b outside.In the present embodiment, lead frame 49 is to have designs such as pin through hole, conductive projection, the coat of metal or chip supporting seat.
Embodiment 11
Please refer to Fig. 4 E, it illustrates is profile according to the multichip packaging structure of embodiments of the invention 11.In Fig. 4 E, the multichip packaging structure 40c of present embodiment is different with the multichip packaging structure 40a of embodiment nine is in coating mode in adhesive body 52c.Adhesive body 52c coat the first chipset 43a, the part the second chipset 43b and the part pin 41a, second disconnected 45b of the second chipset 43b be exposed to adhesive body 52c outside.In the present embodiment, lead frame 49 is to have designs such as pin through hole, conductive projection, the coat of metal or chip supporting seat.
Embodiment 12
Please refer to Fig. 4 F, it illustrates is profile according to the multichip packaging structure of embodiments of the invention 12.In Fig. 4 F, the multichip packaging structure 40d of present embodiment is different with the multichip packaging structure 40a of embodiment nine is in coating mode in adhesive body 52d.The pin 41a of second chipset 43b of the first chipset 43a of adhesive body 52d covered section, part and part, first disconnected 44b and second disconnected 45b be exposed to adhesive body 52d outside.In the present embodiment, lead frame 49 is to have designs such as pin through hole, conductive projection, the coat of metal or chip supporting seat.
Embodiment 13
Please refer to Fig. 5 A, it illustrates is profile according to the multichip packaging structure of embodiments of the invention 13.In Fig. 5 A, multichip packaging structure 60a comprises a lead frame 69, a chipset 63, several electric conducting materials 67 and an adhesive body 72a.Lead frame 69 has several pins 61a, and each pin 61a has pin surface 61b.Chipset 63 has several chips 62, and shown in Fig. 5 B, each chip 62 has several chip through holes 62d, several insulating barriers 62e and a relative acting surface 62a and a non-acting surface 62b.In each chip 62, the peripheral part of acting surface 62a has several weld pads 62c, and each weld pad 62c and non-acting surface 62b are run through in each chip through hole 62d system, and each insulating barrier 62e system coats on the inwall of each the chip through hole 62d beyond each weld pad 62c.Please refer to Fig. 5 A, these chips 62 stick together storehouse in regular turn, make chipset 63 have a relative joint face 64 and one disconnected 65, the chip through hole 62d of a chip 62 of two adjacent chips 62 system connects accordingly with the chip through hole 62d of another chip 62 arbitrarily.The chip through hole 62d of chipset 63 forms several chipset through holes 66, and chipset through hole 66 is to run through joint face 64 and disconnected 65.Joint face 64 is to be attached to each pin surface 61b, and chipset through hole 66 is corresponding to pin 61a.
Each electric conducting material 67 is to be filled in each chipset through hole 66, makes the weld pad 62c of each chip 62 electrically connect with pin 61a accordingly.In addition, adhesive body 72a is in order to the pin 61a of coating chip group 63 and part.In the present embodiment, lead frame 69 is to have designs such as pin through hole, conductive projection, the coat of metal or chip supporting seat.
Embodiment 14
Please refer to Fig. 5 C, it illustrates is profile according to the multichip packaging structure of embodiments of the invention 14.In Fig. 5 C, the multichip packaging structure 60b of present embodiment is different with the multichip packaging structure 60a of embodiment 13 is in coating mode in adhesive body 72b.The pin 61a of the chipset 63 of adhesive body 72b covered section and part, disconnected 65 of chipset 63 be exposed to adhesive body 72b outside.In the present embodiment, lead frame 69 is to have designs such as pin through hole, conductive projection, the coat of metal or chip supporting seat.
The disclosed multichip packaging structure of the above embodiment of the present invention, the chip through hole of its chip runs through the design of weld pad, allows electric conducting material be filled in the chipset through hole of chip of institute's storehouse, makes the weld pad of these chips and the effect that pin reaches electric connection.Can save the consideration and the cost of routing on the one hand, and effectively shorten chip and chip or pin electric connection approach, improve whole electric characteristics; Can dwindle integral thickness, width and the volume of multichip packaging structure on the other hand.
In sum; though the present invention discloses as above with a preferred embodiment; right its is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, thus the present invention protection range should be as the criterion according to the scope person of defining of claims.
Claims (28)
1. multichip packaging structure comprises:
A plurality of chips, system respectively has a relative acting surface and a non-acting surface, a plurality of chip through holes and a plurality of insulating barrier, respectively the peripheral part of this acting surface has a plurality of weld pads, respectively respectively this weld pad and this non-acting surface are run through in this chip through hole system, respectively these insulation series of strata are coated on the inwall of respectively this chip through hole beyond this weld pad respectively, those chip systems of part stick together in regular turn and are stacked into one first chipset, those chip systems of another part stick together in regular turn and are stacked into one second chipset, make this first chipset have one first relative joint face and one first disconnected, this second chipset has one second relative joint face and one second disconnected, those through hole systems of a chip of two adjacent these chips connect accordingly with those through holes of another chip arbitrarily, those through holes of this first chipset and this second chipset form a plurality of first chipset through holes and a plurality of second chipset through hole respectively, this first joint face and this first disconnected are run through in those first chipset through holes system, and this second joint face and this second disconnected are run through in those second chipset through holes systems;
One lead frame, have a plurality of pins, respectively this pin has relative one first pin surface and one second pin surface, respectively this first pin surface and respectively this second pin surface system be attached to this first joint face and this second joint face respectively, and correspond respectively to respectively this first chipset through hole and respectively this second chipset through hole;
A plurality of first electric conducting materials are respectively to be filled in respectively in this first chipset through hole, make those weld pads of respectively this chip of this first chipset electrically connect with those pins accordingly; And
A plurality of second electric conducting materials are respectively to be filled in respectively in this second chipset through hole, make those weld pads of respectively this chip of this second chipset electrically connect with those pins accordingly.
2. multichip packaging structure according to claim 1 is characterized in that, respectively this pin has more a pin through hole, and respectively respectively this pin is run through in this pin through hole system, respectively this first electric conducting material or respectively this second electric conducting material system be filled in again respectively in this pin through hole.
3. multichip packaging structure according to claim 1 is characterized in that, respectively this first pin surface has a conductive projection, and respectively this conductive projection embeds respectively in this first chipset through hole, and electrically connects with this first electric conducting material respectively.
4. multichip packaging structure according to claim 1 is characterized in that, respectively this second pin surface has a conductive projection, and respectively this conductive projection embeds respectively in this second chipset through hole, and electrically connects with this second electric conducting material respectively.
5. multichip packaging structure according to claim 1 is characterized in that, respectively this first pin surface has a coat of metal.
6. multichip packaging structure according to claim 1 is characterized in that, respectively this second pin surface has a coat of metal.
7. multichip packaging structure according to claim 1 is characterized in that, this lead frame more comprises:
One chip supporting seat has one first relative commissure and one second commissure, and this first commissure system is attached to this first joint face, and this second commissure system is attached to this second joint face.
8. multichip packaging structure according to claim 1, this multichip packaging structure more comprises:
One adhesive body is in order to coat those pins of this first chipset, this second chipset and part.
9. multichip packaging structure according to claim 1 is characterized in that, this multichip packaging structure more comprises:
One adhesive body, in order to this first chipset of covered section at least, this second chipset of part and those pins of part, this first disconnected or this second disconnected is to be exposed to outside this adhesive body.
10. multichip packaging structure according to claim 1 is characterized in that, this multichip packaging structure more comprises:
One adhesive body, in order to this first chipset of covered section, this second chipset of part and those pins of part, this first disconnected and this second disconnected is to be exposed to outside this adhesive body.
11. a multichip packaging structure comprises:
One lead frame has a plurality of pins, and respectively this pin has relative one first pin surface and one second pin surface;
One first chipset, have a plurality of first chips, respectively this first chip has a plurality of first chip through holes, a plurality of first insulating barriers and relative one first acting surface and one first non-acting surface, the peripheral part of this first acting surface has a plurality of first weld pads, respectively respectively this first weld pad and this first non-acting surface are run through in this first chip through hole system, respectively these first insulation series of strata are coated on the inwall of respectively this first chip through hole beyond this first weld pad respectively, those first chips stick together storehouse in regular turn, make this first chipset have one first relative joint face and one first disconnected, those first chip through hole systems of one first chip of two adjacent these first chips connect accordingly with those first chip through holes of another first chip arbitrarily, those first chip through holes of this first chipset form a plurality of first chipset through holes, this first joint face and this first disconnected are run through in those first chipset through holes system, this first joint face system is attached to respectively this first pin surface, and those first chipset through hole systems are corresponding to those pins;
One second chipset, have a plurality of second chips, respectively this second chip has a plurality of second chip through holes, a plurality of second insulating barriers and relative one second acting surface and one second non-acting surface, the peripheral part of this second acting surface has a plurality of second weld pads, respectively respectively this second weld pad and this second non-acting surface are run through in this second chip through hole system, respectively these second insulation series of strata are coated on the inwall of respectively this second chip through hole beyond this second weld pad respectively, those second chips stick together storehouse in regular turn, make this second chipset have one second relative joint face and one second disconnected, those second chip through hole systems of one second chip of two adjacent these second chips connect accordingly with those second chip through holes of another second chip arbitrarily, those second chip through holes of this second chipset form a plurality of second chipset through holes, this second joint face and this second disconnected are run through in those second chipset through holes system, this second joint face system is attached to respectively this second pin surface, and those second chipset through hole systems are corresponding to those pins;
A plurality of first electric conducting materials are respectively to be filled in respectively in this first chipset through hole, make that respectively those first weld pads of this first chip electrically connect with those pins accordingly; And
A plurality of second electric conducting materials are respectively to be filled in respectively in this second chipset through hole, make that respectively those second weld pads of this second chip electrically connect with those pins accordingly.
12. multichip packaging structure according to claim 11, it is characterized in that, respectively this pin has more a pin through hole, and respectively respectively this pin is run through in this pin through hole system, respectively this first electric conducting material or respectively this second electric conducting material system be filled in accordingly again respectively in this pin through hole.
13. multichip packaging structure according to claim 11, it is characterized in that, respectively this pin has more two pin through holes, and respectively this pin is run through in this two pins through hole system, respectively this first electric conducting material and respectively this second electric conducting material system be filled in accordingly again in this two pins through hole of this pin respectively.
14. multichip packaging structure according to claim 11 is characterized in that, respectively this first pin surface has a conductive projection, and respectively this conductive projection embeds respectively in this first chipset through hole, and electrically connects with this first electric conducting material respectively.
15. multichip packaging structure according to claim 11 is characterized in that, respectively this second pin surface has a conductive projection, and respectively this conductive projection embeds respectively in this second chipset through hole, and electrically connects with this second electric conducting material respectively.
16. multichip packaging structure according to claim 11 is characterized in that, respectively this first pin surface has a coat of metal.
17. multichip packaging structure according to claim 11 is characterized in that, respectively this second pin surface has a coat of metal.
18. multichip packaging structure according to claim 11 is characterized in that, this lead frame more comprises:
One chip supporting seat has one first relative commissure and one second commissure, and this first commissure system is attached to this first joint face, and this second commissure system is attached to this second joint face.
19. multichip packaging structure according to claim 11, this multichip packaging structure more comprises:
One adhesive body is in order to coat those pins of this first chipset, this second chipset and part.
20. multichip packaging structure according to claim 11 is characterized in that, this multichip packaging structure more comprises:
One adhesive body, in order to this first chipset of covered section at least, this second chipset of part and those pins of part, this first disconnected or this second disconnected is to be exposed to outside this adhesive body.
21. multichip packaging structure according to claim 11 is characterized in that, this multichip packaging structure more comprises:
One adhesive body, in order to this first chipset of covered section, this second chipset of part and those pins of part, this first disconnected and this second disconnected is to be exposed to outside this adhesive body.
22. a multichip packaging structure comprises:
One lead frame has a plurality of pins, and respectively this pin has a pin surface;
One chipset, have a plurality of chips, respectively this chip has a plurality of chip through holes, a plurality of insulating barriers and a relative acting surface and a non-acting surface, the peripheral part of this acting surface has a plurality of weld pads, respectively respectively this weld pad and this non-acting surface are run through in this chip through hole system, respectively these insulation series of strata are coated on the inwall of respectively this chip through hole beyond this weld pad respectively, those chips stick together storehouse in regular turn, make this chipset have a relative joint face and one disconnected, those chip through hole systems of a chip of two adjacent these chips connect accordingly with those chip through holes of another chip arbitrarily, those chip through holes of this chipset form a plurality of chipset through holes, those chipset through hole systems run through this joint face and reach this disconnected, this joint face system is attached to respectively this pin surface, and those chipset through hole systems are corresponding to those pins; And
A plurality of electric conducting materials are respectively to be filled in respectively in this chipset through hole, make that respectively those weld pads of this chip electrically connect with those pins accordingly.
23. multichip packaging structure according to claim 22 is characterized in that, respectively this pin has more a pin through hole, and respectively respectively this pin is run through in this pin through hole system, and respectively this electric conducting material system is filled in again respectively in this pin through hole.
24. multichip packaging structure according to claim 22 is characterized in that, respectively this pin surface has a conductive projection, and respectively this conductive projection embeds respectively in this chipset through hole, and electrically connects with this electric conducting material respectively.
25. multichip packaging structure according to claim 22 is characterized in that, respectively this pin surface has a coat of metal.
26. multichip packaging structure according to claim 22 is characterized in that, this lead frame more comprises:
One chip supporting seat has a commissure, and this commissure system is attached to this joint face.
27. multichip packaging structure according to claim 22, this multichip packaging structure more comprises:
One adhesive body is in order to coat those pins of this chipset and part.
28. multichip packaging structure according to claim 22 is characterized in that, this multichip packaging structure more comprises:
One adhesive body, in order to this chipset of covered section and those pins of part, this disconnected is to be exposed to outside this adhesive body.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100055157A CN100343964C (en) | 2004-02-13 | 2004-02-13 | Multiple chip packaging arrangement |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100055157A CN100343964C (en) | 2004-02-13 | 2004-02-13 | Multiple chip packaging arrangement |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1655333A true CN1655333A (en) | 2005-08-17 |
| CN100343964C CN100343964C (en) | 2007-10-17 |
Family
ID=34892077
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100055157A Expired - Lifetime CN100343964C (en) | 2004-02-13 | 2004-02-13 | Multiple chip packaging arrangement |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100343964C (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101330077B (en) * | 2007-06-21 | 2010-06-16 | 海力士半导体有限公司 | Stacked semiconductor package and method for manufacturing the same |
| CN101211899B (en) * | 2006-12-29 | 2010-06-23 | 海力士半导体有限公司 | Stack package having reduced electrical connection length suitable for high speed operations and method of manufacturing the same |
| US7973414B2 (en) | 2007-08-16 | 2011-07-05 | Hynix Semiconductor Inc. | Semiconductor package through-electrode suitable for a stacked semiconductor package and semiconductor package having the same |
| CN114105084A (en) * | 2021-11-15 | 2022-03-01 | 歌尔微电子股份有限公司 | MEMS common-cavity membrane-splitting SOC chip and preparation method thereof |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01144664A (en) * | 1988-03-01 | 1989-06-06 | Mitsubishi Electric Corp | Integrated circuit device for semiconductor memory |
| US5247423A (en) * | 1992-05-26 | 1993-09-21 | Motorola, Inc. | Stacking three dimensional leadless multi-chip module and method for making the same |
| CN100361301C (en) * | 2002-06-28 | 2008-01-09 | 矽品精密工业股份有限公司 | Multi-chip semiconductor package and mfg. method thereof |
-
2004
- 2004-02-13 CN CNB2004100055157A patent/CN100343964C/en not_active Expired - Lifetime
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101211899B (en) * | 2006-12-29 | 2010-06-23 | 海力士半导体有限公司 | Stack package having reduced electrical connection length suitable for high speed operations and method of manufacturing the same |
| US8202762B2 (en) | 2006-12-29 | 2012-06-19 | Hynix Semiconductor Inc. | Stack package having reduced electrical connection length suitable for high speed operations and method of manufacturing the same |
| CN101330077B (en) * | 2007-06-21 | 2010-06-16 | 海力士半导体有限公司 | Stacked semiconductor package and method for manufacturing the same |
| US7858439B2 (en) | 2007-06-21 | 2010-12-28 | Hynix Semiconductor Inc. | Stacked semiconductor package and method for manufacturing the same |
| US8067839B2 (en) | 2007-06-21 | 2011-11-29 | Hynix Semiconductor Inc. | Stacked semiconductor package and method for manufacturing the same |
| US7973414B2 (en) | 2007-08-16 | 2011-07-05 | Hynix Semiconductor Inc. | Semiconductor package through-electrode suitable for a stacked semiconductor package and semiconductor package having the same |
| CN102176439A (en) * | 2007-08-16 | 2011-09-07 | 海力士半导体有限公司 | Semiconductor package through-electrode suitable for a stacked semiconductor package and semiconductor package having the same |
| US8232654B2 (en) | 2007-08-16 | 2012-07-31 | Hynix Semiconductor Inc. | Semiconductor package through-electrode suitable for a stacked semiconductor package and semiconductor package having the same |
| CN101369566B (en) * | 2007-08-16 | 2013-04-24 | 海力士半导体有限公司 | Semiconductor package through-electrode suitable for a stacked semiconductor package and semiconductor package having the same |
| CN114105084A (en) * | 2021-11-15 | 2022-03-01 | 歌尔微电子股份有限公司 | MEMS common-cavity membrane-splitting SOC chip and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100343964C (en) | 2007-10-17 |
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