CN1655116A - Device and method for switching temporary memory according to operation mode in processor - Google Patents
Device and method for switching temporary memory according to operation mode in processor Download PDFInfo
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- CN1655116A CN1655116A CN 200410005334 CN200410005334A CN1655116A CN 1655116 A CN1655116 A CN 1655116A CN 200410005334 CN200410005334 CN 200410005334 CN 200410005334 A CN200410005334 A CN 200410005334A CN 1655116 A CN1655116 A CN 1655116A
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Abstract
This invention relates to a device and a method for switching working registers with operation mode. Said processor has many kinds of operation modes, said device includes a working register position decoder, a first working register, multiple second working registers and a selection device, said register position decoder is for decoding the instructions of the microprocessor to output a decode output, said selecting device selects one to output from at least a first working register and multiple second registers based on the operation mode and said decode output.
Description
Technical field
The invention relates to the technical field of processor, refer to a kind of device and method that in processor, switches working storage especially with operator scheme.
Background technology
In general processor, because processor can be subjected to the restriction of order number space and hardware, make processor can access working storage be subject to the order number space, as shown in Figure 1, have a plurality of working storages 11 in its video-stream processor, when processor is wanted a certain working storage 11 contents of access, demoder 12 meeting decoding instructions, this instruction has working storage addressing field, processor can be according to this field value decoding, see through multiplex's selector switch, the working storage of access appointment, because the number of working storage 11 can be subjected to the restriction of working storage addressing field length, suppose that this field has the length of P-bit, the maximum upper limit of then representing the number that processor can access working storage 11 is 2p, if think to expand again or increase the energy access working storage, unique method just must increase the length of the working storage addressing field in the instruction set, but this will reduce other fields can define in the instruction set space (as the function field, the immediate value field, Deng ... .), therefore, this change is very big for the function effect of instruction set, in addition, for the fixing processor of an instruction set, the field of change instruction set also is infeasible for the formula compatibility, and hence one can see that, well known processor also can't expand the working storage number of institute energy access effectively, and gives improved necessity.
Summary of the invention
Fundamental purpose of the present invention is to switch the device and method of working storage with operator scheme providing a kind of, to solve every shortcoming of known technology.It can expand the working storage number effectively.
According to one of the present invention characteristic, a kind of device that in processor, switches working storage with operator scheme, this processor has multiple modes of operation, it is characterized in that, and this device comprises:
One working storage address demoder is in order to the instruction decoding with microprocessor, to produce a decoding output;
At least one first working storage;
Most second working storage;
One selecting arrangement is operator scheme and this decoding output according to this processor, by this at least one first working storage and most second working storages, selects one of them with output.
Wherein, this selecting arrangement is according to this decoding output, selects one of them by this majority second working storage, and determines whether to select this at least one first working storage according to the operator scheme of this processor, to replace one of this majority second working storage.
Wherein, this selecting arrangement comprises:
At least one first multiplex's selector switch, it is according to the operator scheme of this processor, by one of this at least one first working storage and this majority second working storage, selects one of them and exports; And
One second multiplex's selector switch, it is according to this decoding output, by the output of this majority second working storage and this first multiplex (MUX) selector switch, selects one of them and exports.
Wherein, this multiple modes of operation comprises: user's operator scheme, core operation pattern and debug operator scheme.
Wherein, when this processor during in user's operator scheme and core operation pattern, this selecting arrangement is to select this second working storage.
Wherein, when this processor during in the debug operator scheme, this selecting arrangement is to select this first working storage to replace this second working storage.
According to another characteristic of the present invention, a kind of method of switching working storage in processor with operator scheme, this processor have at least one first working storage and most second working storages, and this processor provides multiple modes of operation, it is characterized in that the method comprising the steps of:
(A) with the instruction decoding of microprocessor, export to produce a decoding; And
(B) be to export,, select one of them with output by this at least one first working storage and most second working storages according to operator scheme and this decoding of this processor.
Wherein, step (B) comprising:
(B1) according to this decoding output, select one of them by this majority second working storage; And
(B2) according to the operator scheme of this processor, whether decision selects this at least one first working storage, to replace one of this majority second working storage.
Wherein, this multiple modes of operation comprises: user's operator scheme, core operation pattern and debug operator scheme.
Wherein, in step (B2),, be to select this second working storage when this processor during in user's operator scheme and core operation pattern.
Wherein, in step (B2),, be to select this first working storage to replace this second working storage when this processor during in the debug operator scheme.
According to another characteristic of the present invention, a kind of device that switches working storage in processor with operator scheme, this processor has multiple modes of operation, it is characterized in that, this device comprises:
One working storage address demoder is in order to the instruction decoding with microprocessor, to produce a decoding output;
At least one first working storage;
Most second working storage;
One selecting arrangement is according to the operator scheme of this processor and this decoding output, by the combination of the some of this majority second working storage and this first working storage and one second working storage, selects one of them and exports.
Wherein, this selecting arrangement is according to this decoding output, selects one of them by this majority second working storage, and according to the operator scheme of this processor, whether decision selects the combination of the some of this first working storage and second working storage, to replace this second working storage.
Wherein, this selecting arrangement comprises:
At least one first multiplex's selector switch, it is according to the operator scheme of this processor, by the combination of the some of this first working storage and one second working storage, and one of this second working storage, selects one of them with output; And
One second multiplex's selector switch, it is according to this decoding output, by the output of this majority second working storage and this first multiplex (MUX) selector switch, selects one of them with output.
Wherein, this multiple modes of operation comprises: user's operator scheme, core operation pattern and debug operator scheme.
Wherein, when this processor during in user's operator scheme and core operation pattern, this selecting arrangement is to select this second working storage.
Wherein, when this processor during in the debug operator scheme, this selecting arrangement is the combination of selecting the some of this first working storage and second working storage, to replace this second working storage.
According to a characteristic more of the present invention, a kind of method of switching working storage in processor with operator scheme, this processor have at least one first working storage and most second working storages, and this processor provides multiple modes of operation, it is characterized in that the method comprising the steps of:
(A) with the instruction decoding of microprocessor, export to produce a decoding; And
(B) be according to the operator scheme of this processor and this decoding output,, select one of them and export by the combination of the some of this majority second working storage and this first working storage and one second working storage.
Wherein, step (B) comprising:
(B1) according to this decoding output, select one of them by this majority second working storage;
(B2) according to this processor De Shu operation mode, whether decision selects the combination of the some of this first working storage and second working storage, to replace this second working storage.
Wherein, this multiple modes of operation comprises: user's operator scheme, core operation pattern and debug operator scheme.
In step (B2),, be to select this second working storage when this processor during at user's operator scheme and He Xin Shu operation mode.
Wherein, in step (B2),, be the combination of selecting the some of this first working storage and second working storage, to replace this second working storage when this processor during in the debug operator scheme.
Description of drawings
For further specifying technology contents of the present invention, below in conjunction with embodiment and accompanying drawing describes in detail as after, wherein:
Fig. 1 is the working storage access device of known technology.
Fig. 2 be a preferred embodiment of the present invention switch the device of working storage with operator scheme.
Fig. 3 be another preferred embodiment of the present invention switch the device of working storage with operator scheme.
Embodiment
For allowing the auditor can more understand technology contents of the present invention, be described as follows especially exemplified by two preferred embodiment.
Relevant one of device and method preferred embodiment of in processor, switching working storage of the present invention with operator scheme, please refer to circuit diagram shown in Figure 2, it is mainly by at least one first working storage 21, most second working storage 22, one selecting arrangement 20, constitute with institutes such as demoders 25, wherein, demoder 25 is in order to the instruction decoding with microprocessor, to produce a decoding output, and in instruction set, the instruction of access working storage has the working storage addressing field of a P bit, processor is just according to the value of these working storage addressing fields of demoder 25 decoding, and the operator scheme of processor, and the working storage content of decision access, and the working storage content that is determined read in system bus and handle, or see through system bus and data write the working storage that is determined by arithmetic element 29.
Aforementioned selecting arrangement 20 includes one first multiplex's selector switch 23 and one second multiplex's selector switch 24, in order to operator scheme and this decoding output according to this processor, with by this first working storage 21 and second working storage 22, selects one of them with output.In present embodiment, processor can have user's pattern, core schema, and various modes such as debug mode.The number of aforementioned second working storage 22 is the length corresponding to the working storage addressing field of processor instruction, for example, when the addressing field is the P bit, the number of second working storage 22 is 2p, and one of them working storage 221 of these second working storages 22 and this first working storage 21 are two links 231 and 232 that are coupled to this first multiplex (MUX) selector switch 23 respectively, and the control end 233 of this first multiplex (MUX) selector switch 23 is selected ends 234 of selecting link 231 or 232 is communicated to this first multiplex (MUX) selector switch 23 according to the operator scheme of processor.
Aforementioned second multiplex's selector switch 24 has most links 241 and a selected end 242, and select that by a control end 243 one of these links 241 are communicated to this and select end 242, wherein, these links 241 are connected to selected end 234, and all the other second working storages 22 except that this second working storage 221 of first multiplex's selector switch 23 respectively; The control end 243 of this second multiplex (MUX) selector switch 24 links to each other with the output of demoder 25, and the working storage addressing field of demoder 25 decoding instructions with the foundation decoded results, is selected one of these links 241 are communicated to this selected end 242.
With aforesaid framework, because the result of the working storage addressing field of demoder 25 decoding instructions selects one of these links 241 are communicated to this selected end 242, these links 241 then are to be connected to the selected end 232 of last selector switch 23 more than first and all the other second working storages 22 except that this second working storage 221, therefore, when the decoded result of demoder 25 is communicated to this selected end 242 for the link 241 of the selected end 234 that will be connected to this first multiplex (MUX) selector switch 23, then all working storages of getting need further to decide according to first multiplex's selector switch 23, that is, when first multiplex's selector switch 23 is when connecting end 231 and being communicated to selected end 234, then processor is access first working storage 21, otherwise, when first multiplex's selector switch 23 is when connecting end 232 and being communicated to selected end 234, then processor is access second working storage 221, and because more than first last selector switchs 23 are controlled by the operator scheme of processor, therefore can make processor under different operator schemes, come the different working storage of access by identical working storage address, and reach the purpose of switching working storage with operator scheme, expand accessible working storage number.
Still please refer to shown in Figure 2; in the present embodiment; when processor during in core schema or user's pattern; control end 233 is that the link 232 with this first multiplex (MUX) selector switch 23 is communicated to selected end 234; therefore; processor can only access second working storage 221; and can't access first working storage 21; so can be when core schema or user's pattern; protect the content of first working storage 21 can not be modified; otherwise; when processor when debug mode is worked, control end 233 is that the link 231 with this first multiplex (MUX) selector switch 23 is communicated to selected end 234, therefore; but processor with access to first working storage 21; and first working storage 21 can store for example processor identification code, uses for debugger, but not only can reach the number of expansion access working storage; also can provide specific city to carry out required identification information, reach the effect of software identification protecting.
Fig. 3 shows another preferred embodiment of switching the device and method of working storage in processor with operator scheme of the present invention; be same as last embodiment; its circuit is by at least one first working storage 31; most second working storage 32; one selecting arrangement 30; salty with institute's structures such as demoders 35; this selecting arrangement 30 also includes one first multiplex's selector switch 33 and one second multiplex's selector switch 34; they are different, and to be in these more than first two links 332 and 331 of going up selector switchs 33 are one of them working storages 321 that is coupled to this majority second working storage 32 respectively; and first working storage 31 is coupled to the some of second working storage 321 of the link 332 of first multiplex's selector switch 33 with this; selecting arrangement 30 can be exported according to the operator scheme and the decoding of processor; and by the combination of the some of this second working storage 32 or first working storage 31 and one second working storage 321; select one of them and export; that is; when processor during in core schema or user's pattern; control end 333 is that the link 332 with this first multiplex (MUX) selector switch 33 is communicated to selected end 334; therefore; processor can access second working storage 321; and can't access first working storage 31; otherwise; when processor is done on debug mode; control end 333 is that the link 331 with this first multiplex (MUX) selector switch 33 is communicated to selected end 334; therefore; but processor also closes access together second working storage 321 of branch to first working storage 31; but thereby also can reach the number of expansion access working storage; and provide specific city to carry out required identification information, reach the effect of software identification protecting.
By above explanation as can be known; the present invention controls multiplex's selector switch by the different operation modes of processor; to switch accessible working storage content; working storage addressing field that can be identical comes the different working storage of access; essence increases the working storage number of energy access; in addition, but the working storage that is expanded is just access under specific operator scheme, so also can protect working storage can not changed arbitrarily by the user under general modfel.
The foregoing description only is to give an example for convenience of description, and the interest field that the present invention advocated should be as the criterion so that claim is described certainly, but not only limits to the foregoing description.
Claims (22)
1. device that in processor, switches working storage with operator scheme, this processor has multiple modes of operation, it is characterized in that, and this device comprises:
One working storage address demoder is in order to the instruction decoding with microprocessor, to produce a decoding output;
At least one first working storage;
Most second working storage;
One selecting arrangement is operator scheme and this decoding output according to this processor, by this at least one first working storage and most second working storages, selects one of them with output.
2. switch the device of working storage in the processor as claimed in claim 1 with operator scheme, it is characterized in that, wherein, this selecting arrangement is according to this decoding output, select one of them by this majority second working storage, and determine whether to select this at least one first working storage according to the operator scheme of this processor, to replace one of this majority second working storage.
3. switch the device of working storage in the processor as claimed in claim 2 with operator scheme, it is characterized in that, wherein, this selecting arrangement comprises:
At least one first multiplex's selector switch, it is according to the operator scheme of this processor, by one of this at least one first working storage and this majority second working storage, selects one of them and exports; And
One second multiplex's selector switch, it is according to this decoding output, by the output of this majority second working storage and this first multiplex (MUX) selector switch, selects one of them and exports.
4. switch the device of working storage in the processor as claimed in claim 1 with operator scheme, it is characterized in that, wherein, this multiple modes of operation comprises: user's operator scheme, core operation pattern and debug operator scheme.
5. switch the device of working storage in the processor as claimed in claim 2 with operator scheme, it is characterized in that, wherein, when this processor during in user's operator scheme and core operation pattern, this selecting arrangement is to select this second working storage.
6. switch the device of working storage in the processor as claimed in claim 2 with operator scheme, it is characterized in that, wherein, when this processor during in the debug operator scheme, this selecting arrangement is to select this first working storage to replace this second working storage.
7. method of switching working storage in processor with operator scheme, this processor have at least one first working storage and most second working storages, and this processor provides multiple modes of operation, it is characterized in that, the method comprising the steps of:
(A) with the instruction decoding of microprocessor, export to produce a decoding; And
(B) be to export,, select one of them with output by this at least one first working storage and most second working storages according to operator scheme and this decoding of this processor.
8. as claim 7 a described method of in processor, switching working storage, it is characterized in that wherein, step (B) comprising with operator scheme:
(B1) according to this decoding output, select one of them by this majority second working storage; And
(B2) according to the operator scheme of this processor, whether decision selects this at least one first working storage, to replace one of this majority second working storage.
9. the method for switching working storage in processor with operator scheme as claimed in claim 7 is characterized in that, wherein, this multiple modes of operation comprises: user's operator scheme, core operation pattern and debug operator scheme.
10. the method for switching working storage in processor with operator scheme as claimed in claim 9 is characterized in that, wherein, in step (B2), when this processor during in user's operator scheme and core operation pattern, is to select this second working storage.
11. the method for switching working storage in processor with operator scheme as claimed in claim 9 is characterized in that, wherein, in step (B2), when this processor during in the debug operator scheme, is to select this first working storage to replace this second working storage.
12. a device that switches working storage in processor with operator scheme, this processor has multiple modes of operation, it is characterized in that, this device comprises:
One working storage address demoder is in order to the instruction decoding with microprocessor, to produce a decoding output;
At least one first working storage;
Most second working storage;
One selecting arrangement is according to the operator scheme of this processor and this decoding output, by the combination of the some of this majority second working storage and this first working storage and one second working storage, selects one of them and exports.
13. the device that in processor, switches working storage as claimed in claim 12 with operator scheme, it is characterized in that, wherein, this selecting arrangement is according to this decoding output, select one of them by this majority second working storage, and according to the operator scheme of this processor, whether decision selects the combination of the some of this first working storage and second working storage, to replace this second working storage.
14. the device that switches working storage in processor with operator scheme as claimed in claim 13 is characterized in that, wherein, this selecting arrangement comprises:
At least one first multiplex's selector switch, it is according to the operator scheme of this processor, by the combination of the some of this first working storage and one second working storage, and one of this second working storage, selects one of them with output; And
One second multiplex's selector switch, it is according to this decoding output, by the output of this majority second working storage and this first multiplex (MUX) selector switch, selects one of them with output.
15. the device that switches working storage in processor with operator scheme as claimed in claim 12 is characterized in that, wherein, this multiple modes of operation comprises: user's operator scheme, core operation pattern and debug operator scheme.
16. the device that switches working storage in processor with operator scheme as claimed in claim 12 is characterized in that, wherein, when this processor during in user's operator scheme and core operation pattern, this selecting arrangement is to select this second working storage.
17. the device that in processor, switches working storage as claimed in claim 12 with operator scheme, it is characterized in that, wherein, when this processor during in the debug operator scheme, this selecting arrangement is the combination of selecting the some of this first working storage and second working storage, to replace this second working storage.
18. a method of switching working storage in processor with operator scheme, this processor have at least one first working storage and most second working storages, this processor provides multiple modes of operation, it is characterized in that, the method comprising the steps of:
(A) with the instruction decoding of microprocessor, export to produce a decoding; And
(B) be according to the operator scheme of this processor and this decoding output,, select one of them and export by the combination of the some of this majority second working storage and this first working storage and one second working storage.
19. the method for switching working storage in processor with operator scheme as claimed in claim 18 is characterized in that, wherein, step (B) comprising:
(B1) according to this decoding output, select one of them by this majority second working storage;
(B2) according to this processor De Shu operation mode, whether decision selects the combination of the some of this first working storage and second working storage, to replace this second working storage.
20. the method for switching working storage in processor with operator scheme as claimed in claim 19 is characterized in that, wherein, this multiple modes of operation comprises: user's operator scheme, core operation pattern and debug operator scheme.
21. the method for switching working storage in processor with operator scheme as claimed in claim 20 is characterized in that, wherein, in step (B2), when this processor during at user's operator scheme and He Xin Shu operation mode, is to select this second working storage.
22. the method for in processor, switching working storage as claimed in claim 20 with operator scheme, it is characterized in that, wherein, in step (B2), when this processor during in the debug operator scheme, be the combination of selecting the some of this first working storage and second working storage, to replace this second working storage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410005334 CN1655116A (en) | 2004-02-11 | 2004-02-11 | Device and method for switching temporary memory according to operation mode in processor |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200410005334 CN1655116A (en) | 2004-02-11 | 2004-02-11 | Device and method for switching temporary memory according to operation mode in processor |
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| CN1655116A true CN1655116A (en) | 2005-08-17 |
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| CN 200410005334 Pending CN1655116A (en) | 2004-02-11 | 2004-02-11 | Device and method for switching temporary memory according to operation mode in processor |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103051297A (en) * | 2011-09-30 | 2013-04-17 | 英特尔移动通信有限责任公司 | Circuit and power amplifier |
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2004
- 2004-02-11 CN CN 200410005334 patent/CN1655116A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103051297A (en) * | 2011-09-30 | 2013-04-17 | 英特尔移动通信有限责任公司 | Circuit and power amplifier |
| CN103051297B (en) * | 2011-09-30 | 2016-08-03 | 英特尔移动通信有限责任公司 | Circuit and power amplifier |
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