CN1645928A - Image storing method for compressing video frequency signal decode - Google Patents
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Abstract
The method includes following steps: the frame image in video sequence is divided into multi pixel blocks that are defined as current pixel window; the memory is allocated for each window; the above window is composed of multi macro blocks, each macro block is 16X16 pixel block; the macro block completing decode is written in, and multi written-in addresses are generated for the above macro block; the each of written in addresses points a different location in memory allocated for the above macro block; when current decoding macro block needs to read out the reference macro block, multi read-out addresses are generated, the reference macro block is read out according to the read-out addresses.
Description
Technical field
The present invention relates to a kind of image storage method that is used for compressing video frequency signal decode, belong to the video decode technical field.
Background technology
MPEG (Motion Picture Experts Group)-2 video compression standard be owing to can provide high compression ratio and high quality graphic under the moderate prerequisite of computational complexity, thereby obtained development energetically in recent years and used widely.The motion estimation algorithm that Moving Picture Experts Group-2 adopts owing to it to a great extent for the compressed capability of moving image, that is: 16 * 16 pixel block is defined as macro block (MB), selected part frame figure from sequence of frames of video and is that unit encodes fully to the pixel data of these reference frames with the macro block as the reference frame in when coding; And when other non-reference frames of coding, also be that unit encodes with the macro block, at first find out the most similar part of current macro correspondence in reference frame during coding, obtain the position of current macro in frame figure and the position of the most similar part in the frame figure displacement of being found between the two---be called motion vector, and current macro to similar between difference-be called residual error, last motion vector and the residual error data that only needs coding to try to achieve.Cooperate discrete cosine transform and entropy coding just can reduce the coded data amount greatly.
But when the code stream that meets the MPEG-2 video compression standard is decoded, must be based on selected reference frame, all video frame images of could correctly decoding.Therefore, in decode procedure, need to preserve maximum two width of cloth reference frames (when bidirectional-movement is predicted) all the time.Except storing reference frame, in decoding, also need to preserve current just decoded frame and the frame that is being shown.Because the data volume of view data is very big, generally can select for use synchronous DRAM (hereinafter to be referred as SDRAM) to preserve above-mentioned frame figure in video decoding system.
When decoded compressed video resolution was very high, for example when decoding HDTV signal, the data throughout of decode system was very big, and this has just proposed very high requirement to the data bandwidth of SDRAM, can reach 3Gbps under the highest situation.Although SDRAM can provide high storage capacity, its internal structure has determined it the sequential of read-write operation to be had the requirement of comparison strictness.Existing method adopts linear mapping to store usually, the line number that is the image pixel data is corresponding with the row address of SDRAM, columns is then corresponding with column address, reading from SDRAM or when wherein writing a macro block, at least need to carry out 15 line feed, this is called disconnected page or leaf (page break) in the operation of SDRAM.Each page or leaf situation that occurs breaking, SDRAM will carry out precharge (precharge) and line activating (row activation) again, every operation all requires to postpone certain clock cycle on sequential (2-3 clock cycle do not waited, the temporal characteristics and the working clock frequency that depend on SDRAM) finish corresponding actions so that wait for memory cell, this just means when running into line feed in reading or writing, and all can cause the certain time sequence waste.And because read or write operation adopts the mode of operation of burst read/write (burstread/write), read or write data line and also only need 2-3 clock cycle.Like this, the sequential that causes of line feed be wasted in ratio shared in the whole memory access process can be up to 50%.Therefore, linear storage mode can cause the bandwidth of memory resource by serious waste, to such an extent as to can not realize correct decoding function, or need use higher clock frequency and more expensive memory device instead.
Summary of the invention
Purpose of the present invention is to propose a kind of image storage method that is used for compressing video frequency signal decode, improves the image storage method in the decode procedure, to overcome the shortcoming of prior art, improves the utilance of bandwidth of memory.
The image storage method that is used for compressing video frequency signal decode that the present invention proposes may further comprise the steps:
(1) two field picture in the video sequence is divided into a plurality of pixel blocks, the definition pixel block is a window, and is each window memory allocated space, and described window consists of a plurality of macro blocks, and each macro block is 16 * 16 pixel block;
(2) write the macro block of finishing decoding, be that described macro block generates a plurality of addresses that write, the described address that writes is pointed to diverse location in the memory space of distributing to described macro block place window separately;
(3) when current decoded macroblock need read reference macroblock, generate a plurality of addresses of reading, read reference macroblock according to reading the address.
Compressed video signal in the said method satisfies the MPEG-2 video standard.
Comprising the steps: for the method in each window memory allocated space described in the said method
(1) described memory space is divided into 4 stores packets, described each stores packets is carried out address decoding, line activating and reading and writing independently of one another;
(2) delegation in the stores packets in the described memory space distributes to a window, and the memory space of distributing to any four adjacent window apertures is four delegation in the mutually different stores packets.
In the said method,, comprise the steps: for described macro block generates a plurality of methods that write the address
(1) determines window under it according to the parameter information of described macro block, and generate and initially write the address, initially write and comprise grouping address, row address and column address in the address;
(2) all pairing grouping address and row addresses that writes in the address of writing unit all are above-mentioned initial packet address and row address in the described macro block;
(3) for the writing unit in the delegation, writing unit the corresponding column address that writes the address from left to right increase progressively;
(4) for the adjacent writing unit of different rows, be to have one between the column address of last writing unit and first writing unit of next line in the delegation greater than 1 fixedly hop value, the number of macroblocks and the stored data bit that are comprised in this hop value and the described window are wide relevant.
In the said method, read the method for address, may further comprise the steps for reference macroblock generates:
(1) determines the window at described reference macroblock place according to the reference information of current decoded macro block, and the address is initially read in generation, the macroblock address, motion vector and the predictive mode that comprise current decoded macro block in the parameter information of described decoded macro block, described parameter information all is comprised in the described compressed video signal, the described address packet that initially reads is drawn together initial packet address, initial row address and initial column address, described initially read point to the described reference macroblock upper left corner in the address reading unit should the memory location;
(2) for described reference macroblock with the adjacent reading unit in the delegation, when described adjacent reading unit does not stride across the vertical direction border of described window, the grouping address of described adjacent reading unit is identical with row address and equal initial packet address and row address, column address increases progressively successively, when described adjacent reading unit strides across the vertical direction border of described window, grouping address saltus step, row address is constant or increase progressively 1, the column address saltus step;
(3) for the adjacent reading unit of different rows in the described reference macroblock, when described adjacent reading unit does not stride across the horizontal direction border of described window, the grouping address is identical with row address and equal initial packet address and row address, the column address saltus step, when described adjacent reading unit strode across the horizontal direction border of described window, grouping address saltus step, row address was constant or saltus step, column address saltus step.
The image storage method that is used for compressing video frequency signal decode that the present invention proposes, its distinguishing feature and effect are, the internal structure of the grouping of generally adopting according to current SDRAM (bank), and at capacity is to adopt the such fact of four grouping (4 banks) structures among the SDRAM more than the 64Mbits usually, adopts the storage mode of piecemeal.The image storage method that the present invention proposes, making does not need to enter a new line in the process of a macro block is read or writes the time in decoding, or the read/write operation of other groupings is overlapping in feasible enter a new line required extra sequential expense and the memory, thereby has improved the utilance of bandwidth of memory.
Description of drawings
Fig. 1 is the SDRAM internal structure schematic diagram that meets the memory space of the inventive method requirement.
Fig. 2 a is the sequential schematic diagram that memory space is read, and wherein the data that read for twice lay respectively in the different groupings.
Fig. 2 b is the sequential schematic diagram that memory space is read, and wherein the data that read for twice lay respectively in the different rows of identical grouping.
Fig. 3 is in the two field picture of one embodiment of the present of invention, the storage organization schematic diagram of macro block data in memory space.
Fig. 4 a is read the storage organization schematic diagram that macro block is positioned at single window.
Fig. 4 b is read macroblock level storage organization schematic diagram transboundary.
Fig. 4 c is read the vertical storage organization schematic diagram transboundary of macro block.
Embodiment
The image storage method that is used for compressing video frequency signal decode that the present invention proposes, comprise: the two field picture in the video sequence is divided into a plurality of pixel blocks, the definition pixel block is a window, and be each window memory allocated space, described window consists of a plurality of macro blocks, each macro block is 16 * 16 pixel block, as shown in Figure 3; Write the macro block of finishing decoding, be that described macro block generates a plurality of addresses that write, the described address that writes is pointed to diverse location in the memory space of distributing to described macro block place window separately; When current decoded macroblock need read reference macroblock, generate a plurality of addresses of reading, read reference macroblock according to reading the address.
Described reference macroblock may stride across a plurality of windows, the described diverse location that reads in the memory space that points to a window distributing to described reference macroblock place or a plurality of windows separately in the address, the described grouping address that comprises memory space in the address of reading, row address and column address, a plurality of pixel datas in the same delegation pixel of described reference macroblock are formed a reading unit, each reading unit reads the address corresponding to one, contained pixel number depends on the data bit width of described memory space in the described reading unit, the number of described reading unit then depends on the quantity of the data bit width and the described window that described reference macroblock strides across in the horizontal direction of described memory space, described reading unit be according to they in described reference macroblock from left to right, sequence arrangement is from top to bottom also read memory space successively.
A plurality of pixel datas in the same delegation pixel of described macro block are formed a writing unit, each writing unit writes the address corresponding to one, the individual number average of contained pixel number and writing unit depends on the data bit width of described memory space in the said write unit, described writing unit be according to they in described macro block from left to right, from top to bottom sequence arrangement and write memory space successively.
Compressed video signal in the said method satisfies the MPEG-2 video standard.
Be the method in each window memory allocated space in the said method, comprise that described memory space is divided into 4 stores packets, and described each stores packets is carried out address decoding, line activating and reading and writing independently of one another; Delegation in the stores packets in the described memory space distributes to a window, and the memory space of distributing to any four adjacent window apertures is four delegation in the mutually different stores packets.
Comprise for described macro block generates a plurality of methods that write the address in the said method, determine window under it, and generate and initially write the address, initially write and comprise grouping address, row address and column address in the address according to the parameter information of described macro block; Pairing grouping address and the row addresses that write in the address of writing unit all in the described macro block all are above-mentioned initial packet address and row address; For with the writing unit in the delegation, writing unit the corresponding column address that writes the address from left to right increase progressively; Adjacent writing unit for different rows, be to have one between the column address of last writing unit and first writing unit of next line in the delegation greater than 1 fixedly hop value, the number of macroblocks and the stored data bit that are comprised in this hop value and the described window are wide relevant.
For generating the method that reads the address, reference macroblock comprises in the said method, determine the window at described reference macroblock place according to the reference information of current decoded macro block, and the address is initially read in generation, the macroblock address that comprises current decoded macro block in the parameter information of described decoded macro block, motion vector and predictive mode, described parameter information all is comprised in the described compressed video signal, the described address packet that initially reads is drawn together the initial packet address, initial row address and initial column address, described initially read point to the described reference macroblock upper left corner in the address reading unit should the memory location; For described reference macroblock with the adjacent reading unit in the delegation, when described adjacent reading unit does not stride across the vertical direction border of described window, the grouping address of described adjacent reading unit is identical with row address and equal initial packet address and row address, column address increases progressively successively, when described adjacent reading unit strides across the vertical direction border of described window, grouping address saltus step, row address is constant or increase progressively 1, the column address saltus step; Adjacent reading unit for different rows in the described reference macroblock, when described adjacent reading unit does not stride across the horizontal direction border of described window, the grouping address is identical with row address and equal initial packet address and row address, the column address saltus step, when described adjacent reading unit strode across the horizontal direction border of described window, grouping address saltus step, row address was constant or saltus step, column address saltus step.
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is elaborated.
Fig. 1 is the internal structure schematic diagram of the SDRAM of the desired memory space of the inventive method, in SDRAM, and four divide into groups shared address and data/address buss, and each grouping has independently row address decoder, column address decoder and sense amplifier.The mode of operation of mode register indication SDRAM comprises burst length, CAS delay, interlace mode or the like.Memory access operation comprises following three steps:
1, use the line activating instruction that certain line data in the designated packet is copied in the sense amplifier of this grouping;
2, use the burst type access instruction from amplifier, to read the data that length equals the indicated burst length of mode register, and data be put on the data/address bus, or to data/address bus put will write memory data; Only change column address and just can operate, and need not to send extra line activating instruction any column unit of the same line storage unit in the designated packet;
3, sense amplifier is carried out precharge, be the ready for operation of other row.
Adopt and the synchronous streamline of external clock because SDRAM is inner, the instruction that therefore is used for different grouping can be overlapped, just can be overlapping with the burst reading command of another grouping such as the line activating instruction of a grouping.As shown in Figure 2, the required clock number of storage operation is with closely related by the memory location of the data of connected reference.In the situation shown in Fig. 2 a, the data that read continuously are stored in respectively in grouping 0 and the grouping 1, therefore just can be overlapping with the instruction RAS00 and the CAS00 of grouping 0 to divide into groups 1 instruction RAS01 that is applied and CAS01.And in the situation shown in Fig. 2 b, the data that read continuously are stored in respectively in grouping two different rows of 0, thereby must wait for the reading command RAS11 of the one group of data in back and CAS11 and just can send after the reading command RAS10 of last group of data and CAS10 finished.Clearly, compare with the situation shown in Fig. 2 a, situation shown in Fig. 2 b has had more extra clock number consumption.The present invention has utilized this sequential characteristics that data on the SDRAM diverse location are carried out connected reference, hereinafter will be elaborated to this in conjunction with the accompanying drawings.
Fig. 3 represents in the two field picture of the present invention that the storage mode of macro block data in memory storage SDRAM, this storage organization are one embodiment of the present of invention.A complete two field picture is divided into the pixel block of plurality of square virtually, a pixel block is called as a window, it is made of four neighboring macro-blocks, because the number of macroblocks of image on level and vertical direction that Moving Picture Experts Group-2 requires to be encoded is even number, even original image is really not so, in coding, also on the position of deficiency, mends and go into remainder certificate.Therefore, must comprise an integer so-called window among a complete frame figure.Suppose that the employing capacity is the memory storage SDRAM that 128Mbit, data bit width 64bit and internal structure are divided into 4 groupings, sort memory can use two capacity to be 64Mbit, data bit width to be the memory storage SDRAM that 32bit and internal structure be divided into 4 groupings and to constitute by parallel, such as MT48LC2M32B2P-7 that can use Micron company or MT48LC2M32B2TG-7.This hypothesis is only made for explanation the present invention, but application of the present invention is not subjected to the restriction of this hypothesis, and method promptly of the present invention is equally applicable to the SDRAM of other specifications.The data total amount that is comprised in the above-mentioned window is 4 * 16 * 16 * 8bit=8192bit, can deposit in just in the line storage unit of the inner grouping of SDRAM.When storing into frame image data in the memory storage SDRAM, four windows that just can level is adjacent with vertical direction deposit in respectively in the same delegation of four different grouping, and other four adjacent window apertures on the horizontal direction are deposited in another row of four different grouping, and the like, till all windows are all deposited in SDRAM.It should be noted that in two field picture level or vertical adjacent any two windows can not be stored in the identical grouping, the reason of doing like this will be illustrated in the explanation hereinafter.
Fig. 4 represents a kind of feasible storage organization.When reading the data of reference macroblock from SDRAM, owing to adopted motion estimation algorithm, the macro block that is read often is not arranged on the macroblock boundaries of two field picture, but relative macroblock boundaries has the side-play amount of a motion vector.Like this, the data of a described reference macroblock just might cover-most reach the scope of 4 macro blocks.Various situations of striding window edge may appear in the reference macroblock that need read, and Fig. 4 shows some kinds of such situations.Hereinafter will describe various window edge situation and the corresponding processing methods of striding in detail in conjunction with Fig. 5.
Fig. 4 a shows the situation that macro block is positioned at single window that is read.In this case, the data of whole macro block all are arranged in the same delegation of same memory grouping, when reading, do not need to change row address, do not need the line activating operation is carried out in other groupings and/or other storage lines yet, and only need the change column address that establishes an equation under the basis:
column_address(0)＝column_counter(0)＝the_first_column_address
column_address(n)＝column_counter(n-1)+Incr1
column_counter(n)＝column_address(n)
Wherein n represents the sequence number of the current unit that is read, when line feed, horizontal direction and/or vertical direction occurring and stride the situation of window, n will be incremented 1, described unit can be the full line data in the macro block, also can be that beginning with certain line data be starting point with the vertical direction border of window is a terminal point, or be the same line data that end up being terminal point of starting point with certain line data with the vertical direction border of window; Column_address is the initial column address that is read the unit; Column_counter is a column counter; The_first_column_address is the current initial column address that is read macro block, the i.e. residing column address in the unit in this macro block upper left corner; Incr1 is the difference between the initial column address of two adjacent unit of vertical direction.This situation itself can not produce disconnected page or leaf phenomenon, does not need to change grouping address and row address when reading.
Illustrated among Fig. 4 b and be read the situation that macro block is crossed over the window edge of vertical direction, this situation is called as level transboundary.In this case, the data of whole macro block may be positioned at the same delegation of different grouping, and this situation is called not disconnected row; Also may be positioned at the different rows of different grouping, this situation is called disconnected row.Will pressing when reading establishes an equation changes grouping address, row address and column address:
bank_address(0)＝bank_counter(0)＝the_first_bank_address
bank_address(n)＝bank_counter(n-1)+1
bank_counter(n)＝bank_counter(n-1)
row_address(0)＝row_counter(0)＝the_first_row_address
column_address(0)＝column_counter(0)＝the_first_column_address
column_address(n)＝column_counter(n-1)-Imod
column_counter(n)＝column_counter(n-1)
Wherein n represents the sequence number of the current unit that is read; Bank_address is the memory grouping that is read the place, unit, and value is one of 0,1,2,3; Bank_counter is the memory packet counter; The_first_bank_address is the start element that is read macro block-be the memory grouping at the place, unit in the upper left corner; Row_address is the row address that is read the place, unit; Bank_counter is a linage-counter; Column_address is the initial column address that is read the unit; The_first_row_address is the current initial row address that is read macro block, the i.e. row at the place, unit in this macro block upper left corner; Column_counter is a column counter; The_first_column_address is the current initial column address that is read macro block; Imod is the distance that the current original position that is read the unit is left its left window vertical boundary.
Fig. 4 c shows and is read the situation that macro block is crossed over the window edge of horizontal direction, and this situation is called as vertically transboundary.Transboundary situation is similar with above-mentioned level, and the data of whole macro block may be positioned at the same delegation of different grouping, also may be positioned at the different rows of different grouping, and both of these case is called disconnected row and disconnected row.Will pressing when reading establishes an equation changes grouping address, row address and column address:
bank_address(0)＝bank_counter(0)＝the_first_bank_address
bank_address(n)＝bank_counter(n-1)+2
bank_counter(n)＝bank_address(n)
row_address(0)＝row_counter(0)＝the_first_row_address
row_counter(n)＝row_address(n)
column_address(0)＝column_counter(0)＝the_first_column_address
column_address(n)＝column_counter(n-1)+Incr2
column_counter(n)＝column_address(n)
Wherein n represents the sequence number of the current unit that is read; Bank_address is the memory grouping that is read the place, unit, and value is one of 0,1,2,3; Bank_counter is the memory packet counter; The_first_bank_address is the start element that is read macro block, i.e. the memory at the place, unit in upper left corner grouping; Row_address is the row address that is read the place, unit; Bank_counter is a linage-counter; Column_address is the initial column address that is read the unit; The_first_row_address is the current initial row address that is read macro block, the i.e. row at the place, unit in this macro block upper left corner; Column_counter is a column counter; The_first_column_address is the current initial column address that is read macro block; Hrow is read poor between the row address of different rows at the adjacent two row places of vertical direction in the macro block, and this value depends on the specification of image size and memory storage SDRAM; Incr2 is read column address poor of unit for two of being separated by the horizontal boundary of window.
If current macro is carried out the operation of write memory SDRAM, then at first calculate the first address that current macro should be deposited in according to described macroblock address, comprise the address of row, column and memory grouping in the first address, described first address depends on the macroblock address of the resolution sizes and the current macro of image.Because storage means of the present invention is that whole macro block is stored in the same delegation of same grouping, in writing, need not change row address and memory grouping address, and each line data that only is required to be current macro changes the column address of storage and gets final product.Under the situation of the SDRAM memory of above-mentioned employing 128Mbit capacity 64bit data bit width, the column address that writes of back delegation is that previous row writes column address and adds 4, that is:
column_address(n)＝column_address(n-1)+4
Claims (5)
1, a kind of image storage method that is used for compressing video frequency signal decode is characterized in that this method may further comprise the steps:
(1) two field picture in the video sequence is divided into a plurality of pixel blocks, the definition pixel block is a window, and is each window memory allocated space, and described window consists of a plurality of macro blocks, and each macro block is 16 * 16 pixel block;
(2) write the macro block of finishing decoding, be that described macro block generates a plurality of addresses that write, the described address that writes is pointed to diverse location in the memory space of distributing to described macro block place window separately;
(3) when current decoded macroblock need read reference macroblock, generate a plurality of addresses of reading, read reference macroblock according to reading the address.
2, the method for claim 1 is characterized in that described compressed video signal satisfies the MPEG-2 video standard.
3, the method for claim 1 is characterized in that wherein saidly comprising the steps: for the method in each window memory allocated space
(1) described memory space is divided into 4 stores packets, described each stores packets is carried out address decoding, line activating and reading and writing independently of one another;
(2) delegation in the stores packets in the described memory space distributes to a window, and the memory space of distributing to any four adjacent window apertures is four delegation in the mutually different stores packets.
4, the method for claim 1 is characterized in that wherein said is that a plurality of methods that write the address of described macro block generation comprise the steps:
(1) determines window under it according to the parameter information of described macro block, and generate and initially write the address, initially write and comprise grouping address, row address and column address in the address;
(2) all pairing grouping address and row addresses that writes in the address of writing unit all are above-mentioned initial packet address and row address in the described macro block;
(3) for the writing unit in the delegation, writing unit the corresponding column address that writes the address from left to right increase progressively;
(4) for the adjacent writing unit of different rows, be to have one between the column address of last writing unit and first writing unit of next line in the delegation greater than 1 fixedly hop value, the number of macroblocks and the stored data bit that are comprised in this hop value and the described window are wide relevant.
5, the method for claim 1 is characterized in that wherein saidly may further comprise the steps for reference macroblock generates the method read the address:
(1) determines the window at described reference macroblock place according to the reference information of current decoded macro block, and the address is initially read in generation, the macroblock address, motion vector and the predictive mode that comprise current decoded macro block in the parameter information of described decoded macro block, described parameter information all is comprised in the described compressed video signal, the described address packet that initially reads is drawn together initial packet address, initial row address and initial column address, described initially read point to the described reference macroblock upper left corner in the address reading unit should the memory location;
(2) for described reference macroblock with the adjacent reading unit in the delegation, when described adjacent reading unit does not stride across the vertical direction border of described window, the grouping address of described adjacent reading unit is identical with row address and equal initial packet address and row address, column address increases progressively successively, when described adjacent reading unit strides across the vertical direction border of described window, grouping address saltus step, row address is constant or increase progressively 1, the column address saltus step;
(3) for the adjacent reading unit of different rows in the described reference macroblock, when described adjacent reading unit does not stride across the horizontal direction border of described window, the grouping address is identical with row address and equal initial packet address and row address, the column address saltus step, when described adjacent reading unit strode across the horizontal direction border of described window, grouping address saltus step, row address was constant or saltus step, column address saltus step.
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| CN111538677A (en) * | 2020-04-26 | 2020-08-14 | 西安万像电子科技有限公司 | Data processing method and device |
| CN111831212A (en) * | 2019-04-19 | 2020-10-27 | 杭州海康威视数字技术股份有限公司 | Data writing and reading method, device and equipment |
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| CN101483743B (en) * | 2009-01-19 | 2011-03-30 | 凌阳科技股份有限公司 | Data access apparatus and method |
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| WO1994018799A1 (en) * | 1993-02-03 | 1994-08-18 | Qualcomm Incorporated | Interframe video encoding and decoding system |
| FR2719398B1 (en) * | 1994-04-27 | 1996-07-19 | Sgs Thomson Microelectronics | Device and method for addressing a cache memory of a mobile image compression circuit. |
| FR2723796B1 (en) * | 1994-08-19 | 1996-11-29 | Thomson Consumer Electronics | MOTION ESTIMATION DEVICE |
| FR2742248B1 (en) * | 1995-12-06 | 1998-01-23 | Thomson Multimedia Sa | METHOD FOR PROCESSING DATA IN MATRIX NETWORKS IN A MOTION ESTIMATION SYSTEM |
| JPH09312774A (en) * | 1996-05-21 | 1997-12-02 | Matsushita Electric Ind Co Ltd | Image data encoder |
| US5793985A (en) * | 1996-06-17 | 1998-08-11 | Hewlett-Packard Company | Method and apparatus for block-based motion estimation |
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| CN1949826B (en) * | 2005-10-12 | 2010-06-23 | 宏正自动科技股份有限公司 | Digital image data processor |
| CN101527849B (en) * | 2009-03-30 | 2011-11-09 | 清华大学 | Storing system of integrated video decoder |
| CN102281390A (en) * | 2010-06-11 | 2011-12-14 | 索尼公司 | Image processing apparatus and image processing method |
| CN101990102A (en) * | 2010-11-09 | 2011-03-23 | 福州瑞芯微电子有限公司 | Data reading method and device on embedded equipment in video decoding process |
| CN101990102B (en) * | 2010-11-09 | 2013-07-24 | 福州瑞芯微电子有限公司 | Data reading method and device on embedded equipment in video decoding process |
| CN107392838A (en) * | 2017-07-27 | 2017-11-24 | 郑州云海信息技术有限公司 | WebP compression parallel acceleration methods and device based on OpenCL |
| CN107392838B (en) * | 2017-07-27 | 2020-11-27 | 苏州浪潮智能科技有限公司 | WebP compression parallel acceleration method and device based on OpenCL |
| CN111831212A (en) * | 2019-04-19 | 2020-10-27 | 杭州海康威视数字技术股份有限公司 | Data writing and reading method, device and equipment |
| CN111538677A (en) * | 2020-04-26 | 2020-08-14 | 西安万像电子科技有限公司 | Data processing method and device |
| CN111538677B (en) * | 2020-04-26 | 2023-09-05 | 西安万像电子科技有限公司 | Data processing method and device |
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