CN1636322A - Digital to analogue converting device - Google Patents
Digital to analogue converting device Download PDFInfo
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- CN1636322A CN1636322A CNA008101094A CN00810109A CN1636322A CN 1636322 A CN1636322 A CN 1636322A CN A008101094 A CNA008101094 A CN A008101094A CN 00810109 A CN00810109 A CN 00810109A CN 1636322 A CN1636322 A CN 1636322A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/68—Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/662—Multiplexed conversion systems
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/82—Digital/analogue converters with intermediate conversion to time interval
- H03M1/822—Digital/analogue converters with intermediate conversion to time interval using pulse width modulation
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Abstract
The invention relates to a digital to analogue converting device comprising a converting step establishing an upper (UL) and a lower voltage level (LL) in dependency of at least one digital input signal (DIS), said upper (UL) and lower voltage levels (LL) being time-modulated in dependency of at least said digital input signal (DIS) into a time-modulated output signal (TMOS), said time-modulated output signal having a period (T), said time-modulated output signal being fed through an output stage comprising at least one integrator (I), said integrator (I) being dimensioned in such a way that said time-modulated output signal is filtered and converted into an analogue representation of said digital input signal (DIS). According to the invention, a high-bit low-cost D/A-converter having small non-linearities has been obtained.
Description
Technical field
The present invention relates to according to claim 1,10, a kind of digital to analog converter of 12 and 14, according to claim 15 and 18 produce a kind of method of at least one time modulated output signal, according to a kind of multistage digital to analog converter of claim 20 and according to the purposes of claim 22 and 23.
Background technology
In for example instrument and meter or field of telecommunications, the high definition digital to analog converter must have low DNL and integral nonlinearity.At high temperature must keep these linear requirements.
Traditional problem quick, low-cost digital to analog converter is that nonlinear problem is quite outstanding, and in fact these non-linear natures limited the use of higher bit transducer, because the increase of bit number can improve the DNL of least significant bit.For obtaining in high definition, digital to analog converter is introduced fast several technology, there is a kind of technology mainly to comprise two independent digit weighted-voltage D/A converters, one of them is used to produce the highest effective simulation part of digital input signals, and another is used to produce the low live part of analog signal.At last, two analog signals are superimposed in the simulation adder stage.Nature, this method can be brought the transducer matching problem and cause the DNL of transducer more serious.
The purpose of this invention is to provide a kind of have less nonlinear higher bit, digital to analog converter cheaply.
The present invention's general introduction
Just according to claim 1, a kind of digiverter comprises:
At least a switch process that produces a high-voltage level (UL) and a low voltage level (LL) according to a digital input signals (DIS),
Described high-voltage level (UL) and low voltage level (LL) are modulated to a time modulated output signal (TMOS) according to described digital input signals (DIS) by the time at least,
Described time modulated output signal has one-period (T),
Described time modulated output signal is presented by an output stage that comprises at least one integrator (I),
Described integrator (I) is provided with by this way, makes that described time modulated output signal is filtered and is converted into the analog representation of described digital input signals (DIS), thereby realize a kind of preferred digital to analog converter.
According to the present invention,, thereby can reach low-cost and high integrated owing to the requirement that has reduced laser trimming and special-purpose silicon processing procedure.
When as described in claim 2, when described time modulated output signal (TMOS) is a pwm signal, can realize the preferred embodiments of the present invention.
If as described in claim 3, described high-voltage level and low voltage level (UL, LL) be to produce by a digital MUX who controls DAC, described MUX walks abreast by this way by digital input signals or presents serially, make the numeral output of this MUX control DAC continuously, and produce first analog signal that comprises a high-voltage level (UL) and a low voltage level (LL) according to DAC output, then can realize another preferred embodiment of the present invention.
If as described in claim 4, described high-voltage level and low voltage level (UL, LL) produce by special-purpose DAC (DAC1, DAC2), each special-purpose DAC produces analog output signal (UL, LL) according to the digital signal that is fed to described special-purpose DAC, described analog signal is analog representation, undertaken multiplexingly by a switch, can realize another preferred embodiment of the present invention to form described first analog signal (AS1).
If as described in claim 5, high level and low level signal (UL, LL) are created as analogue value UL=LL+nLSB, n=1 wherein, 2,3, ..., then can realize a kind of preferred amplitude modulation, because can between two comparable modulation levels, modulate to this output signal to described time modulated output signal (TMOS).Like this, the time modulation can produce a kind of decomposable process based on the LSB deviation.This decomposable process can be modulated by for example a kind of relative low level PWM and produce, because utilized low voltage level LL to produce the first of this signal.Like this, owing to being compressed 2 for the required PWM modulator clock cycle of each decomposable process that produces by generation high level and low level signal
nTimes, thereby can carry out the PWM modulated process very apace.
If it is, carry out careful selection, then relatively slow but can produce inferior decomposable process for linear PWM modulator according to low nonlinearity to producing the least significant bit of high level and low level relative digital to analog converter fast.
Like this,, produce high level and low level, in these 10 D/A converters, have only 8 to be used to produce required level by a kind of 10 traditional D/A converters according to a kind of 13 embodiment of the present invention.Two least significant bits are because unacceptable non-linear and deleted.Modulate carrying out PWM between following two signals of 8 signals that obtained: a low level signal, promptly most probable is near the approximation of 8 bit pads; Add this signal of least significant bit, promptly add the 8th.PWM produces 5 decomposed signals and it is added on this low level signal.Therefore, obviously improved the linearity that high-order accurate transducer reached.
Obviously, should cautiously be provided with a kind of D/A converter according to the present invention, because this set is a kind of balance between, decomposing force non-linear such as accepting, dynamic range and these parameters of conversion speed according to current applicable cases.
Even want careful selection to realize the digital to analog converter of amplitude modulation, because for example can adopt a kind of high-quality digital to analog converter, replace the delete procedure that carries out above-mentioned least significant bit fully.
If as described in claim 6, MUX and DAC are synchronous, then can realize another preferred embodiment of the present invention.Can obviously improve the linearity synchronously between multiplexer and the digital to analog converter.
If as described in claim 7, described integrator (I) comprises a low pass filter, can realize another preferred embodiment of the present invention.Therefore, can produce inexpensive low pass filter.
Should be noted that within the scope of the present invention the filter that can also use other type is as output stage, or a kind of filter is carried out multiple modification.。
If as described in claim 8, when described time modulated output signal (TMOS) is created as the Fractional-N frequency signal, then can realize another preferred embodiment of the present invention, because the low frequency modulations to the time modulated output signal can be converted to more high frequency.
If as described in claim 9, described integrator (I) is set to a low pass filter that has the cycle (T) ≈ τ, wherein τ is the time constant RC of integrator (I), R is a resistance, C is an electric capacity, then can realize another preferred embodiment of the present invention, this modulation that has benefited from being caused by coding has been transferred to more high frequency.Therefore, the time constant of output filter can shorten to about 1 cycle from for example 10 times modulation period time.
Should be noted that the integrator in the scope of the invention is a kind of filter with expection integral characteristic, because the integrator that can not realize ideal.
Utilization has the filter of integral characteristic, for example low pass filter or band pass filter), can realize according to a kind of integrator of the present invention.
If by this way described time modulated output signal is not regulated, make the low frequency part of described time modulation signal be lowered to minimum, then time constant is preferably near 10 times less than the time cycle.
If as described in claim 10, a kind of digiverter comprises the switch process that produces a high-voltage level (UL) and a low voltage level (LL) at least according to a digital input signals (DIS), described high-voltage level (UL) is fed to the input of a DAC, described low voltage level (LL) is fed to the input of the 2nd DAC, wherein the output signal of a described DAC is fed to the first input end of time modulation output stage, the output signal of described the 2nd DAC is fed to second input of described time modulation output stage, and the described first input end of wherein said output stage and the input impedance of second input are basic identical, then can realize according to a preferred embodiment of the present invention.
Term " output stage " means the output circuit of any kind that can present DAC.An example is one or more filters that comprise resistive element and/or capacity cell.Another example is the time modulation switch circuit of any kind.
If as described in claim 11, the described first input end of described output stage is identical with the input impedance of second input, then can produces its output signal and remain dull digital to analog converter.
If as described in claim 12, digiverter comprises the switch process that produces high-voltage level (UL) and low voltage level (LL) at least according to a digital input signals (DIS), described high-voltage level (UL) is fed to the input of a DAC, described low voltage level (LL) is fed to the input of the 2nd DAC, wherein the output signal of a described DAC is fed to the first input end of time modulation output stage, the output signal of described the 2nd DAC is fed to second input of described time modulation output stage, and the difference between the described first input end of wherein said output stage and the input impedance of second input less than+/-40%, and preferably less than+/-5%, then can realize according to a further advantageous embodiment of the invention.Especially, preferably the intermittence with output signal is reduced to minimum.
Term " 40% " and " 5% " mean corresponding to the relative difference between the impedance of one of used impedance (the preferably less impedance of resistance value).
If as described in claim 13, the described first input end of described output stage and the impedance difference between second input are 0, then can produce its output signal and remain dull digital to analog converter.
If as described in claim 14, digiverter comprises the switch process that produces high-voltage level (UL) and low voltage level (LL) at least according to relevant digital input signals (DIS), described high-voltage level (UL) is fed to the input of a DAC, described low voltage level (LL) is fed to the input of the 2nd DAC, wherein the output signal of a described DAC is fed to the input of resistor network, the output signal of described the 2nd DAC is fed to the input of described resistor network, the input of described resistor network, can be produced its output signal and remains dull digital to analog converter when public by the output signal of a described DAC and the 2nd DAC.This is because the apparent impedance of two DAC is identical.
Term " public " means that the output signal of two DAC is connected to a common input node in the resistor network, perhaps is connected to two isolated nodes short circuit in a known way or basic short circuit.
Term " resistance " means one or more resistance, perhaps the combination of resistance, electric capacity and/or inductance.
If as described in claim 15, a kind of method produces at least one time modulated output signal (TMOS) according to a digital input signals, described digital input signals (DIS) and described output signal at least, can obtain to utilize the preferred embodiment of the time modulated output signal with commercial value component.Described output signal comprises the basic fixed cycle (Tp), in this fixed cycle, at least produce output amplitude as high-voltage level (UL) or low voltage level (LL) or other voltage level, by described supplied with digital signal (DIS) determine the to have output amplitude time modulated output signal (TMOS) of (0A), and at particular conversion time (Ts), according to described digital input signals (DIS), at least between described high-voltage level (UL) and low voltage level (LL), change described time modulated output signal (TMOS), this method provides to produce has the possibility of low-down nonlinear high definition digital to analog converter.
Brief description of drawings
Describe the present invention in detail hereinafter with reference to accompanying drawing, wherein:
Fig. 1 shows the linear number weighted-voltage D/A converter of prior art;
Fig. 2 shows first and preferred embodiment according to a kind of D/A converter of the present invention;
Fig. 3 shows another embodiment according to a kind of digital to analog converter of the present invention;
Fig. 4 shows the output waveform figure of digital to analog converter shown in Figure 2;
Fig. 5 shows the process of presenting of numeral input;
Fig. 6 shows the composition of analog output signal;
Fig. 7 a to Fig. 7 c shows a kind of method of converted output signal.
Describe in detail
Fig. 1 shows the example of the high n figure place weighted-voltage D/A converter of prior art.
By shown in the digital to analog converter method that obtains a large amount of bits can be used in the instrument and meter transformation applications.
This transducer comprises two digital to analog converters, i.e. 10 figure place weighted-voltage D/A converters 11 and 5 figure place weighted-voltage D/A converters 12.These two digital to analog converter mutual calibrations by this way, promptly transducer 11 is determined the highest significant position component of signal, and transducer 12 produces the least significant bit component of signal.Utilize amplifier to make two Signal Matching and finally summation in sum unit 15.
The advantage of above-mentioned technology is, decomposing force height, fast and not free delay of conversion speed.
The problem of above-mentioned prior art transducer is, those two transducers are matched each other, and this matching process means calibration process consuming time.In addition, careful calibration process is not estimated each transducer non-linear and is adopted expensive device.
Fig. 2 illustrates the preferred embodiment of the present invention that comprises two the digital input register REG of parallel connection H 21 and REG L 22.The numeral and the signal of register 21 and 22 outputs are fed to digital MUX 23.The numeral output of MUX 23 is fed to DAC 24.According to the numeral input that is input to analog band-pass filter 26, DAC 24 output analog signals.
In addition, this transducer also comprises register 27, register 27 control PWM modulators 25, PWM modulator 25 control MUX and DAC 24.
The function of digiverter is, given digital multibit signal is fed to register 27,21 and 22.By this way multibit signal is divided into sub-segmentation, so that can obtains the particular requirement decomposing force.REG 21 determines the high-voltage level (UL) of digital to analog converter 24 pulse that produces, and the low voltage level (LL) that REG 22 determines according to the pulse that output produces of digital to analog converter 24.
Utilize PWM 25,, high-voltage level (UL) signal and low voltage level (LL) signal are carried out the time modulation according to the content of REG 27.Carry out the PWM modulated process with fixed time period Tp.
The output waveform of digital to analog converter is shown in Fig. 4, wherein represents the PWM cycle with Tp.Period T p is subdivided into several clock cycle.According to shown in embodiment, the fixed cycle of PWM modulated process comprises 4 clock cycle Tclock.Therefore, PWM can realize effective 2 modulated processs.
Therefore, according to illustrated embodiment, the output of digital to analog converter 24 comprises amplitude modulation high-voltage level signal component and the low voltage level signal component of being determined by REG 21 and REG22 generation, simultaneously according to REG 27, utilizes PWM modulator 25 to carry out the time modulation.This modulation adopts digital method to control.
Fig. 3 illustrates another preferred embodiment of the present invention, and wherein modulated process is the analog-modulated process, but controls with digital method.
This digital to analog converter comprises 3 digital input register REG 31, REG 32 and REG33.REG 31 control digital to analog converters 36, REG 32 control digital to analog converters 37.
Each digital to analog converter produces high-voltage level UL and low voltage level LL respectively.
REG 33 control PWM modulators 38 utilize analog switch 39, PWM modulator 38 control simulation multiplexers.
Now, with reference to figure 3 and Fig. 4, under the control of REG 31 and REG 32, two digital to analog converters produce high-voltage level UL and low voltage level LL, and when under the control of REG 38, when changing between high-voltage level and low voltage level, PWM modulator 38 is realized PWM time modulated process.During fixed cycle Tp, between high-voltage level and low voltage level, change and can modulate the signal that is fed to output band pass filter 34, in output band pass filter 34, produce analog signal.Be arranged in such a way band pass filter 34, so that it makes fixed cycle Tp and possible signal level coupling.
In Fig. 4,, between high-voltage level UL and low voltage level LL, signal is modulated at each time transfer point Ts.
In Fig. 4, utilize Tp to represent each modulation period, and each period T p contain 4 clock cycle Tclk.Each, Tp contained one, two, three or four high level clock cycle Tclk substantially modulation period, and they produce 25%, 50%, 75% and 100% corresponding modulation level respectively.
Should be noted that high-voltage level UL and low voltage level LL are very approaching, i.e. for example 2.755V and 2.750V.
With reference now to Fig. 5,, Fig. 5 shows the basic step according to digital to analog converter cataloged procedure of the present invention.
Shown content is corresponding to the preferred embodiments of the present invention.Obviously, the scope of the invention is not limited to illustrated embodiment.
51 expressions of 13 bit digital are fed to the numeral according to 13 figure place weighted-voltage D/A converters of the present invention.Then, these 13 signals are split as two 8 signals and be fed to two register R1 and R2.8 highest significant positions of 13 inputs 51 of register R2 storage.The incremental representation of 8 highest significant positions of 13 inputs 51 of register R1 storage, i.e. the numerical value in the register R1 and the least significant bit addition of register 51.In another preferred embodiment of the present invention, get least significant bit 8 highest significant positions in storing register R1 into.Content in the register R1 produces high-voltage level UL, and the content of register R2 produces low voltage level LL.
Minimum 5 with 13 signals are fed to register R3.
Get back to Fig. 6 now, basic comprehension to two-stage modulated process of the present invention is described with reference to figure 5.In order to say something, pwm signal to be shown 2 signals, and not to be shown 5 signals.
In Fig. 6, an axle A illustrates, according to the PWM position, as the function of the PWM modulated process of UL and LL, according to the simulation output of digital to analog converter of the present invention.
Register R1 and R2 produce high-voltage level UL and low voltage level LL.Low level can be regarded as the modulation of blocking, be about to 5 least significant bits and put 0 13 signals 51.This means basically, in fact can regard interior 8 signals of register R2 that are stored in that produce like this as 13 deleted signals of its 5 least significant bits.Therefore, the analog equivalent signal of register R2 is equal to or less than 13 signals of simulation of requirement.The analog signal of the analog signal of 5 least significant bits of necessary adjunct register R3 to obtain to require.
In this embodiment, utilize the least significant bit of 8 signals in the R2, R1 is carried out " adding ".Difference between UL and the LL is represented the least significant bit of the most-significant byte of 13 signals.Utilization is determined additional signal to the modulated process that the UL that is higher than LL carries out.In Fig. 6, reduce to 2 with 5 in the register R3, to show the function of this PWM modulated process.
If minimum 5 (diagrams: 2) in the register R3 are 0, UL can be modulated 0%, promptly modulated numerical value is corresponding to LL, and if minimum 5 (diagrams: 2) be 01, then modulated numerical value will add 25% of difference between UL and the LL corresponding to LL, i.e. simulation output=LL+ (UL-LL)/4.
If we get back to 8+5 embodiment shown in Figure 5, when then in output filter, carrying out integration, simulation PWM output Va=LL+ (UL-LL) * (r3/Rn), wherein r3 is the currency of register R3 memory contents, and Rn is 2
5
Therefore, traditional digital to analog converter produces high level and low level, and between the least significant bit of traditional digital to analog converter, PWM modulates the high definition component.
Get back to Fig. 7 now, Fig. 7 illustrates the method that conventional P WM output signal is converted to the Fractional-N frequency signal.
The basic problem of conventional P WM signal is that PWM contains undesirable low frequency component, because signal is carried out the PWM coding.
Fig. 7 a illustrates the period T p of pulse-width modulation PWM signal.Produce this signal by period T p with 6 clock cycle.From 1 to 6 pair of each clock cycle is numbered.
Shown signal contains the DC signal of the output filter that is fed to transducer.In addition, this signal obviously can produce the low frequency modulations process that lowest modulation frequency is 1/Tp.Because Tp is higher, so will modulate in the low-frequency range of frequency band.
When in the output integrator signal being carried out filtering, cut-off frequency must be very near DC, and low-pass characteristic must be sharp-pointed.
So just require to export integrator and have very high performance, therefore, the cost height is set.Take, should be noted that the requirement to sharp-pointed filter characteristic causes the very slow response time.
Therefore, the timeconstant of integrator is about 10 times of period T p of pwm signal.
When utilizing following technology, reduced the output filter spectrum requirement, and time window can be reduced to and be low to moderate Tp, be i.e. τ ≈ Tp.
Can determine the output of integrator with less time constant.
Now, with reference to figure 7a, the output valve that should be noted that requirement is the V as a result that appears on the output filter
DcValue.Utilize the V during dotted line VDC illustrates period T p
Dc
Fig. 7 b illustrates and the pwm signal shown in Fig. 7 a is converted to the first step that has the higher frequency component, still keeps the signal of DC value during Tp.
At first, determine high level number and low level number.If the low level signal number is less than the high level signal number, then the first step is the step shown in Fig. 7 b, and is positioned at last 6 low levels of position 11 to 16 and will be respectively moves to position 2,4,6,8,10 and 12 from the end of period T p.The DC value that keeps this cycle.
This cycle still 13 to 16 is contained high level pulse in the position.
In Fig. 7 c, because last 4 positions 13 to 16 are subdivided into two time cycles of two Tclock, so further shortened the low frequency modulations process that the end at period T p carries out high level signal.Subsequently, the position 13 and 14 shown in Fig. 7 b moves to reposition 3 and 4, and the position 15 and 16 shown in Fig. 7 b moves to reposition 7 and 8.Should be noted that the DC value that still needs during the hold period Tp.
Claims (23)
1. digiverter, this digiverter comprises:
At least produce the switch process of high-voltage level (UL) and low voltage level (LL) according to a digital input signals (DIS);
At least according to described digital input signals (DIS), described high-voltage level (UL) and low voltage level (LL) time are modulated to time modulated output signal (TMOS);
Described time modulated output signal has the cycle (T);
By comprising the output stage of an integrator (26,34) at least, present described time modulated output signal;
Be arranged in such a way described integrator (26,34), so that described time modulated output signal is carried out filtering and it is converted to the analog representation of described digital input signals (DIS).
2. digiverter according to claim 1, wherein said time modulated output signal (TMOS) is a pwm signal.
3. digiverter according to claim 1 and 2, wherein utilize the digital MUX (23) of control DAC (24) to produce described high level (UL) and low level (LL), in parallel with digital input signals (DIS) the by this way or described MUX of series-feed, i.e. the numeral of MUX output continuous control DAC also produces the high level (UL) that comprises DAC output and the time modulated output signal (TMOS) of low level (LL).
4. digiverter according to claim 1 and 2, wherein utilize special-purpose digital to analog converter (36,37) produce described high level (UL) and low level (LL), each according to the digital signal generation analog output signal (UL that is fed to described special-purpose DAC, LL), utilize the multiplexing described analog signal of switch (39) simulation to produce described time modulated output signal (TMOS).
5. according to the described digiverter of claim 1 to 4, wherein produce high level signal and low level signal (UL, LL) as the analogue value, UL=LL+nLSB, n=1 wherein, 2,3....
6. according to the described digiverter of claim 1 to 5, wherein MUX and DAC are synchronous.
7. according to the described digiverter of claim 1 to 6, wherein said integrator (I) comprises band pass filter.
8. according to the described digiverter of claim 1 to 7, wherein produce described time modulated output signal (TMOS) as the Fractional-N frequency signal.
9. digiverter according to claim 8 wherein is set to period T＜5 with described integrator (I), the band pass filter of T ≈ τ preferentially, and wherein τ is the time constant RC of integrator, and R is a resistance, and C is an electric capacity.
10. digiverter, this digiverter comprises:
At least produce the switch process of high-voltage level (UL) and low voltage level (LL) according to a digital input signals (DIS);
Described high-voltage level (UL) is fed to the input of a DAC, and described low voltage level (LL) is fed to the input of the 2nd DAC;
Wherein the output signal of a described DAC is fed to the first input end of time modulation output stage, the output signal of described the 2nd DAC is fed to second input of described time modulation output stage, and
The described first input end of wherein said output stage and the input impedance of second input are basic identical.
11. digiverter according to claim 10, the described first input end of wherein said output stage is identical with the input impedance of second input.
12. a digiverter, this digiverter comprises:
At least according to a digital input signals (DIS), produce the switch process of high-voltage level (UL) and low voltage level (LL);
Described high-voltage level (UL) is fed to the input of a DAC, described low voltage level (LL) is fed to the input of the 2nd DAC;
Wherein the output signal of a described DAC is fed to the first input end of time modulation output stage, the output signal of described the 2nd DAC is fed to second input of described time modulation output stage, and
Difference between the described first input end of wherein said output stage and the input impedance of second input less than+/-40%, and preferentially less than+/-5%.
13. digiverter according to claim 12, the difference of described first output of wherein said output stage and the input impedance of second output is 0.
14. a digiverter, this digiverter comprises:
At least produce the switch process of high-voltage level (UL) and low voltage level (LL) according to a digital input signals (DIS);
Described high-voltage level (UL) is fed to the input of a DAC, and described low voltage level (LL) is fed to the input of the 2nd DAC,
Wherein the output signal of a described DAC is fed to the input of resistor network, the output signal of described the 2nd DAC is fed to the input of described resistor network.And
The input of wherein said resistor network is public by the output signal of a described DAC and the 2nd DAC.
15. one kind at least according to a digital input signals, described digital input signals (DIS) and described output signal, produces the method for a time modulated output signal (TMOS) at least,
Described output signal comprises the basic fixed cycle (Tp), in this fixed cycle, produces output amplitude at least as high-voltage level (UL) or low voltage level (LL) or other voltage level,
By described supplied with digital signal (DIS) determine the to have output amplitude time modulated output signal (TMOS) of (0A),
And,, between described high-voltage level (UL) and low voltage level (LL), change described time modulated output signal (TMOS) at least according to described digital input signals (DIS) at particular conversion time (Ts).
16. the method that produces an output signal at least according to claim 15, wherein said digital input signals (DIS) has total bit (TN), wherein
The content of a plurality of (N) highest significant position of described digital input signals (DIS) is determined described low level (LL), and
Wherein a least significant bit is appended to the described content of determining described high level (UL), and wherein
The content of all the other positions (M=TN-N) produces M bit time modulated process.
17. according to claim 15 or the 16 described methods that produce an output signal at least, a wherein said least significant bit is the least significant bit that is used for the content of definite described high level (UL).
18. one kind at least according to a digital input signals, produces the method for an output signal at least, described digital input signals (DIS) comprises
In the basic fixed cycle (Tp), in this fixed cycle, between high-voltage level (UL) and low voltage level (LL), produce output amplitude, perhaps as described high-voltage level (UL) or described low voltage level (LL);
Utilize described supplied with digital signal (DIS) determine the to have output amplitude time modulated output signal (TMOS) of (OA);
And,, between described high-voltage level (UL) and low voltage level (LL), change described time modulated output signal (TMOS) at least according to described digital input signals (DIS) at particular conversion time (Ts).
19. according to the described method that produces an output signal at least of claim 15 to 18, wherein by at least one cycle (Tp) described output signal is carried out integration, described integrated signal is the analog representation of described digital input signals (DIS).
20. a multistage digital to analog converter, this multistage digital to analog converter comprises:
Be used for digital input signals is converted to the device of time modulation signal;
Being used for described time modulation signal integral and calculating is the device of analog output signal;
The described device that is used for digital input signals is converted to the time modulation signal comprises the device that produces described time modulation signal by this way, and the low frequency component that is about to described time modulation signal is reduced to minimum device.
21. multistage digital to analog converter according to claim 20 wherein produces the described device of described time modulation signal in this manner, the low frequency component that is about to described time modulation signal is reduced to minimum device and comprises the N distributor.
22. in voice applications, using according to the described digiverter of claim 1 to 14, according to the one or more claims in the claim 15 to 19, produce the method for a time modulated output signal at least and/or according to the multistage digital to analog converter of the one or more claims in the claim 20 to 21.
23. in such as the communication equipment of mobile phone, use according to the described digiverter of claim 1 to 14, according to the one or more claims in the claim 15 to 19, produce the method for a time modulated output signal at least and/or according to the multistage digital to analog converter of the one or more claims in the claim 20 to 21.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DKPA199901006 | 1999-07-09 | ||
| DK199901006A DK199901006A (en) | 1999-07-09 | 1999-07-09 | Digital to analog conversion device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1636322A true CN1636322A (en) | 2005-07-06 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA008101094A Pending CN1636322A (en) | 1999-07-09 | 2000-07-10 | Digital to analogue converting device |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP1208647A2 (en) |
| CN (1) | CN1636322A (en) |
| AU (1) | AU5806500A (en) |
| DK (1) | DK199901006A (en) |
| WO (1) | WO2001005036A2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101242186B (en) * | 2008-03-18 | 2010-10-06 | 苏州纳米技术与纳米仿生研究所 | A programmable non linear digital/analog converter |
| CN106323391A (en) * | 2015-06-30 | 2017-01-11 | 株式会社堀场Stec | Flow rate measuring device and flow rate controlling device |
| CN107846221A (en) * | 2017-11-02 | 2018-03-27 | 深圳市太铭科技有限公司 | A kind of method that combination PWM thoughts improve DAC precision |
| CN112671410A (en) * | 2020-12-29 | 2021-04-16 | 珠海禅光科技有限公司 | Method based on PWM analog DAC function, digital-to-analog conversion circuit and storage medium |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102005030563B4 (en) | 2005-06-30 | 2009-07-09 | Infineon Technologies Ag | Multichannel digital / analog converter arrangement |
| CN106691432B (en) * | 2016-10-19 | 2023-04-21 | 深圳市杰纳瑞医疗仪器股份有限公司 | Induction type electrocardio measuring method and device |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5087914A (en) * | 1990-08-22 | 1992-02-11 | Crystal Semiconductor Corp. | DC calibration system for a digital-to-analog converter |
| US5248970A (en) * | 1991-11-08 | 1993-09-28 | Crystal Semiconductor Corp. | Offset calibration of a dac using a calibrated adc |
| US5235334A (en) * | 1992-03-30 | 1993-08-10 | Motorola, Inc. | Digital-to-analog converter with a linear interpolator |
| DE19828399C1 (en) * | 1998-06-25 | 1999-11-11 | Siemens Ag | High speed digital to analog converter for PWM output signals of lambda-probe in motor vehicle |
| US6078277A (en) * | 1998-07-02 | 2000-06-20 | Motorola, Inc. | Arrangement and method for producing a plurality of pulse width modulated signals |
-
1999
- 1999-07-09 DK DK199901006A patent/DK199901006A/en not_active Application Discontinuation
-
2000
- 2000-07-10 CN CNA008101094A patent/CN1636322A/en active Pending
- 2000-07-10 AU AU58065/00A patent/AU5806500A/en not_active Abandoned
- 2000-07-10 EP EP00943696A patent/EP1208647A2/en not_active Withdrawn
- 2000-07-10 WO PCT/DK2000/000381 patent/WO2001005036A2/en not_active Application Discontinuation
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101242186B (en) * | 2008-03-18 | 2010-10-06 | 苏州纳米技术与纳米仿生研究所 | A programmable non linear digital/analog converter |
| CN106323391A (en) * | 2015-06-30 | 2017-01-11 | 株式会社堀场Stec | Flow rate measuring device and flow rate controlling device |
| US10352748B2 (en) | 2015-06-30 | 2019-07-16 | Horiba Stec, Co., Ltd. | Flow rate measuring device |
| CN107846221A (en) * | 2017-11-02 | 2018-03-27 | 深圳市太铭科技有限公司 | A kind of method that combination PWM thoughts improve DAC precision |
| CN112671410A (en) * | 2020-12-29 | 2021-04-16 | 珠海禅光科技有限公司 | Method based on PWM analog DAC function, digital-to-analog conversion circuit and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2001005036A3 (en) | 2008-01-10 |
| DK199901006A (en) | 2001-01-10 |
| WO2001005036A2 (en) | 2001-01-18 |
| EP1208647A2 (en) | 2002-05-29 |
| AU5806500A (en) | 2001-01-30 |
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