CN1595807A - Semiconductor integrated circuit in which voltage down converter output can be observed as digital value - Google Patents

Semiconductor integrated circuit in which voltage down converter output can be observed as digital value Download PDF

Info

Publication number
CN1595807A
CN1595807A CNA2004100617474A CN200410061747A CN1595807A CN 1595807 A CN1595807 A CN 1595807A CN A2004100617474 A CNA2004100617474 A CN A2004100617474A CN 200410061747 A CN200410061747 A CN 200410061747A CN 1595807 A CN1595807 A CN 1595807A
Authority
CN
China
Prior art keywords
circuit
voltage
mentioned
register
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2004100617474A
Other languages
Chinese (zh)
Inventor
中野直佳
那须隆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Publication of CN1595807A publication Critical patent/CN1595807A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/021—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in voltage or current generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5004—Voltage

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Logic Circuits (AREA)

Abstract

An output voltage of a VDC circuit is subjected to A/D conversion with an on-chip A/D converter. Accordingly, an output voltage VDCout of the VDC circuit can be observed as a digital value, which facilitates measurement. Reduction in the number of terminals leads to reduction in chip size. In addition, the terminal that has been used for providing voltage VDCout can be used for other purposes. Therefore, a semiconductor integrated circuit allowing for easy mass production test and reduced number of man-hours in the mass production test can be provided.

Description

Can observe the semiconductor integrated circuit of step-down controller output with digital quantity
Technical field
The present invention relates to semiconductor integrated circuit.
Background technology
Because the electric current supply ability of the booster circuit that nonvolatile memory is built-in is extremely low, so the ability such as high voltage antinoise that produced can not be exported the high voltage that is produced to outside terminal.Therefore, open A/D (mould/number) transducer that discloses built-in detection usefulness in the flat 5-325580 communique the spy, with the high voltage dividing potential drop that is produced, after changing by A/D converter digital signal is outputed to the outside, confirm the technology of builtin voltage by the monitoring digital signal.
But for the voltage of confirming to produce in inside, the A/D converter of integrated detection special use increases chip area on chip, is not very wise move aspect cost.
On the other hand, along with the development of monolithic system, the circuit scale of semiconductor integrated circuit increases in recent years, and therefore, count increase and become problem the man-hour of the detection of dispatching from the factory of design verification and batch process.
Particularly (VDC: step-down controller) and in the semiconductor integrated circuit of A/D converter, present situation is to the design evaluation of reduction voltage circuit, A/D converter and other logical circuits and produces in batches to detect each circuit unit is carried out respectively at integrated reduction voltage circuit.
In the output voltage of estimating the VDC circuit identical occasion whether with design load, or whether the voltage that detection VDC circuit is exported when detecting that dispatches from the factory under the batch process situation exists unusual occasion, the output voltage V DCout of VDC circuit need be exported from the terminal that semiconductor integrated circuit had as analog quantity, and it is measured.Therefore, there is the mensuration system complicated problems that becomes.
In addition, the circuit scale of each circuit increases, and design is estimated, produced in batches and increases the man-hour of detecting.Also have, the input that these semiconductor integrated circuit had, output subnumber increase, and are formed in the chip size of semiconductor integrated circuit the situation that can not ignore input, export the configuring area of welding zone.Particularly when input, when output welding zone number increases, chip size is not by being configured in inner circuit scale decision, but by the situation decision of circumferential arrangement welding zone.
Summary of the invention
The objective of the invention is to: be used for the detection of integrated in addition circuit in being provided at the semiconductor integrated circuit of reduction voltage circuit, A/D converter and other logical circuits integrated by means of function integrated circuit, can design evaluation effectively, the batch process detection is simultaneously easy trying to achieve, and can also reduce and produce the detection semiconductor integrated circuit in man-hour in batches.In addition, its purpose of while also is to suppress input, the output subnumber of semiconductor integrated circuit.
More particularly, the objective of the invention is to: utilize the function of A/D converter that the voltage of reduction voltage circuit is observed as digital quantity, judge the voltage relevant simultaneously with this reduction voltage circuit, perhaps this voltage control is become suitable voltage, therefore, its purpose also is to reduce the terminal of the voltage that is used to observe directly relevant with reduction voltage circuit.
Come to the point, the present invention is a kind of semiconductor integrated circuit, and it possesses: the 1st terminal of the outer power voltage that acceptance applies from the outside; Reduce the voltage generating circuit of outer power voltage, generation builtin voltage; Use internal circuit with the builtin voltage correspondent voltage; Builtin voltage is converted to the A/D change-over circuit of digital value to outside output digital signal from the analogue value; And be used for exporting digital signal to outside the 2nd terminal.
Therefore, major advantage of the present invention is: owing to have the A/D converter that is integrated on the chip, builtin voltage is become digital signal output, so measure simply, can reduce the detection terminal that voltage monitoring is used simultaneously.
Above-mentioned purpose of the present invention and other purpose, feature, aspect and advantage can be understood the detailed description below understandable, of the present invention in conjunction with the accompanying drawings.
Description of drawings
Fig. 1 is the block diagram of structure that the semiconductor integrated circuit 1 of the embodiment of the invention 1 is shown.
Fig. 2 is the block diagram of structure that the semiconductor integrated circuit 50 of embodiment 2 is shown.
Fig. 3 is the block diagram of structure that the semiconductor integrated circuit 60 of embodiment 3 is shown.
Fig. 4 is the block diagram of structure that the semiconductor integrated circuit 70 of embodiment 4 is shown.
Fig. 5 is the block diagram of structure that the semiconductor integrated circuit 80 of embodiment 5 is shown.
Fig. 6 is the block diagram of structure that the semiconductor integrated circuit 90 of embodiment 6 is shown.
Fig. 7 is the circuit diagram that the structure of the reference voltage generating circuit 98 among Fig. 6 is shown.
Fig. 8 is the block diagram of structure that the semiconductor integrated circuit 140 of embodiment 7 is shown.
Fig. 9 is the circuit diagram that the structure of the differential amplifier 147 of Fig. 8 and voltage conversion circuit 148 is shown.
Figure 10 is the block diagram of structure that the semiconductor integrated circuit 200 of embodiment 8 is shown.
Figure 11 is the figure that the structure example of Zapping circuit 204 is shown.
Figure 12 is the block diagram of structure that the semiconductor integrated circuit 210 of embodiment 9 is shown.
Figure 13 is the block diagram of structure that the semiconductor integrated circuit 220 of embodiment 10 is shown.
Figure 14 illustrates the 1st flow chart of handling that CPU carries out.
Figure 15 is the 2nd flow chart of handling of explanation CPU 228.
Figure 16 is explanation the 3rd flow chart of handling that CPU carried out.
Figure 17 is the block diagram of structure that the semiconductor integrated circuit 240 of embodiment 11 is shown.
Figure 18 is the block diagram of structure that the semiconductor integrated circuit 250 of embodiment 12 is shown.
Figure 19 is the block diagram of structure that the semiconductor integrated circuit 260 of embodiment 13 is shown.
Figure 20 is the circuit diagram of structure that the voltage conversion circuit 268 of Figure 19 is shown.
Figure 21 is the block diagram of structure that the semiconductor integrated circuit 290 of embodiment 14 is shown.
Figure 22 is the block diagram of structure that the semiconductor integrated circuit 300 of embodiment 15 is shown.
Figure 23 is the circuit diagram that the structure of the voltage conversion circuit 306 among Figure 22 is shown.
Figure 24 is the block diagram of structure that the semiconductor integrated circuit 350 of embodiment 16 is shown.
Embodiment
Below embodiments of the present invention will be described in detail with reference to the accompanying drawings.In addition, the same-sign among the figure is represented identical or suitable part.
Embodiment 1
Fig. 1 is the block diagram of structure that the semiconductor integrated circuit 1 of the embodiment of the invention 1 is shown.
With reference to Fig. 1, semiconductor integrated circuit 1 comprises: terminal 2,4,6,8,10,12,14,16～18; Step-down conversion (VDC) circuit 20; A/D converter 22; And logical circuit 24.
VDC circuit 20 comprises reference voltage generating circuit 26, differential amplifier 28 and voltage conversion circuit 30.A/D converter 22 comprises the register 32 of storage A/D transformation result.
About power supply, supply voltage VCC is supplied to VDC circuit 20 from terminal 2.In addition, supply voltage AVCC is supplied to A/D converter 22 through terminal 12.Voltage VDCout as the output of VDC circuit 20 is supplied to logical circuit 24.That is, each circuit acceptance supply voltage separately carries out work.In addition, simple for making explanation, earthed voltage VSS, just public by each circuit.
About the terminal of VDC circuit 20 usefulness, the terminal 4 of output voltage V DCref of the terminal 2 of accepting supply voltage, output reference voltage generation circuit 26 and the output terminal 6 as the voltage VDCout of the output voltage of VDC circuit 20 is arranged.The terminal of A/D converter has the terminal 12 of input supply voltage AVCC, the terminal 14 that A/D conversion usefulness reference voltage Avref is provided and the terminal 10 of input analog signal AN1.The terminal of logical circuit 24 usefulness is useful on the terminal 16～18 with outside exchange input, output signal.
In addition, the analog input of existing A/D converter 22 is not VDC circuit 20 or logical circuit 24 inputs internally all from the outside input of semiconductor integrated circuit.This is because A/D converter is arranged on the cause of the analog interface part of LSI usually.So, when the output voltage of the output voltage of confirming VDC circuit 20 or reference voltage generating circuit 26, by means of observing terminal 6 or the terminal 4 of exporting these voltages respectively carry out from the semiconductor integrated circuit outside as analog quantity.
In embodiment 1, the output voltage V DCout of VDC circuit 20 is connected with the signal input node AN0 ' of A/D converter 22.Therefore, voltage VDCout becomes digital signal by means of A/D converter 22 from analog signal conversion, and the value after the conversion is stored in the register 32 that is used for storing the A/D transformation result of A/D converter 22 inside.Whether therefore, in general, for the output voltage of the built-in VDC circuit of semiconductor integrated circuit, observe the work of judging the VDC circuit normal by means of the voltage of the terminal that will export voltage VDCout as analog quantity, whether magnitude of voltage is suitable.In contrast, in the present invention, voltage VDCout can be observed as the digital quantity that is stored in the register 32.The value of this register 32 can be read by reading with logical circuit in the logical circuit 24, and the regulation terminal of the data output usefulness from the terminal 16～18 of input, output usefulness is to the output of the outside of semiconductor integrated circuit 1.
In the past, when estimating or detect, must be with the output voltage V DCout of VDC circuit as analog quantity from the terminal output that semiconductor integrated circuit had, it is measured, therefore have the mensuration system complicated problems that becomes.In contrast, in the semiconductor integrated circuit 1 of embodiment 1, because utilize the A/D converter on the chip that the output voltage of VDC circuit has been carried out the A/D conversion, thus the output voltage values of VDC circuit can be observed as digital quantity, thus be easy to measure.
In addition, though it is stable for the output that makes the VDC circuit usually, need be to terminal 6 additional a certain amount of electric capacity, but when the very stable load capacitance of the output low in energy consumption, can guarantee to make the VDC circuit in semiconductor integrated circuit 1 of the logical circuit 24 that is driven by the output of VDC circuit 20, it is unnecessary that 6 of terminals become.Therefore, when the chip size of semiconductor integrated circuit is determined by number of terminals, can cut down the shared space of terminal 6, reduce chip size.In addition, the terminal 6 that is used for output voltage V DCout originally can be used for other purposes.
Embodiment 2
Fig. 2 is the block diagram of structure that the semiconductor integrated circuit 50 of embodiment 2 is shown.
With reference to Fig. 2, the semiconductor integrated circuit 50 of embodiment 2 comprises logical circuit 56, with the logical circuit in the structure that is substituted in semiconductor integrated circuit shown in Figure 11 24, in addition, also comprises terminal 54 and selector 52.
Logical circuit 56 output is used for signal ADSEL0 that the input of A/D converter is selected.The setting of terminal 54 is in order to import analog input signal AN0.Selector 52 is selected the voltage VDCout of signal AN0 and 20 outputs of VDC circuit according to signal ADSEL0, and selection result is put on the input node AN0 ' of A/D converter 22.
Embodiment 2 is characterised in that to possess selector 52, and this selector 52 has 2 inputs, and its output is connected with the analog input node AN0 ' of A/D converter 22.
In embodiment 1, the analog input node AN0 ' of A/D converter 22 and the output voltage V DCout of VDC circuit 20 coupling.In embodiment 2, voltage VDCout is connected with an input of selector 52, and another input of selector 52 is applied from the analog input signal AN0 of terminal 54 inputs.Logical circuit 56 output indications are to selecting the signal ADSEL0 of which input in 2 inputs of selector 52.Selecteed input signal is applied to the analog input node AN0 of A/D converter 22 in 2 inputs of selector 52.
Selected as the output voltage V DCout of VDC circuit 20, when inputing to A/D converter 22, voltage VDCout is carried out the A/D conversion by A/D converter 22.Value after the conversion is stored in the register 32.The value of register 32 can be read by not shown the reading with logical circuit in the logical circuit 56, and the regulation terminal of the data output usefulness from input, lead-out terminal 16～18 is to the output of the outside of semiconductor integrated circuit 50.
When the detection of the work of carrying out the VDC circuit and magnitude of voltage are measured, generally voltage VDCout is exported from the output voltage terminal that is connected with VDC circuit that semiconductor integrated circuit is had as analog quantity, and it is observed.In embodiment 2, can voltage VDCout be applied to the analog input node that is integrated in A/D converter 22 on the chip by selector 52.Therefore, can the value of voltage VDCout be carried out the A/D conversion, observe from the outside as the digital quantity that is stored in the register 32 at chip internal.
In addition, when analog signal AN0 selects according to the selected device 52 of the signal ADSEL0 that exports from logical circuit 56, when signal AN0 is applied to the input node AN0 ' of A/D converter 22, analog signal AN0 is carried out the A/D conversion.Then, transformation result is stored in the register 32.The transformation result that is stored in the signal AN0 in the register 32 can be read by not shown the reading with logical circuit in the logical circuit 56, and the regulation terminal of the data output usefulness from terminal 16～18 is to the output of the outside of semiconductor integrated circuit 50.
According to embodiment 2, owing to possess selector 52, so the input node AN0 ' that can make A/D converter 22 is public for the input measurement of the output voltage measurement of VDC circuit 20 and the analog signal AN0 that applies from the outside.Therefore, can not reduce the live end subnumber of the analog input terminal that semiconductor integrated circuit 50 had, the work of VDC circuit 20 is judged, or the magnitude of voltage of voltage VDCout is estimated and observed.
In addition, though in present embodiment 2, used selector, also can use the input number at the many input selectors more than 2 with 2 inputs, 1 output.At this moment, the output voltage V DCout of VDC circuit can be from the signal that also comprises other signals, selected, the effect identical can be obtained with the invention of embodiment 2.
Embodiment 3
Fig. 3 is the block diagram of structure that the semiconductor integrated circuit 60 of embodiment 3 is shown.
With reference to Fig. 3, semiconductor integrated circuit 60 has removed terminal 4,6 and 10 on the one hand in the structure of semiconductor integrated circuit shown in Figure 11, be provided with the terminal 54 that is used to apply analog signal AN0 on the other hand again.Then, A/D converter 22 accepts to be applied to through terminal 54 the analog signal AN0 of input node AN0 ', and AN1 ' accepts the reference voltage V DCref that reference voltage generating circuit 26 is exported at the input node.Other aspects are owing to identical with the structure shown in Fig. 1, so do not repeat its explanation.
VDC circuit 20 is to the output voltage V DCout of differential amplifier 28 input VDC circuit 20 with as the reference voltage V DCref of the output voltage of reference voltage generating circuit 26.Differential amplifier 28 is adjusted into identical voltage with voltage VDCout with voltage VDCref according to the difference control voltage conversion circuit 30 of voltage.
In general structure, whether as design load, produced in order to estimate by reference voltage generating circuit 26 at chip exterior reference voltage V DCref, voltage VDCref is output to the outside via terminal.
In contrast, in 60 structure of the semiconductor integrated circuit of embodiment 3, the input node AN1 ' coupling of voltage VDCref and A/D converter 22.Voltage VDCref is changed by A/D converter 22 at chip internal, and the value after the conversion is stored in the register 32.Therefore, though voltage VDCref generally externally is used as analog quantity observation through the output voltage terminal, in embodiment 3, voltage VDCref can be observed as the digital quantity that is stored in the register 32.The value of register 32 can be read by reading with logical circuit in the logical circuit 24, and the regulation terminal of the data output usefulness from terminal 16～18 is to the output of the outside of semiconductor integrated circuit 60.
As previously discussed, there is the mensuration system complicated problems that becomes in prior art, in contrast, in the semiconductor integrated circuit 60 of embodiment 3, owing to can utilize the output of 22 pairs of reference voltage generating circuits 26 of A/D converter to change, observe as digital quantity, so the mensuration of voltage VDCref becomes easily the cost that can reduce checking simultaneously and measure.
In addition, can reduce the terminal that is used for voltage VDCref is exported to chip exterior.Therefore, the shared physical space of terminal can be reduced, when the size of chip is determined by number of terminals, chip size can be reduced.When not being such situation, the terminal of terminal as other purposes can be used.
Embodiment 4
Fig. 4 is the block diagram of structure that the semiconductor integrated circuit 70 of embodiment 4 is shown.
With reference to Fig. 4, semiconductor integrated circuit 70 comprises logical circuit 74, with the logical circuit in the structure that is substituted in semiconductor integrated circuit shown in Figure 3 60 24, also comprises selector 72 and terminal 10.Other structure is because identical with the semiconductor integrated circuit 60 of Fig. 3, so do not repeat its explanation.
Selector 72 is accepted the reference voltage V DCref that the analog input signal AN1 that applies through terminal 10 as input signal and reference voltage generating circuit 26 are exported.Selector 72 is applied to selected signal the input node AN1 ' of A/D converter 22 according to 1 from 2 inputs of signal ADSEL1 selection of logical circuit 74 outputs.
When having selected reference voltage V DCref, and when being entered into A/D converter 22, reference voltage V DCref is carried out the A/D conversion in selector 72, the value after the conversion is stored in the register 32.The value of register 32 can be read by not shown the reading with logical circuit in the logical circuit 74, exports to the outside of semiconductor integrated circuit 70 with the regulation terminal of the output of the data the terminal 16～18 usefulness from input and output.
When the mensuration of the detection of the work of carrying out the VDC circuit and magnitude of voltage, generally with reference voltage V DCref as analog quantity from the terminal output that semiconductor integrated circuit had, and it is observed.In contrast, in embodiment 4,, can utilize A/D converter 22 to carry out the A/D conversion at chip internal owing to can reference voltage V DCref be connected to the input node AN1 ' of A/D converter 22 by selector 72.In view of the above, reference voltage V DCref can be observed as the digital quantity that is stored in the register 32.
According to embodiment 4, owing to possess selector 72, so the input node AN1 ' that can make A/D converter 22 is public for the input measurement of the reference voltage measurement of VDC circuit 20 and the analog signal AN1 that applies from the outside.Therefore, can not reduce the live end subnumber of the analog input terminal that semiconductor integrated circuit 70 had, the work of VDC circuit 20 is judged, the magnitude of voltage of voltage VDCref is estimated and observed.
In addition, though in embodiment 4, used selector, also can use the input number at the many input selectors more than 2 with 2 inputs, 1 output.At this moment, the reference voltage V DCref of VDC circuit can be from the signal that also comprises other signals, selected, the effect identical can be obtained with the invention of embodiment 4.
Embodiment 5
Fig. 5 is the block diagram of structure that the semiconductor integrated circuit 80 of embodiment 5 is shown.
With reference to Fig. 5, semiconductor integrated circuit 80 is integrated VDC circuit 20 on 1 block semiconductor chip; A/D converter 22; Logical circuit 82; And selector 52,72.Each circuit is provided with special-purpose input, lead-out terminal respectively.
Be provided with the terminal 2 that is used for VDC circuit 20 is applied supply voltage VCC relatively with power supply, be used for A/D converter 22 is applied the terminal 12 of supply voltage AVCC.Provide voltage VDCout to logical circuit 82 as the output of VDC circuit 20.That is, VDC circuit 20, A/D converter 22 and logical circuit 82 acceptance supply voltage separately carry out work.On the other hand, earthed voltage VSS is public to these 3 circuit blocks promptly.
As the terminal of A/D converter 22 usefulness, also be provided with the terminal 14 of the reference voltage Avref of input A/D conversion usefulness; And the terminal 54,10 that is used for importing respectively analog input signal AN0, AN1.Though A/D converter 22 has input node AN1 ', these 2 inputs of AN0 ', also can have more analog input end.Selector 52 accept the analog signal AN0 that applies through terminal 54 and from the voltage VDCout of VDC circuit 20 outputs as 2 input signals, select one of them according to the signal ADSEL0 that is applied by logical circuit 82, the input node AN0 ' to A/D converter 22 exports with selected signal.
Selector 72 is accepted reference voltage V DCref that the analog input signal AN1 that applies through terminal 10 and reference voltage generating circuit 26 exported as 2 input signals, select one of them according to signal ADSEL1, selected signal is applied to the input node AN1 ' of A/D converter 22 by logical circuit 82 outputs.
Terminal 16～18,100～102nd is to the terminal of logical circuit 82 settings.Terminal 16～18th is as the terminal of the input of the outside of control signal or data and semiconductor integrated circuit 80, output signal I/O1～I/On n (n is a natural number).In addition, terminal 100～102nd, for and the outside of semiconductor integrated circuit 80 between the terminal of input, output m (m is a natural number) being provided with as the data of the register 84,86,88 in the logical circuit 82 of data D1～Dm.
VDC circuit 20 comprises reference voltage generating circuit 26, differential amplifier 28 and voltage conversion circuit 30.Reference voltage generating circuit 26 becomes the reference voltage V DCref of benchmark of voltage VDCout of the output of VDC circuit 20.Differential amplifier 28 is accepted voltage VDCref and voltage VDCout, if voltage VDCout is lower than voltage VDCref, then so that the mode that voltage VDCout raises transmits signals to voltage conversion circuit 30.On the other hand, if voltage VDCout is higher than voltage VDCref, then differential amplifier 28 is sent to voltage conversion circuit 30 in the mode that voltage VDCout is raise with output signal.The output signal that voltage conversion circuit 30 is accepted from differential amplifier 28 generates than its low assigned voltage VDCout from supply voltage VCC.
A/D converter 22 can carry out work according to the signal from logical circuit 82 and set.22 pairs of analog signals from input node AN0 ', AN1 ' input of A/D converter are carried out the A/D conversion, and transformation result is kept in the register 32 as digital quantity.
Logical circuit 82 outputs are respectively applied for signal ADSEL0, the ADSEL1 that the input of the selector 52,72 of 2 inputs is selected.In addition, logical circuit 82 can also be read the value of the register 32 in the A/D converter 22.
Logical circuit 82 comprises the 1st register the 84, the 2nd register the 86, the 3rd register 88 and arithmetic unit 89.Arithmetic unit 89 can store the result who deducts the value of the 2nd register 86 from the value of the 1st register 84 in the 3rd register 88.
The following describes the overall work of the semiconductor integrated circuit 80 of embodiment 5.
Selector 52 is according to the voltage VDCout that selects voltage conversion circuit 30 outputs from signal ADSEL0, the ADSEL1 of logical circuit 82.Selector 72 is according to the reference voltage V DCref of signal ADSEL1 selection reference voltage generating circuit 26 outputs.Voltage VDCout carries out the A/D conversion at chip internal by A/D converter 22, and its result is stored in the register 32.The value of this register 32 is read by logical circuit 82, and the digital value of voltage VDCout is stored in the 1st register 84.
In addition, reference voltage V DCref is changed by A/D converter 22, and this transformation result is stored in the register 32.The digital value of reference voltage V DCref is read from register 32 by logical circuit 82, and this value is stored in the 2nd register 86.
The value that the arithmetic unit 89 that logical circuit 82 is had is accepted the 1st register 84 and the 2nd register 86 is imported as it, can be with their difference, and promptly (values of value-Di 2 registers of the 1st register) store in the 3rd register 88.
The value that the 1st register the 84, the 2nd register 86 and the 3rd register 88 keep can be used as data D1～Dm and reads from the outside of semiconductor integrated circuit 80 through terminal 100～102.
In embodiment 5, except that the digital quantity of the digital quantity of the output voltage V DCout that can observe the VDC circuit and reference voltage V DCref, can also observe the digital quantity of their voltage difference from the outside of semiconductor integrated circuit 80.Therefore, and compare from the outside to the situation that these voltages are observed, can simply and easily carry out the evaluation of VDC circuit working as analog quantity.That is, obtain being used to change the value of input supply voltage VCC or the information of reference voltage V DCref (data of output voltage and input voltage characteristic) in can be between short-term, make the output of VDC circuit become the optimum voltage of internal logic circuit work.According to these information, can also determine the input value of supply voltage VCC, or make chip again by changing mask design, obtain desirable output voltage.
In addition, owing to can carry out voltage VDCout and logical operation, so whether by means of the work of logical circuit 82, can easily carry out voltage VDCout is the judgement of exceptional value as the reference voltage V DCref of its expected value.
Embodiment 6
Fig. 6 is the block diagram of structure that the semiconductor integrated circuit 90 of embodiment 6 is shown.
With reference to Fig. 6, semiconductor integrated circuit 90 is integrated VDC circuit 92 on 1 block semiconductor chip; A/D converter 22; Logical circuit 94; And selector 52,72, each circuit has special-purpose separately input, lead-out terminal.
About power supply, through 2 pairs of VDC circuit of terminal, 92 supply line voltage VCC, through 12 pairs of A/D converters of terminal, 22 supply line voltage AVCC.In addition, the voltage VDCout that logical circuit 94 is supplied with as the output of VDC circuit 92.That is, VDC circuit 92, A/D converter 22 and logical circuit 94 acceptance supply voltage separately carry out work.Here, earthed voltage VSS, promptly public by these 3 circuit.
VDC circuit 92 is accepted supply voltage VCC and is exported as it at inside generation reference voltage V DCref, and voltage VDCout is exported.A/D converter 22 carries out the A/D conversion with reference to the reference voltage Avref of A/D conversion usefulness to 2 analog input signals that input to input node AN0 ', AN1 ', and its result is stored in the register 32.
Selector 52 is selectors of 2 inputs, and output is connected with the input node AN0 ' of A/D converter.Selector 72 also is the selector of 2 inputs, and its output is connected with the input node AN1 ' of A/D converter 22.
The analog signal AN0 that applies through terminal 54 is applied to an input of selector 52, is applied to its another input as the voltage VDCout of the output of voltage conversion circuit 30.In addition, the analog signal AN1 that applies through terminal 10 is applied to an input of selector 72, is applied to another input of selector 72 as the reference voltage V DCref of the output of reference voltage generating circuit 98.
Logical circuit 94 is through the signal I/O1～I/On of n terminal 16～18 exchanges as control signal or data.In addition, the data of built-in register are imported, exported to logical circuit 94 as data D1～Dm through terminal 100～102.
VDC circuit 92 comprises reference voltage generating circuit 98, differential amplifier 28 and voltage conversion circuit 30.The output that reference voltage generating circuit 98 becomes VDC circuit 92 is the reference voltage V DCref of the benchmark of voltage VDCout.Differential amplifier 28 accepts voltage VDCref and voltage VDCout imports as it.If voltage VDCout is lower than voltage VDCref, then differential amplifier 28 is so that the mode that voltage VDCout raises exports control signal to voltage conversion circuit 30.
On the other hand, if voltage VDCout is higher than voltage VDCref, then differential amplifier 28 exports control signal to voltage conversion circuit 30 in the mode that voltage VDCout is raise.The control signal that voltage conversion circuit 30 is accepted from differential amplifier 28 generates than its low assigned voltage VDCout from supply voltage VCC.
A/D converter 22 can carry out work according to the signal from logical circuit 94 and set.22 pairs of analog signals from input node AN0 ', AN1 ' input of A/D converter are carried out the A/D conversion.A/D converter 22 is kept at transformation result in the register 32 as digital quantity.
Logical circuit 94 output is used for signal ADSEL0, ADSEL1 that the input of selector 52,72 is selected.In addition, logical circuit 94 can also be read the value of the register 32 in the A/D converter 22.
Logical circuit 94 comprises the 1st register the 84, the 2nd register the 86, the 3rd register 88 and arithmetic unit 89.Logical circuit 94 can store the result who deducts the value of the 2nd register 86 from the value of the 1st register 84 in the 3rd register 88 by means of arithmetic unit 89.
VDC circuit 92 comprises reference voltage generating circuit 98.Reference voltage generating circuit 98 can be exported the output voltage that becomes benchmark, and one or more voltages and one or more voltages that are lower than it of being higher than it.
VDC circuit 92 also comprises the register 96 that is used to control reference voltage.According to the value of register 96, in can 98 a plurality of voltages that can produce of selection reference voltage generating circuit 1.In addition, though register 96 is configured in the VDC circuit 92 in Fig. 6, also can be configured in the logical circuit 94 or zone in addition.
Fig. 7 is the circuit diagram of structure that the reference voltage generating circuit 98 of Fig. 6 is shown.
With reference to Fig. 7, reference voltage generating circuit 98 comprises the reference voltage generating circuit 112 that uses band gap to generate reference voltage; And to being deciphered by the output of the register 96 that is provided with from the control signal Dref of logical circuit, thereby the output opposite house selects the decoding and the door of the signal controlled to select a circuit 114.Decoding and door select circuit 114 output signal SG1～SGn as control signal.
Reference voltage generating circuit 98 also comprises with the phase inverter 116 of signal SG1 counter-rotating, with the phase inverter 120 of signal SG2 counter-rotating and the phase inverter 124 that signal SGn is reversed.
Reference voltage generating circuit 98 also comprises: its negative input node is accepted the output of reference voltage generating circuit 112, the amplifier 128 that node N4 is connected with its positive input node; Its grid is accepted the output of amplifier 128, the P channel MOS transistor 130 of source and supply voltage VCC coupling; Be connected the leakage of P channel MOS transistor 130 and the resistance 132 between the node N1; Be connected the resistance 134 between node N1 and the node N2; And be connected resistance 136 between node N3 and the ground connection node.Source output reference voltage VDCref from P channel MOS transistor 130.In addition, between node N3 and node N2, be provided with resistance specified quantity, that be connected in series.
Reference voltage generating circuit 98 also comprises: the transmission gate 118 that node N1 is connected with node N4 according to the output of signal SG1 and phase inverter 116; The transmission gate 122 that node N2 is connected with node N4 according to the output of signal SG2 and phase inverter 120; And the transmission gate 126 that node N3 is connected with node N4 according to the output of signal SGn and phase inverter 124.
Voltage VDCref by resistance 132,134 ..., 136 be divided into a plurality of branch pressure voltages, in the branch pressure voltage one be transmitted door 118,122 ..., 126 select, input to node N4.Amplifier 128 compares the output of selected branch pressure voltage and reference voltage generating circuit 112, the conducting of control P channel MOS transistor 130.
Referring again to Fig. 6, the overall work of semiconductor integrated circuit 90 is described.
Selector 52 is according to the voltage VDCout that selects voltage conversion circuit 30 outputs from the signal ADSEL0 of logical circuit 94.Selector 72 is according to the signal ADSEL1 selection reference voltage VDCref of logical circuit 94 outputs.
Voltage VDCout carries out the A/D conversion by A/D converter 22, and its result is stored in the register 32.The value of register 32 is read by logical circuit 94, and its value is stored in the 1st register 84.
In addition, reference voltage V DCref is carried out the A/D conversion by A/D converter 22.The A/D transformation result is stored in the register 32.The value of register 32 is read by logical circuit 94, is stored in the 2nd register 86.The arithmetic unit 89 of logical circuit 94 inside can be with reference to the value of the 1st register 84 and the value of the 2nd register 86, and with their difference, promptly (values of value-Di 2 registers of the 1st register) store in the 3rd register 88.
The 1st register the 84, the 2nd register 86 in the logical circuit 94 and the content of the 3rd register 88 can be used as data D1～Dm and read from the outside of semiconductor integrated circuit 90 through terminal 100～102.
When the value of reading the 1st register the 84, the 2nd register 86 and the 3rd register 88 from the outside of semiconductor integrated circuit 90, and in the time of consequently must be revised, the 3rd register 88 is write the numerical value of expression and the difference of present reference voltage V DCref to reference voltage V DCref.By means of the control of logical circuit 94 content of the 3rd register 88 is write register 96, can change the reference voltage V DCref of reference voltage generating circuit 98 outputs.
In embodiment 6, can read the value of the 1st register the 84, the 2nd register 86 and the 3rd register 88 from the outside of semiconductor integrated circuit 90, calculate the reference voltage that is suitable for condition of work, write in the register 96 that VDC circuit 94 had by difference, can change reference voltage V DCref it and present reference voltage.In view of the above, semiconductor integrated circuit 90 can carry out work with higher allowance.In addition, by configuration when semiconductor integrated circuit energized etc. is carried out initialization, can be used to carry out the control device that it sets the boot of work in the execution of the outside of semiconductor integrated circuit 90, can adjust the reference voltage V DCref of VDC circuit 92 according to operating position.
Embodiment 7
Fig. 8 is the block diagram of structure that the semiconductor integrated circuit 140 of embodiment 7 is shown.
With reference to Fig. 8, semiconductor integrated circuit 140 is integrated VDC circuit 141 on 1 block semiconductor chip; A/D converter 22; Logical circuit 142; And selector 52,72, each circuit has special-purpose input, lead-out terminal respectively.
About power supply, through 2 pairs of VDC circuit of terminal, 141 supply line voltage VCC, through 12 pairs of A/D converters of terminal, 22 supply line voltage AVCC.In addition, the voltage VDCout that logical circuit 142 is supplied with as the output of VDC circuit 141.That is, VDC circuit 141, A/D converter 22 and logical circuit 142 acceptance supply voltage separately carry out work.Here, earthed voltage VSS, promptly public by these 3 circuit.
VDC circuit 141 is accepted supply voltage VCC and is exported as it at inside generation reference voltage V DCref, and voltage VDCout is exported.A/D converter 22 carries out the A/D conversion with reference to the reference voltage Avref of A/D conversion usefulness to 2 analog input signals that input to input node AN0 ', AN1 ', and its result is stored in the register 32.
Selector 52 is selectors of 2 inputs, and output is connected with the input node AN0 ' of A/D converter.Selector 72 also is the selector of 2 inputs, and its output is connected with the input node AN1 ' of A/D converter 22.
The analog signal AN0 that applies through terminal 54 is applied to an input of selector 52, is applied to its another input as the voltage VDCout of the output of voltage conversion circuit 148.In addition, the analog signal AN1 that applies through terminal 10 is applied to an input of selector 72, is applied to another input of selector 72 as the reference voltage V DCref of the output of reference voltage generating circuit 26.
Logical circuit 142 is through the signal I/O1～I/On of n terminal 16～18 exchanges as control signal or data.In addition, the data of built-in register are imported, exported to logical circuit 142 as data D1～Dm through terminal 100～102.
VDC circuit 141 comprises reference voltage generating circuit 26, differential amplifier 147 and voltage conversion circuit 148.The output that reference voltage generating circuit 26 becomes VDC circuit 141 is the reference voltage V DCref of the benchmark of voltage VDCout.
Differential amplifier 147 accepts voltage VDCref and voltage VDCout imports as it.If voltage VDCout is lower than voltage VDCref, then differential amplifier 147 is so that the mode that voltage VDCout raises exports control signal to voltage conversion circuit 148.
On the other hand, if voltage VDCout is higher than voltage VDCref, then differential amplifier 147 exports control signal to voltage conversion circuit 148 in the mode that voltage VDCout is raise.The control signal that voltage conversion circuit 148 is accepted from differential amplifier 147 generates than its low assigned voltage VDCout from supply voltage VCC.
A/D converter 22 can carry out work according to the signal from logical circuit 142 and set.22 pairs of analog signals from input node AN0 ', AN1 ' input of A/D converter are carried out the A/D conversion.A/D converter 22 is kept at transformation result in the register 32 as digital quantity.
Logical circuit 142 output is used for signal ADSEL0, ADSEL1 that the input of selector 52,72 is selected.In addition, logical circuit 142 can also be read the value of the register 32 in the A/D converter 22.
Logical circuit 142 comprises the 1st register the 84, the 2nd register the 86, the 3rd register 88 and arithmetic unit 89.Logical circuit 142 can store the result who deducts the value of the 2nd register 86 from the value of the 1st register 84 in the 3rd register 88 by means of arithmetic unit 89.
The voltage conversion circuit 148 of VDC circuit 141 comprises a plurality of current driving circuits.Usually the current driving circuit that becomes the number of benchmark carries out work.The number of the current driving circuit of work can be by means of the value change of register 146.When the value of register 146 when negative, the number of current driving circuit increases.When the value of register 146 is timing, the number of current driving circuit reduces.Though the register 146 that is used for the Control current driving force in embodiment 7 is configured in the inside of VDC circuit 141, also register 146 can be configured in logical circuit 142 inner or zones in addition.Control by means of logical circuit 142 can be transferred to the value of the 3rd register 88 in the register 146.
Fig. 9 is the circuit diagram that the structure of the differential amplifier 147 of Fig. 8 and voltage conversion circuit 148 is shown.
With reference to Fig. 9, differential amplifier 147 comprises its each negative input node and accepts reference voltage V DCref, its positive input node accept voltage VDCout comparison circuit 152,154 ..., 156.Voltage conversion circuit 148 comprises: the output to register 146 is deciphered, output signal SG11, SG12 ..., the decoding of SG1n and door select circuit 162; Import the input-switching circuit 164 of switching according to signal SG11～SG1n; And according to the output of input-switching circuit 164, the drive circuit 166 that its driving force changes.Drive circuit 166 comprises a plurality of P channel MOS transistors 197,198,199 as current driving circuit.P channel MOS transistor 197～199 be connected power supply node in parallel and node that voltage VDCout is exported between.
Input-switching circuit 164 comprises: acknowledge(ment) signal SG11 and with the phase inverter 172 of its counter-rotating; Be connected between the grid of power supply node and P channel MOS transistor 197, the P channel MOS transistor 176 of its grid acknowledge(ment) signal SG11; And the transmission gate 174 that the output of comparison circuit 152 is connected to the grid of P channel MOS transistor 197 according to the output of signal SG11 and phase inverter 172.
Referring again to Fig. 8, the overall work of semiconductor integrated circuit 140 is described.
Selector 52 is according to the voltage VDCout that selects voltage conversion circuit 148 outputs from the signal ADSEL0 of logical circuit 142.Selector 72 is according to the signal ADSEL1 selection reference voltage VDCref of logical circuit 142 outputs.
Voltage VDCout carries out the A/D conversion by A/D converter 22, and its result is stored in the register 32.The value of register 32 is read by logical circuit 142, and its value is stored in the 1st register 84.
In addition, reference voltage V DCref is carried out the A/D conversion by A/D converter 22.The A/D transformation result is stored in the register 32.The value of register 32 is read by logical circuit 142, is stored in the 2nd register 86.The arithmetic unit 89 of logical circuit 142 inside can be with reference to the value of the 1st register 84 and the value of the 2nd register 86, and with their difference, promptly (values of value-Di 2 registers of the 1st register) store in the 3rd register 88.
The 1st register the 84, the 2nd register 86 in the logical circuit 142 and the content of the 3rd register 88 can be used as data D1～Dm and read from the outside of semiconductor integrated circuit 140 through terminal 100～102.
When logical circuit 142 consumed current increased, voltage VDCout reduced.Thus, the storage content of the 3rd register 88 of difference of having carried out the value of the value of voltage VDCout of A/D conversion and voltage VDCref becomes negative value.Then, by means of the control of logical circuit 142, the value of the 3rd register 88 is transferred in the register 146.In view of the above, the number of the P channel MOS transistor of working in the drive circuit 166 of Fig. 9 increases, and plays the effect that voltage reduces that suppresses.
In addition, behind the retention value of reading the 1st register the 84, the 2nd register 86 and the 3rd register 88 from the outside of semiconductor integrated circuit 140, when the current driving ability of VDC circuit 141 is revised, the 3rd register 88 is write the numerical value of the difference of the number that should carry out work of P channel MOS transistor of expression drive circuit 166 and its standard operation number from the outside.The value of the 3rd register 88 can be transferred into the register 146 of VDC circuit by means of logical circuit 142, thereby changes the current driving ability of VDC circuit.
In embodiment 7, read into the outside of semiconductor integrated circuit 140 by value with the 1st register the 84, the 2nd register 86 and the 3rd register 88, judge the operating current of the necessity that is suitable for condition of work externally, the difference of the current driving ability of itself and present voltage conversion circuit 148 is write in the register 146, thereby can change the current driving ability of voltage conversion circuit 148.In view of the above, semiconductor integrated circuit 140 can carry out work with higher allowance.
In addition, disposed, can carry out the control device of the boot etc. of the setting that is used to carry out register 146 in the outside of semiconductor integrated circuit 140 at the initial stage of semiconductor integrated circuit 140 energized etc. being carried out work.In view of the above, can adjust the current driving ability of VDC circuit 141, thereby try to achieve the optimization of current sinking according to operating position.
In addition, by means of when semiconductor integrated circuit 140 is worked, utilizing outside control circuit to upgrade the content of the 1st register the 84, the 2nd register 86 and the 3rd register 88, the content of the 3rd register 88 is sent to register 146, can dynamically changes the current driving ability of VDC circuit 141.
Embodiment 8
Figure 10 is the block diagram of structure that the semiconductor integrated circuit 200 of embodiment 8 is shown.
With reference to Figure 10, semiconductor integrated circuit 200 is integrated VDC circuit 202 on 1 block semiconductor chip; A/D converter 22; Logical circuit 94; And selector 52,72, each circuit has special-purpose separately input, lead-out terminal.The title of the input signal of power supply and each circuit and function are identical with embodiment's 6, therefore do not repeat its explanation.
VDC circuit 202 comprises Zapping circuit 204, with the register 96 in the structure of the VDC circuit 92 that is substituted in Fig. 6.That is, VDC circuit 202 comprises reference voltage generating circuit 98, differential amplifier 28, voltage conversion circuit 30 and Zapping circuit 204.The output that reference voltage generating circuit 98 becomes VDC circuit 202 is the reference voltage V DCref of the benchmark of voltage VDCout.Differential amplifier 28 accepts voltage VDCref and voltage VDCout imports as it.If voltage VDCout is lower than voltage VDCref, then differential amplifier 28 is so that the mode that voltage VDCout raises exports control signal to voltage conversion circuit 30.
On the other hand, if voltage VDCout is higher than voltage VDCref, then differential amplifier 28 exports control signal to voltage conversion circuit 30 in the mode that voltage VDCout is raise.The control signal that voltage conversion circuit 30 is accepted from differential amplifier 28 generates than its low assigned voltage VDCout from supply voltage VCC.
A/D converter 22 can carry out work according to the signal from logical circuit 94 and set.22 pairs of analog signals from input node AN0 ', AN1 ' input of A/D converter are carried out the A/D conversion.A/D converter 22 is kept at transformation result in the register 32 as digital quantity.
Logical circuit 94 output is used for signal ADSEL0, ADSEL1 that the input of selector 52,72 is selected.In addition, logical circuit 94 can also be read the value of the register 32 in the A/D converter 22.
Logical circuit 94 comprises the 1st register the 84, the 2nd register the 86, the 3rd register 88 and arithmetic unit 89.Logical circuit 94 can store the result who deducts the value of the 2nd register 86 from the value of the 1st register 84 in the 3rd register 88 by means of arithmetic unit 89.
Reference voltage generating circuit 98 can be exported the output voltage that becomes benchmark, and one or more voltages and one or more voltages that are lower than it of being higher than it.Set and to select these voltage by means of the fusing of Zapping circuit 204.In addition, though Zapping circuit 204 is configured in the inside of VDC circuit 202 in Figure 10, also can be configured in the inside of logical circuit 94 or zone in addition.
Figure 11 is the figure that the structure example of Zapping circuit 204 is shown.
With reference to Figure 11, Zapping circuit 204 comprises a plurality of by being connected in series in the unit that resistance R between power supply node and the ground connection node and fuse element FUSE constitute.Control signal SIG1～SIGn exports respectively from a plurality of unit.Control signal corresponding in each unit is exported from the connected node of resistance R and fuse element FUSE.When being in the nonconducting state that fuse element FUSE is blown, control signal is the H level, if fuse element maintains the original state, then control signal is the L level.
In addition, the configuration of resistance and fuse element also can reverse, and fuse element also can be to blow the fuse that the two ends, back are conducting state as anti-fusing device in addition.
Referring again to Figure 10, the overall work of semiconductor integrated circuit 200 is described.
Selector 52 is according to the voltage VDCout that selects voltage conversion circuit 30 outputs from the signal ADSEL0 of logical circuit 94.Selector 72 is according to the signal ADSEL1 selection reference voltage VDCref of logical circuit 94 outputs.
Voltage VDCout carries out the A/D conversion by A/D converter 22, and its result is stored in the register 32.The value of register 32 is read by logical circuit 94, and its value is stored in the 1st register 84.
In addition, reference voltage V DCref is carried out the A/D conversion by A/D converter 22.The result of A/D conversion is stored in the register 32.The value of register 32 is read by logical circuit 94, is stored in the 2nd register 86.The arithmetic unit 89 of logical circuit 94 inside can be with reference to the value of the 1st register 84 and the value of the 2nd register 86, and with their difference, promptly (values of value-Di 2 registers of the 1st register) store in the 3rd register 88.
The 1st register the 84, the 2nd register 86 in the logical circuit 94 and the content of the 3rd register 88 can be used as data D1～Dm and read from the outside of semiconductor integrated circuit 200 through terminal 100～102.
When the value of reading the 1st register the 84, the 2nd register 86 and the 3rd register 88 from the outside of semiconductor integrated circuit 200, when judgement must be revised reference voltage V DCref, the 3rd register is write the numerical value of expression and the difference of present reference voltage from the outside.Then, utilize logical circuit 94 that the content of the 3rd register 88 is set as the fusing of Zapping circuit 204 inside and write, can change reference voltage generating circuit 98 output voltages.
In embodiment 8, can read the value of the 1st register the 84, the 2nd register 86 and the 3rd register 88 from the outside of semiconductor integrated circuit 200.Then, can judge the reference voltage that is suitable for condition of work.The fusing of the inside of the Zapping circuit 204 that the difference of itself and present reference voltage is had as VDC circuit 202 according to result of determination is set and is write, thereby reference voltage V DCref can be changed into the voltage of the service condition that is suitable for semiconductor integrated circuit 200.By means of fusing is write optimum value, can generate the reference voltage that permanently is modified to optimum value when using afterwards.
In addition, by when dispatching from the factory detection, reading out in the value of storing in the 1st～the 3rd register, after calculating the appropriate value of judging by each magnitude of voltage, fusing is write the reference voltage correction value, the semiconductor integrated circuit that its reference voltage that can dispatch from the factory has permanently been adjusted.
Embodiment 9
Figure 12 is the block diagram of structure that the semiconductor integrated circuit 210 of embodiment 9 is shown.
With reference to Figure 12, semiconductor integrated circuit 210 is integrated VDC circuit 212 on 1 block semiconductor chip; A/D converter 22; Logical circuit 142; And selector 52,72.Each circuit has special-purpose separately input, lead-out terminal.The title of the input signal of power supply and each circuit and function are identical with embodiment's 7, therefore do not repeat its explanation.
VDC circuit 212 comprises reference voltage generating circuit 26, differential amplifier 147, voltage conversion circuit 148.The output that reference voltage generating circuit 26 becomes VDC circuit 212 is the reference voltage V DCref of the benchmark of voltage VDCout.Differential amplifier 147 accepts voltage VDCref and voltage VDCout imports as it.If voltage VDCout is lower than voltage VDCref, then differential amplifier 147 is so that the mode that voltage VDCout raises exports control signal to voltage conversion circuit 148.
On the other hand, if voltage VDCout is higher than voltage VDCref, then differential amplifier 147 exports control signal to voltage conversion circuit 148 in the mode that voltage VDCout is raise.The control signal that voltage conversion circuit 148 is accepted from differential amplifier 147 generates than its low assigned voltage VDCout from supply voltage VCC.
A/D converter 22 can carry out work according to the signal from logical circuit 142 and set.22 pairs of analog signals from input node AN0 ', AN1 ' input of A/D converter are carried out the A/D conversion.A/D converter 22 is kept at transformation result in the register 32 as digital quantity.
Logical circuit 142 output is used for signal ADSEL0, ADSEL1 that the input of selector 52,72 is selected.In addition, logical circuit 142 can also be read the value of the register 32 in the A/D converter 22.
Logical circuit 142 comprises the 1st register the 84, the 2nd register the 86, the 3rd register 88 and arithmetic unit 89.Logical circuit 142 can store the result who deducts the value of the 2nd register 86 from the value of the 1st register 84 in the 3rd register 88 by means of arithmetic unit 89.
VDC circuit 212 comprises Zapping circuit 214, with the register 146 in the structure that is substituted in VDC circuit 141 shown in Figure 8.Other structures of VDC circuit 212 are identical with VDC circuit 141.
The voltage conversion circuit 148 of VDC circuit 212 inside comprises a plurality of current drives transistors, and the current drives that becomes the number of benchmark is usually worked with transistor.The number of the current drive transistor of work can be set by means of the fusing of Zapping circuit 214 and change.Voltage conversion circuit 148 is worked as follows: when being negative by the value of fusing setting, driving with transistorized number increases, and is timing when this is worth, and drives with transistorized number and reduces.Though Zapping circuit 214 is configured in the inside of VDC circuit 212 in Figure 12, it also can be configured in the inside of logical circuit 142 or zone in addition.
Control by means of logical circuit 142 can write the value of the 3rd register Zapping circuit 214.
Referring again to Figure 12, the overall work of semiconductor integrated circuit 210 is described.
The voltage VDCout that selector 52 selects voltage conversion circuit 148 to be exported according to the signal ADSEL0 from logical circuit 142.Selector 72 is according to the signal ADSEL1 selection reference voltage VDCref of logical circuit 142 outputs.
Voltage VDCout carries out the A/D conversion by A/D converter 22, and its result is stored in the register 32.The value of register 32 is read by logical circuit 142, and its value is stored in the 1st register 84.
In addition, reference voltage V DCref is carried out the A/D conversion by A/D converter 22.The result of A/D conversion is stored in the register 32.The value of register 32 is read by logical circuit 142, is stored in the 2nd register 86.The arithmetic unit 89 of logical circuit 142 inside can be with reference to the value of the 1st register 84 and the value of the 2nd register 86, and with their difference, promptly (values of value-Di 2 registers of the 1st register) store in the 3rd register 88.
The 1st register the 84, the 2nd register 86 in the logical circuit 142 and the content of the 3rd register 88 can be used as data D1～Dm and read from the outside of semiconductor integrated circuit 210 through terminal 100～102.
When logical circuit 142 consumed current increased, voltage VDCout reduced.Thus, the storage content of the 3rd register 88 of difference of having carried out the value of the value of voltage VDCout of A/D conversion and voltage VDCref becomes negative value.Then, by means of the control of logical circuit 142, the value of the 3rd register 88 is transferred in the register 146.In view of the above, the number of carrying out the P channel MOS transistor of work in the drive circuit 166 of Fig. 9 increases, and plays the effect that voltage reduces that suppresses.
That is, read the value of the 1st register the 84, the 2nd register 86 and the 3rd register 88 from the outside of semiconductor integrated circuit 210, judge whether and to be revised the current driving ability of VDC circuit 212.When needs are revised, by the 3rd register 88 being write expression and the numerical value that drives with the difference of transistorized standard operation number, control by means of logical circuit 142, this setting is written into the Zapping circuit 214 that is configured in VDC circuit 212 inside, thereby changes the current driving ability of VDC circuit.
In embodiment 9, the value of the 1st register the 84, the 2nd register 86 and the 3rd register 88 can be read into the outside of semiconductor integrated circuit 210, judge the operating current of the necessity that is suitable for condition of work.Then, the difference of the current driving ability of itself and present voltage conversion circuit 148 is write Zapping circuit 214, can permanently set the driving force of the voltage conversion circuit 148 that is suitable for work.In view of the above, can be accomplished the optimized VDC circuit of power consumption.In addition, by when dispatching from the factory detection, writing Zapping circuit, can dispatch from the factory and permanently be adjusted into the semiconductor integrated circuit of suitable current driving ability the correction value of current driving ability.
Embodiment 10
Figure 13 is the block diagram of structure that the semiconductor integrated circuit 220 of embodiment 10 is shown.
With reference to Figure 13, semiconductor integrated circuit 220 is integrated VDC circuit 222 on 1 block semiconductor chip; A/D converter 22; Logical circuit 226; And flash memory 224.Each circuit has special-purpose separately input, lead-out terminal.
Supply voltage VCC is supplied to VDC circuit 222, and supply voltage AVCC is supplied to A/D converter.Voltage VDCout as the output of VDC circuit 222 is supplied to logical circuit 226 as working power voltage.In addition, to flash memory 224 from outside supply line voltage FVCC.That is, circuit block acceptance working power voltage separately separately carries out work.In addition, here, earthed voltage VSS is public to each circuit block just.
VDC circuit 222 comprises reference voltage generating circuit 98, differential amplifier 147, voltage conversion circuit 148, register 96 and 146.VDC circuit 222 is accepted supply voltage VCC from the outside, output is as the reference voltage V DCref of the output of reference voltage generating circuit 98 with as the voltage VDCout of the output of voltage conversion circuit 148.
A/D converter 22 is accepted supply voltage AVCC as working power voltage.Then, A/D converter 22 is accepted the reference voltage Avref of A/D conversion usefulness through terminal 14.
Selector 52 is selected some analog signal AN0 and the voltage VDCout according to the signal ADSEL0 that applies from logical circuit 226, is applied to the input node AN0 ' of A/D converter 22.Selector 72 is according to some selection the among signal ADSEL1 selection reference voltage VDCref and the analog signal AN1, and is applied to the input node AN1 ' of A/D converter 22.
Logical circuit 226 comprises CPU the 228, the 1st register the 84, the 2nd register 86 and the 3rd register 88.Signal I/O1～the I/On as control signal or data is imported, exported to logical circuit 266 through n the terminal 16～18 and the outside of semiconductor integrated circuit 220.In addition, logical circuit 226 data of reading/writing through the data of m terminal 100～102 exchange registers or by CPU 228 are as data D1～Dm.In addition, logical circuit 226 is exported address value A1～Ak that CPU 228 are exported through terminal 230～232.
Reference voltage generating circuit 98 becomes the reference voltage V DCref of benchmark of the output voltage V DCout of VDC circuit 222.Differential amplifier 147 is accepted voltage VDCref and voltage VDCout, and it is compared.
If voltage VDCout is lower than voltage VDCref, then differential amplifier 147 is so that the mode that voltage VDCout raises is sent to voltage conversion circuit 148 with control signal.On the other hand, if voltage VDCout is higher than voltage VDCref, then differential amplifier 147 is sent to voltage conversion circuit 148 in the mode that voltage VDCout is raise with control signal.
Voltage conversion circuit 148 generates than its low assigned voltage VDCout from supply voltage VCC according to the control signal from differential amplifier 147.
A/D converter 22 can carry out work according to the signal from logical circuit 226 and set.22 pairs of analog signals from input node AN0 ', AN1 ' input of A/D converter are carried out the A/D conversion, and transformation result is saved in the register 32 as digital quantity.
Logical circuit 226 output is used for signal ADSEL0, ADSEL1 that the input of selector 52,72 is selected.In addition, logical circuit 226 can also be read the value of the register 32 of A/D converter 22 inside.In addition, logical circuit 226 result that deducts the value of the reference voltage V DCref that the 2nd register 86 kept can the value with the voltage VDCout that kept from the 1st register 84 stores in the 3rd register 88.This work can be carried out by means of the subtraction function that CPU 228 is had.
The structure of reference voltage generating circuit 98 and voltage conversion circuit 148 is illustrated with Fig. 7 and Fig. 9, so do not repeat its explanation.
Voltage conversion circuit 148 comprises a plurality of driving transistors, and the driving that becomes the number of benchmark is usually worked with transistor.The driving of work can be changed by means of the value of register 146 with transistorized number.Voltage conversion circuit 148 is worked as follows: when the value of register 146 when negative, driving with transistorized number increases, and when this value is timing, drives with transistorized number minimizing.In addition, register 146 also can be stored the transistorized number of current drives of work, constitutes voltage conversion circuit 148 in the mode of being carried out work by the transistor of the number of register 146 appointments.
In addition, though register 146 is configured in the inside of VDC circuit 222 in Figure 13, it also can be configured in the inside of logical circuit 226 or zone in addition.In addition, the logical circuit that the value of storage can involved CPU 228 in register 146 is read and is write.
Reference voltage generating circuit 98 can be exported the output voltage that becomes benchmark, and one or more voltages and one or more voltages that are lower than it of being higher than it.Utilize the value of register 96 to select to these voltage.Though register 96 is configured in the inside of VDC circuit 222 in Figure 13, also can be configured in the inside of logical circuit 226 or zone in addition.
The following describes the work of semiconductor integrated circuit 220.
The data of having used when in flash memory 224, having disposed the performed instruction column of CPU 228 and having carried out these instructions.Being used for carrying out instruction column (program) that the CPU of the work of embodiment 10 uses and the parameter of using in these instructions (data) also is stored in the flash memory 224.When the power connection of semiconductor integrated circuit 220, when resetting, perhaps during this program of program start beyond this program of customer requirements, can carry out program in flash memory 224 stored.
Figure 14 is the flow chart that the 1st processing that CPU carries out is shown.
With reference to Figure 14, in step S1, handle beginning, in step S2, carry out the setting of selector.Selector 52 is selected the voltage VDCout of voltage conversion circuit 148 outputs.In addition, the voltage VDCref of selector 72 selection reference voltage generating circuits 98 outputs.CPU 228 couples of signal ADSEL0, ADSEL1 control to carry out such selection.
Then, in step S3, A/D converter 22 is set at startup.So A/D converter 22 at first carries out the A/D conversion to voltage VDCout, and its result is stored in the register 32.This transformation result is read from register 32 by CPU 228, is stored in the 1st register 84.In addition, voltage VDCref carries out the A/D conversion by A/D converter, is stored in the register 32.The transformation result of voltage VDCref is read by CPU 228, is stored in the 2nd register 86 (step S4).
Then, in step S5, carry out calculation process.That is, CPU as input, stores their difference (values of value-Di 2 registers of the 1st register) value of the 1st register 84 and the 2nd register 86 into the 3rd register 88 in.
Then, in step S6 by means of the performed transfer instructions of CPU 228, the content of the 1st register to the 3 registers as data D1～Dm through terminal 100～102 to the output of the outside of this semiconductor integrated circuit 220.
Figure 15 is the flow chart of the 2nd processing of explanation CPU 228.
To increasing in logical circuit 226 consumed current that comprise CPU, the voltage correction when voltage VDCout reduces is illustrated in Figure 15.When voltage VDCout reduced, the content of the 3rd register 88 that the difference of the voltage VDCout of A/D conversion and voltage VDCref has been passed through in storage was a negative value.
In step S11, handle beginning, the value of in step S12, reading the 3rd register 88.Then, in step S13, the 3rd register value is carried out positive and negative judgement.
When the value of the 3rd register when negative, enter step S14, CPU 228 is sent to current driving ability control register with the value of the 3rd register 88.In view of the above, the driving of voltage conversion circuit 148 inside increases with transistorized number, thereby voltage conversion circuit 148 plays the effect that voltage reduces that suppresses.
On the other hand, when the value of judging the 3rd register in step S13 is timing, do not carry out step S14, and enter step S15, processing finishes.
In addition, also can be by the target voltage values (peak, minimum) that is configured in the flash memory 224 is compared with voltage, judge whether voltage VDCref and voltage VDCout be suitable, judged result is exported from terminal 100～102 through data/address bus as data D1～Dn, also can be with it as the outside of signal I/O1～I/On through input, lead-out terminal 16～18 notice semiconductor integrated circuit 220.
Figure 16 is the flow chart of the 3rd processing being used to illustrate that CPU carries out.
With reference to Figure 16 the situation that 228 couples of voltage VDCout of CPU revise is described.
Handle beginning in step S21 after, then in step S22, CPU 228 reads the value of the 3rd register 88.Then, in step S23, read the target higher limit that is stored in the flash memory 224.
Then, CPU 228 judges whether the value of the 3rd register 88 surpasses the target higher limit in step S24.When judging above the target higher limit, CPU 228 reduces 1 with the value of register 96 in step S25, reference voltage generating circuit 98 is sent instruction voltage VDCref is reduced.In addition, when the value of judging the 3rd register in step S24 is no more than the target higher limit, does not carry out step S25, and enter step S26.
In step S26, read the target lower limit that is stored in the flash memory 224.Then, judge that in step S27 whether the value of the 3rd register is less than the target lower limit.Then, when less than the target lower limit, enter step S28, with the value increase by 1 of reference voltage control with register 96.
On the other hand, when the value of the 3rd register is not less than the target lower limit, does not carry out step S28, and enter step S29, processing finishes.Like this, read the value that the 1st register the 84, the 2nd register 86 and the 3rd register 88 keep, itself and the desired value that is configured in the flash memory 224 are compared by means of the work of CPU 228.Then, can write correction value to register 96, revise voltage VDCref according to this comparative result.About correction result, can confirm to revise the value that voltage VDCout has carried out the A/D conversion whether successful by observation.For example, when needs improve operating voltage for the high operation speed that improves the logical circuit that comprises CPU, reference voltage can be improved, on the other hand, when the current sinking of the logical circuit that reduces to comprise CPU, reference voltage can be reduced.
As mentioned above, in embodiment 10, in logical circuit, be provided with CPU, in flash memory, disposed program and data that CPU uses.In view of the above, can easily manage by means of program control voltage VDCref and voltage VDCout.Particularly, the voltage that comprises logical circuit when work of CPU by detection reduces, and can change the current driving ability of VDC circuit, or change operating voltage as required.In addition, by means of the data of control program in the rewriting flash memory and the use of this program, can carry out the management of VDC circuit to each semiconductor integrated circuit according to purposes.
Embodiment 11
Figure 17 is the block diagram of structure that the semiconductor integrated circuit 240 of embodiment 11 is shown.
With reference to Figure 17, semiconductor integrated circuit 240 also comprises the terminal 242 of importing reset signal and the terminal 244 of input pattern signal except that the structure of semiconductor integrated circuit shown in Figure 13 220.
As activate when the power connection input to the reset signal RESET of terminal 242 in, activate the mode signal MOD that puts on terminal 244, then be disposed at the established procedure work in the flash memory that in embodiment 10, illustrated.So semiconductor integrated circuit 240 can carry out the A/D conversion with voltage VDCref and voltage VDCout, and its value is exported to the outside of semiconductor integrated circuit with digital value as data D1～Dm.Other structures are identical with the situation of embodiment 10 with work, thereby do not repeat its explanation.
By value that relatively is converted to digital value and the goal-setting value of in flash memory, storing, can change the value of register 96,146, thereby change the current driving ability of VDC circuit, perhaps change the reference voltage V DCref of VDC circuit.
In addition,, also can only make mode signal MOD effective, discern with CPU though in embodiment 11, mode signal MOD and reset signal RESET are activated simultaneously so that mode signal MOD is discerned.
In addition, a plurality of terminals that are used for the input pattern signal can be set also, each terminal is associated with work shown in the flow chart of Figure 14～16, carry out work limitedly.For example, 2 pattern terminals can be set, apply signal MOD1, MOD2, the value of change register 146 when making signal MOD1 effective, the current driving ability of change VDC circuit, in addition, the value of change register 96 changes reference voltage V DCref when making signal MOD2 effective.
As mentioned above, in embodiment 11,, can when resetting, revise the current driving ability or the reference voltage V DCref of VDC circuit by means of the pattern terminal is set.In addition, irrespectively make the effective structure of pattern terminal, after the hardware that utilization is disposed at the outside of semiconductor integrated circuit 240 makes the pattern terminal effectively, can revise the current driving ability and the reference voltage V DCref of VDC circuit immediately if make with resetting.
Embodiment 12
Figure 18 is the block diagram of structure that the semiconductor integrated circuit 250 of embodiment 12 is shown.
With reference to Figure 18, semiconductor integrated circuit 250 is integrated VDC circuit 222 on 1 block semiconductor chip; A/D converter 22; Logical circuit 252; And selector 52,72.Each circuit has special-purpose separately input, lead-out terminal.VDC circuit 222 comprises reference voltage generating circuit 98, differential amplifier 147, voltage conversion circuit 148 and register 96 and 146.
A/D converter 22 comprises the register 32 of storage A/D transformation result.
Logical circuit 252 comprises CPU 228, SRAM 254, mask rom the 256, the 1st register the 84, the 2nd register 86 and the 3rd register 88.
Now power supply is described.VDC circuit 222 is accepted supply voltage VCC through terminal 2.A/D converter 22 is accepted supply voltage AVCC through terminal 12.The logical circuit 252 that comprises CPU 228 is accepted voltage VDCout as the output of VDC circuit 222 as supply voltage.That is, each circuit block acceptance supply voltage separately carries out work.Here, earthed voltage VSS is public to each circuit block just.
VDC circuit 222 comprises reference voltage generating circuit 98, differential amplifier 147, voltage conversion circuit 148 and register 96 and 146.VDC circuit 222 is accepted supply voltage VCC from the outside, output is as the reference voltage V DCref of the output of reference voltage generating circuit 98 with as the voltage VDCout of the output of voltage conversion circuit 148.
A/D converter 22 is accepted supply voltage AVCC as working power voltage.Then, A/D converter 22 is accepted the reference voltage Avref of A/D conversion usefulness through terminal 14.
Selector 52 is selected some analog signal AN0 and the voltage VDCout according to the signal ADSEL0 that applies from logical circuit 252, is applied to the input node AN0 ' of A/D converter 22.Selector 72 some according among signal ADSEL1 selection reference voltage VDCref and the analog signal AN1 is applied to the input node AN1 ' of A/D converter 22.
Logical circuit 252 comprises CPU the 228, the 1st register the 84, the 2nd register the 86, the 3rd register 88, SRAM 254 and mask rom 256.Signal I/O1～the I/On as control signal or data is imported, exported to logical circuit 252 through n the terminal 16～18 and the outside of semiconductor integrated circuit 250.In addition, logical circuit 252 data of reading/writing through the data of m terminal 100～102 exchange registers or by CPU 228 are as data D1～Dm.In addition, logical circuit 252 is exported address value A1～Ak that CPU 228 are exported through terminal 230～232.
Reference voltage generating circuit 98 becomes the reference voltage V DCref of benchmark of the output voltage V DCout of VDC circuit 222.Differential amplifier 147 is accepted voltage VDCref and voltage VDCout, and it is compared.
If voltage VDCout is lower than voltage VDCref, then differential amplifier 147 is so that the mode that voltage VDCout raises is sent to voltage conversion circuit 148 with control signal.On the other hand, if voltage VDCout is higher than voltage VDCref, then differential amplifier 147 is sent to voltage conversion circuit 148 in the mode that voltage VDCout is raise with control signal.
Voltage conversion circuit 148 generates than its low assigned voltage VDCout from supply voltage VCC according to the control signal from differential amplifier 147.
A/D converter 22 can carry out work according to the signal from logical circuit 252 and set.22 pairs of analog signals from input node AN0 ', AN1 ' input of A/D converter are carried out the A/D conversion, and transformation result is kept in the register 32 as digital quantity.
Logical circuit 252 output is used for signal ADSEL0, ADSEL1 that the input of selector 52,72 is selected.In addition, logical circuit 252 can also be read the value of the register 32 of A/D converter 22 inside.In addition, logical circuit 252 result that deducts the value of the reference voltage V DCref that the 2nd register 86 kept can the value with the voltage VDCout that kept from the 1st register 84 stores in the 3rd register 88.This work can be carried out by means of the subtraction function that CPU 228 is had.
The structure of reference voltage generating circuit 98 and voltage conversion circuit 148 is illustrated with Fig. 7 and Fig. 9, so do not repeat its explanation.
Voltage conversion circuit 148 comprises a plurality of driving transistors, and the driving that becomes the number of benchmark is usually carried out work with transistor.The driving of work can be changed by means of the value of register 146 with transistorized number.Voltage conversion circuit 148 is worked as follows: when the value of register 146 when negative, driving with transistorized number increases, and when this value is timing, drives with transistorized number minimizing.In addition, also can in register 146, store the transistorized number of current drives of work, constitute voltage conversion circuit 148 in the mode of being carried out work by the transistor of the number of register 146 appointments.
In addition, though register 146 is configured in the inside of VDC circuit 222 in Figure 18, it also can be configured in the inside of logical circuit 252 or zone in addition.In addition, the logical circuit 252 that the value of storage can involved CPU 228 in register 146 is read and is write.
Reference voltage generating circuit 98 can be exported the output voltage that becomes benchmark, and one or more voltages and one or more voltages that are lower than it of being higher than it.Can select these voltages by means of the value of register 96.Though register 96 is configured in the inside of VDC circuit 222 in Figure 18, also can be configured in the inside of logical circuit 252 or zone in addition.
The following describes the work of semiconductor integrated circuit 250 of the present invention.
Instruction column that CPU 228 is performed and the storage used when carrying out these instructions are in the memory devices such as EEPROM (not shown) that are disposed at semiconductor integrated circuit 250 outsides.
In mask rom 256, disposed and be used for the instruction column in the above-mentioned memory device and data load, the work of CPU 228 has been moved into the program (boot) in the program of this loading to SRAM 254.
When semiconductor integrated circuit 250 resets, when perhaps other programs in the mask rom require this boot to start, this boot work.Below the work that guides to the program in the SRAM 254 by this boot when resetting is described.
In embodiment 12, also carry out the work identical with the work that illustrated with Figure 14, Figure 15, Figure 16.That is, begin to handle, carry out the setting of selector.Selector 52 is selected the voltage VDCout of voltage conversion circuit 148 outputs.In addition, the voltage VDCref of selector 72 selection reference voltage generating circuits 98 outputs.CPU 228 control signal ADSEL0, ADSEL1 are to carry out such selection.
Then, A/D converter 22 is set to startup.So A/D converter 22 at first carries out the A/D conversion to voltage VDCout, and its result is stored in the register 32.This transformation result is read from register 32 by CPU 228, is stored in the 1st register 84.In addition, voltage VDCref carries out the A/D conversion by A/D converter, is stored in the register 32.The transformation result of voltage VDCref is read by CPU 228, is stored in the 2nd register 86.
Then, carry out calculation process.That is, CPU as input, stores their difference (values of value-Di 2 registers of the 1st register) value of the 1st register 84 and the 2nd register 86 into the 3rd register 88 in.
Then, by means of the performed transfer instructions of CPU 228, the content of the 1st register to the 3 registers as data D1～Dm through terminal 100～102 to the output of the outside of this semiconductor integrated circuit 250.
The following describes in logical circuit 252 consumed current that comprise CPU and increase the voltage correction when voltage VDCout reduces.When voltage VDCout reduced, the content of the 3rd register 88 that the difference of the voltage VDCout of A/D conversion and voltage VDCref has been passed through in storage was a negative value.
Read the value of the 3rd register 88, then, the value of the 3rd register is carried out positive and negative judgement.
When the value of the 3rd register when negative, CPU 228 is sent to current driving ability control register with the value of the 3rd register 88.In view of the above, the driving of voltage conversion circuit 148 inside increases with transistorized number, thereby voltage conversion circuit 148 plays the effect that voltage reduces that suppresses.
On the other hand, when the value of judging the 3rd register is timing, CPU 228 is not sent to register with the value of the 3rd register 88, and processing finishes.
In addition, also can compare and judge whether voltage VDCref and voltage VDCout be suitable from memory devices such as EEPROM (not shown), be configured to target voltage values (peak, minimum) and voltage in the SRAM by means of guiding, judged result is exported from terminal 100～102 through data/address bus as data D1～Dn, also can be with it as the outside of signal I/O1～I/On through input, lead-out terminal 16～18 notice semiconductor integrated circuit 250.
In addition, when 228 couples of voltage VDCout of CPU revised, CPU 228 read the value of the 3rd register 88.CPU 228 judges whether the value of the 3rd register 88 surpasses the target higher limit.In addition, CPU 228 judges that whether the value of the 3rd register is less than the target lower limit.Like this, read the value that the 1st register the 84, the 2nd register 86 and the 3rd register 88 keep, itself and the desired value that is configured to from memory devices such as EEPROM (not shown) in the SRAM by means of guiding are compared by means of the work of CPU 228.Then, can write correction value to register 96, revise voltage VDCref according to this comparative result.About correction result, can confirm to revise the value that voltage VDCout has carried out the A/D conversion whether successful by observation.
For example, in the time need improving operating voltage, reference voltage can be improved, on the other hand, when the current sinking of the logical circuit that reduces to comprise CPU, reference voltage can be reduced for the high operation speed that improves the logical circuit that comprises CPU.
In embodiment 12, utilize the program of boot program loads in the SRAM 254 on the masked ROM 256, can revise the current driving ability and the reference voltage V DCref of VDC circuit 222.In embodiment 12 since on integrated circuit configuring flash memory not, so compare, can reduce the process number of the processing of wafers of semiconductor integrated circuit with the situation that flash memory is installed.Therefore, can reduce the manufacturing cost of semiconductor integrated circuit.
Embodiment 13
Figure 19 is the block diagram of structure that the semiconductor integrated circuit 260 of embodiment 13 is shown.
With reference to Figure 19, semiconductor integrated circuit 260 is integrated VDC circuit 262 on 1 block semiconductor chip; A/D converter 22; Logical circuit 264; And selector 52,72.Each circuit has special-purpose separately input, lead-out terminal.
VDC circuit 262 comprises reference voltage generating circuit 26, differential amplifier 28, voltage conversion circuit 268 and register 266.A/D converter 22 comprises the register 32 of storage A/D transformation result.
Logical circuit 264 comprises the 1st register the 84, the 2nd register the 86, the 3rd register 88 and arithmetic unit 89.
About power supply, supply voltage VCC supplies with VDC circuit 262 through terminal 2, and supply voltage AVCC supplies with A/D converter 22 through terminal 12.In addition, the voltage VDCout as the output of VDC circuit 262 is supplied to logical circuit 264.That is, VDC circuit 262, A/D converter 22 and logical circuit 264 acceptance supply voltage separately carry out work.Here, earthed voltage VSS, just public by 3 circuit.
VDC circuit 262 is accepted supply voltage VCC, produces reference voltage V DCref in inside and exports as it, and voltage VDCout is exported.A/D converter 22 carries out the A/D conversion with reference to the reference voltage Avref of A/D conversion usefulness to 2 analog input signals that input to input node AN0 ', AN1 ', and its result is stored in the register 32.
Selector 52 is selectors of 2 inputs, and output is connected with the input node AN0 ' of A/D converter.Selector 72 also is the selector of 2 inputs, and its output is connected with the input node AN1 ' of A/D converter 22.
The analog signal AN0 that applies through terminal 54 is applied to an input of selector 52, is applied to its another input as the voltage VDCout of the output of voltage conversion circuit 268.In addition, the analog signal AN1 that applies through terminal 10 is applied to an input of selector 72, is applied to another input of selector 72 as the reference voltage V DCref of the output of reference voltage generating circuit 98.
Logical circuit 264 is through the signal I/O1～I/On of n terminal 16～18 exchanges as control signal or data.In addition, the data of built-in register are imported, exported to logical circuit 2 64 as data D1～Dm through terminal 100～102.
VDC circuit 262 comprises reference voltage generating circuit 98, differential amplifier 28 and voltage conversion circuit 268.The output that reference voltage generating circuit 98 becomes VDC circuit 262 is the reference voltage V DCref of the benchmark of voltage VDCout.Differential amplifier 28 accepts voltage VDCref and voltage VDCout imports as it.If voltage VDCout is lower than voltage VDCref, then differential amplifier 28 is so that the mode that voltage VDCout raises exports control signal to voltage conversion circuit 268.
On the other hand, if voltage VDCout is higher than voltage VDCref, then differential amplifier 28 exports control signal to voltage conversion circuit 268 in the mode that voltage VDCout is raise.The control signal that voltage conversion circuit 268 is accepted from differential amplifier 28 generates than its low assigned voltage VDCout from supply voltage VCC.
A/D converter 22 can carry out work according to the signal from logical circuit 264 and set.22 pairs of analog signals from input node AN0 ', AN1 ' input of A/D converter are carried out the A/D conversion.A/D converter 22 is kept at transformation result in the register 32 as digital quantity.
Logical circuit 264 output is used for signal ADSEL0, ADSEL1 that the input of selector 52,72 is selected.In addition, logical circuit 264 can also be read the value of the register 32 in the A/D converter 22.
Logical circuit 264 comprises the 1st register the 84, the 2nd register the 86, the 3rd register 88 and arithmetic unit 89.Logical circuit 264 can store the result who deducts the value of the 2nd register 86 from the value of the 1st register 84 in the 3rd register 88 by means of arithmetic unit 89.
Be configured in register 266 in the VDC circuit 262 and be storage and be used to change the register of controlling value of the mode of operation of VDC circuit.Utilization is set in the value in the register 266, can select a kind in these 3 kinds of patterns of VDC normal operation mode, VDC direct mode operation and VDC stop mode.VDC circuit 262 carries out above-mentioned common work under the VDC normal operation mode.Reference voltage generating circuit 26 and differential amplifier 28 quit work under the straight-through pattern of VDC, and voltage conversion circuit 268 does not carry out voltage transitions, and the supply voltage VCC with input directly exports as voltage VDCout basically.VDC circuit 262 quits work under the VDC stop mode, and voltage VDCout is by non-activation.In addition, though register 266 is configured in the inside of VDC circuit 262 in Figure 19, also can be configured in logical circuit 264 inside.
Figure 20 is the circuit diagram that the structure of the voltage conversion circuit 268 among Figure 19 is shown.
With reference to Figure 20, voltage conversion circuit 268 comprises: be connected power supply node and node that voltage VDCout is exported between P channel MOS transistor 282; The NOR circuit 274 of acknowledge(ment) signal MVDCoff, MVDCthrough; Accept the output of NOR circuit 274 and with the phase inverter 272 of its counter-rotating; And the transmission gate 270 that the output of differential amplifier 28 is connected to the grid of P channel MOS transistor 282 according to the output of the output of NOR circuit 274 and phase inverter 272.Also have, signal MVDCoff is the signal that is activated when the VDC stop mode.In addition, MVDCthrough is the signal that is activated when the VDC direct mode operation.Mode initialization signal MVDC according to exporting from the logical circuit 264 of Figure 19 writes register 266 with setting, and according to this setting, signal MVDCoff, MVDCthrough are activated/non-activation.
Voltage conversion circuit 268 also comprises: acknowledge(ment) signal MVDCoff and with the phase inverter 276 of its counter-rotating; The P channel MOS transistor of be connected between the grid of power supply node and P channel MOS transistor 282, its grid being accepted the output of phase inverter 276 278; And be connected between the grid and ground connection node of P channel MOS transistor 282, the N-channel MOS transistor 280 of its grid acknowledge(ment) signal MVDCthrough.
When signal MVDCoff was activated, transmission gate 270 became nonconducting state, and the output of differential amplifier 28 separates with the grid of P channel MOS transistor 282.Then, by means of 278 conductings of P channel MOS transistor, the grid of P channel MOS transistor 282 and supply voltage VCC coupling.Consequently P channel MOS transistor 282 becomes nonconducting state, and voltage VDCout is by non-activation.
On the other hand, when signal MVDCthrough was activated, transmission gate 270 became nonconducting state, and the grid of P channel MOS transistor 282 is separated with the output of differential amplifier 28.Then, by means of 280 conductings of N-channel MOS transistor, P channel MOS transistor 282 also becomes conducting state, and consequently supply voltage VCC intactly is output as voltage VDCout basically.
The overall work of semiconductor integrated circuit 260 is described referring again to Figure 19 below.
At first, from logical circuit 264 output signal MVDC, according to this signal, value is written in the register 266.The work that writes is carried out as follows: as writing command signal, write data through terminal 100～102 input data D1～Dm conducts through the part of terminal 16～18 from the external input signal I/O1～I/On of semiconductor integrated circuit 260.
At first VDC circuit 262 carries out the work that illustrated in embodiment 5 grades when the VDC normal operation mode.
Secondly, when being set at the VDC direct mode operation, 262 outputs of VDC circuit equate with supply voltage VCC that roughly the voltage of (low slightly) is as voltage VDCout.
Be used for selection signal ADSEL0 that the input of A/D converter 22 is selected from logical circuit 264 output, in view of the above, the input node AN0 ' of 52 pairs of A/D converters 22 of selector applies voltage VDCout.Voltage VDCout is carried out the A/D conversion by A/D converter, and its result is stored in the register 32.The value of register 32 is read by logical circuit 264, and the digital value corresponding with voltage VDCout is stored in the 1st memory 84.
The content of the 1st register 84 of logical circuit 264 inside can be read through terminal 100～102 from the outside of semiconductor integrated circuit 260.
When being set at the VDC stop mode, voltage conversion circuit 268 is driving voltage VDCout not.Therefore, logical circuit 264 can not be worked.At this moment, input resets (not shown), connects once more after perhaps closing supply voltage VCC once.
According to embodiment 13,, can learn with digital signal whether the supply voltage VCC that the semiconductor IC input is gone into is expected value from the outside of semiconductor integrated circuit by means of VDC circuit 262 is provided with the VDC direct mode operation.
In addition, when the occasion that reduces at supply voltage VCC etc., in the time of under the VDC normal operation mode, can not obtaining voltage VDCout that logical circuit 264 can work, can move to the VDC direct mode operation, therefore, can obtain freely to tackle the semiconductor integrated circuit of the change of supply voltage VCC.
Embodiment 14
Figure 21 is the block diagram of structure that the semiconductor integrated circuit 290 of embodiment 14 is shown.
With reference to Figure 21, semiconductor integrated circuit 290 comprises VDC circuit 262; A/D converter 22; Logical circuit 292; And selector 52,72, they are integrated on the 1 block semiconductor chip.Each circuit has special-purpose separately input, lead-out terminal.
VDC circuit 262 comprises reference voltage generating circuit 26, differential amplifier 28, voltage conversion circuit 268 and register 266.A/D converter 22 comprises the register 32 of storage A/D transformation result.Logical circuit 292 comprises the 1st register the 84, the 2nd register the 86, the 3rd register 88 and arithmetic unit 89.Logical circuit 292 also comprises the 4th register the 294, the 5th register 296 and NG flag register 298.
About power supply, supply voltage VCC is supplied to VDC circuit 262 through terminal 2, and supply voltage AVCC is supplied to A/D converter 22 through terminal 12.In addition, the voltage VDCout as the output of VDC circuit 262 is supplied to logical circuit 292.That is, VDC circuit 262, A/D converter 22 and logical circuit 292 acceptance supply voltage separately carry out work.Here, earthed voltage VSS, just public by 3 circuit.
VDC circuit 262 is accepted supply voltage VCC and is exported as it at inside generation reference voltage V DCref, and voltage VDCout is exported.A/D converter 22 carries out the A/D conversion with reference to the reference voltage Avref of A/D conversion usefulness to 2 analog input signals that input to input node AN0 ', AN1 ', and its result is stored in the register 32.
Selector 52 is selectors of 2 inputs, and output is connected with the input node AN0 ' of A/D converter.Selector 72 also is the selector of 2 inputs, and its output is connected with the input node AN1 ' of A/D converter 22.
The analog signal AN0 that applies through terminal 54 is applied to an input of selector 52, is applied to its another input as the voltage VDCout of the output of voltage conversion circuit 268.In addition, the analog signal AN1 that applies through terminal 10 is applied to an input of selector 72, is applied to another input of selector 72 as the reference voltage V DCref of the output of reference voltage generating circuit 98.
Logical circuit 292 through n terminal 16～18 switching signal I/O1～I/On as control signal or data.In addition, the data of built-in register are imported, exported to logical circuit 292 as data D1～Dm through terminal 100～102.
The output that reference voltage generating circuit 98 becomes VDC circuit 262 is the reference voltage V DCref of the benchmark of voltage VDCout.Differential amplifier 28 accepts voltage VDCref and voltage VDCout imports as it.If voltage VDCout is lower than voltage VDCref, then differential amplifier 28 is so that the mode that voltage VDCout raises exports control signal to voltage conversion circuit 268.
On the other hand, if voltage VDCout is higher than voltage VDCref, then differential amplifier 28 exports control signal to voltage conversion circuit 268 in the mode that voltage VDCout is raise.The control signal that voltage conversion circuit 268 is accepted from differential amplifier 28 generates than its low assigned voltage VDCout from supply voltage VCC.
A/D converter 22 can carry out work according to the signal from logical circuit 292 and set.22 pairs of analog signals from input node AN0 ', AN1 ' input of A/D converter are carried out the A/D conversion.A/D converter 22 is kept at transformation result in the register 32 as digital quantity.
Logical circuit 292 output is used for signal ADSEL0, ADSEL1 that the input of selector 52,72 is selected.In addition, logical circuit 292 can also be read the value of the register 32 in the A/D converter 22.In addition, logical circuit 292 can store the result who deducts the value of the 2nd register 86 from the value of the 1st register 84 in the 3rd register 88 by means of arithmetic unit 89.
Be configured in register 266 in the VDC circuit 262 and be storage and be used to change the register of controlling value of the mode of operation of VDC circuit.Utilization is set in the value in the register 266, can select a kind in these 3 kinds of patterns of VDC normal operation mode, VDC direct mode operation and VDC stop mode.Under the VDC normal operation mode, VDC circuit 262 carries out above-mentioned common work.Under the straight-through pattern of VDC, reference voltage generating circuit 26 and differential amplifier 28 quit work, and voltage conversion circuit 268 does not carry out voltage transitions, basically the supply voltage VCC that is imported is directly exported as voltage VDCout.Under the VDC stop mode, VDC circuit 262 quits work, and voltage VDCout is by non-activation.
Logical circuit 292 also comprises the 4th register 294 and the 5th register 296 except that comprising the 1st～the 3rd register, this point is one of feature of embodiment 14.The higher limit of supply voltage VCC is stored in the 4th register 294, and the lower limit of supply voltage VCC is stored in the 5th register 296.In addition, if the value of storage is not in by the scope between two values of the 4th register 294 and 296 appointments of the 5th register in the 1st register 84, it is effective that then logical circuit 292 makes the mark of storage in NG flag register 298.
The following describes the overall work of semiconductor integrated circuit 290.
At first, from logical circuit 292 output signal MVDC, according to this signal, value is written in the register 266.The work that writes is carried out as follows: as writing command signal, write data through terminal 100～102 input data D1～Dm conducts through the part of terminal 16～18 from the external input signal I/O1～I/On of semiconductor integrated circuit 290.
At first VDC circuit 262 carries out the work that illustrated in embodiment 5 grades when the VDC normal operation mode.
Secondly, when being set at the VDC direct mode operation, 262 outputs of VDC circuit equate with supply voltage VCC that roughly the voltage of (low slightly) is as voltage VDCout.
Be used for selection signal ADSEL0 that the input of A/D converter 22 is selected from logical circuit 292 output, in view of the above, the input node AN0 ' of 52 pairs of A/D converters 22 of selector applies voltage VDCout.Voltage VDCout is carried out the A/D conversion by A/D converter, and its result is stored in the register 32.The value of register 32 is read by logical circuit 292, and the digital value corresponding with voltage VDCout is stored in the 1st memory 84.
The content of the 1st register 84 of logical circuit 292 inside can be read through terminal 100～102 from the outside of semiconductor integrated circuit 290.
By means of the control of logical circuit 292, the value of the 1st register 84 and the value of the 4th register 294 and the value of the 5th register 296 are compared.If in the scope between two values shown in the 4th register 294 and the 5th register 296, it is ineffective that then logical circuit 292 makes the NG mark for the value of the 1st register 84.
The value of the 4th register the 294, the 5th register 296 can read and write from the outside of semiconductor integrated circuit 290.In addition, the value of NG flag register 298 can read or remove from the outside of semiconductor integrated circuit 290.
In embodiment 14, the output voltage VDCout corresponding when the VDC direct mode operation with supply voltage VCC.Can confirm that this voltage VDCout is whether in the voltage range of predesignating by means of mark is read out.In view of the above, can carry out the supervision of supply voltage VCC.
Embodiment 15
Figure 22 is the block diagram of structure that the semiconductor integrated circuit 300 of embodiment 15 is shown.
With reference to Figure 22, semiconductor integrated circuit 300 comprises VDC circuit 302; A/D converter 22; Logical circuit 304; Flash memory 224; And selector 52 and 72, they are integrated on the 1 block semiconductor chip.
VDC circuit 302 comprises reference voltage generating circuit 98; Differential amplifier 147; Voltage conversion circuit 306; And register 96,146 and 266.
A/D converter 22 comprises the register 32 of storage A/D transformation result.
Logical circuit 304 comprises CPU the 308, the 1st register the 84, the 2nd register the 86, the 3rd register the 88, the 4th register the 294, the 5th register 296 and NG flag register 298.
Supply voltage VCC is supplied to VDC circuit 302, and supply voltage AVCC is supplied to A/D converter.Voltage VDCout as the output of VDC circuit 302 is supplied to logical circuit 304 as working power voltage.In addition, to flash memory 224 from outside supply line voltage FVCC.That is, each circuit block acceptance working power voltage separately carries out work.In addition, here, earthed voltage VSS is public to each circuit block just.
VDC circuit 302 comprises reference voltage generating circuit 98; Differential amplifier 147; Voltage conversion circuit 306; And register 96,146 and 266.VDC circuit 302 is accepted supply voltage VCC from the outside, output is as the reference voltage V DCref of the output of reference voltage generating circuit 98 with as the voltage VDCout of the output of voltage conversion circuit 306.
A/D converter 22 is accepted supply voltage AVCC as working power voltage.Then, A/D converter 22 is accepted the reference voltage Avref of A/D conversion usefulness through terminal 14.
Selector 52 is selected some analog signal AN0 and the voltage VDCout according to the signal ADSEL0 that applies from logical circuit 304, is applied to the input node AN0 ' of A/D converter 22.Selector 72 some according among signal ADSEL1 selection reference voltage VDCref and the analog signal AN1 is applied to the input node AN1 ' of A/D converter 22.
Signal I/O1～the I/On as control signal or data is imported, exported to logical circuit 304 through n the terminal 16～18 and the outside of semiconductor integrated circuit 300.In addition, logical circuit 304 data of reading/writing through the data of m terminal 100～102 exchange registers or by CPU 308 are as data D1～Dm.In addition, logical circuit 304 is exported address value A1～Ak that CPU 308 are exported through terminal 230～232.
Reference voltage generating circuit 98 becomes the reference voltage V DCref of benchmark of the output voltage V DCout of VDC circuit 302.Differential amplifier 147 is accepted voltage VDCref and voltage VDCout, and it is compared.
If voltage VDCout is lower than voltage VDCref, then differential amplifier 147 is so that the mode that voltage VDCout raises is sent to voltage conversion circuit 306 with control signal.On the other hand, if voltage VDCout is higher than voltage VDCref, then differential amplifier 147 is sent to voltage conversion circuit 306 in the mode that voltage VDCout is raise with control signal.
Voltage conversion circuit 306 generates than its low assigned voltage VDCout from supply voltage VCC according to the control signal from differential amplifier 147.
A/D converter 22 can carry out work according to the signal from logical circuit 304 and set.22 pairs of analog signals from input node AN0 ', AN1 ' input of A/D converter are carried out the A/D conversion, and transformation result is kept in the register 32 as digital quantity.
Logical circuit 304 output is used for signal ADSEL0, ADSEL1 that the input of selector 52,72 is selected.In addition, logical circuit 304 can also be read the value of the register 32 of A/D converter 22 inside.In addition, logical circuit 304 result that deducts the value of the reference voltage V DCref that the 2nd register 86 kept can the value with the voltage VDCout that kept from the 1st register 84 stores in the 3rd register 88.This work can be carried out by means of the subtraction function that CPU 308 is had.
The structure of reference voltage generating circuit 98 is illustrated with Fig. 7, so do not repeat its explanation.
Figure 23 is the circuit diagram that the structure of the voltage conversion circuit 3D6 among Figure 22 is shown.
With reference to Figure 23, voltage conversion circuit 306 comprises decoding and door is selected circuit 162, input-switching circuit 164, input permanent circuit 320 and drive circuit 166.Decoding and a door selection circuit 162, input-switching circuit 164 and drive circuit 166 with illustrated with Fig. 9 identical, so do not repeat its explanation.
Input permanent circuit 320 comprises: accept from the signal MVDCoff of register 266 outputs and with the phase inverter 322 of its counter-rotating; The P channel MOS transistor of be connected between the grid of power supply node and P channel MOS transistor 197, its grid being accepted the output of phase inverter 322 324; The P channel MOS transistor of be connected between the grid of power supply node and P channel MOS transistor 198, its grid being accepted the output of phase inverter 322 326; And be connected between the grid of power supply node and P channel MOS transistor 199, P channel MOS transistor 328 that its grid is accepted the output of phase inverter 322.
Input permanent circuit 320 also comprises: be connected between the grid and ground connection node of P channel MOS transistor 197, the N-channel MOS transistor 330 of its grid acknowledge(ment) signal MVDCthrough; Be connected between the grid and ground connection node of P channel MOS transistor 198, the N-channel MOS transistor 332 of its grid acknowledge(ment) signal MVDCthrough; And be connected between the grid and ground connection node of P channel MOS transistor 199, the N-channel MOS transistor 334 of its grid acknowledge(ment) signal MVDCthrough.
Reference voltage V DCref can be changed by the value of change setting in register 96, thereby voltage VDCout can be adjusted.In addition, the use number that drives with transistor 197～199 can be changed, in view of the above, the speed of following can be adjusted corresponding to load current by the setting of changing register 146.
In addition,, can under the VDC stop mode, signal MVDCoff be activated the level to H, P channel MOS transistor 197～199 all is set at nonconducting state, the non-activation of voltage VDCout by being set in the value of register 266.
In addition, by being set in the value of register 266, signal MVDCthrough can be activated the level to H when being set to the VDC direct mode operation, making P channel MOS transistor 197～199 all be in conducting state, supply voltage VCC directly is output as voltage VDCout.
Referring again to Figure 22, voltage conversion circuit 306 comprises a plurality of driving transistors, and the driving that becomes the number of benchmark is usually carried out work with transistor.The number of the driving transistors of work can change by means of the value of register 146.Voltage conversion circuit 306 is worked as follows: when the value of register 146 when negative, driving with transistorized number increases, and when this value is timing, drives with transistorized number minimizing.In addition, register 146 also can be stored the transistorized number of current drives of work, constitutes voltage conversion circuit 306 in the mode of being carried out work by the transistor of the number of register 146 appointments.
In addition, though register 146 is configured in the inside of VDC circuit 302 in Figure 22, it also can be configured in the inside of logical circuit 304 or zone in addition.In addition, the logical circuit 304 that the value of storage can involved CPU 308 in register 146 is read and is write.
Reference voltage generating circuit 98 can be exported the output voltage that becomes benchmark, and one or more voltages and one or more voltages that are lower than it of being higher than it.Can utilize the value of register 96 that these voltages are selected.Though register 96 is configured in the inside of VDC circuit 302 in Figure 22, also can be configured in the inside of logical circuit 304 or zone in addition.
Be configured in register 266 in the VDC circuit 302 and be storage and be used to change the register of controlling value of the mode of operation of VDC circuit.Utilization is set in the value in the register 266, can select a kind in these 3 kinds of patterns of VDC normal operation mode, VDC direct mode operation and VDC stop mode.Under the VDC normal operation mode, VDC circuit 302 carries out above-mentioned common work.Under the straight-through pattern of VDC, reference voltage generating circuit 26 and differential amplifier 147 quit work, and voltage conversion circuit 306 does not carry out voltage transitions, basically the supply voltage VCC that is imported is directly exported as voltage VDCout.Under the VDC stop mode, VDC circuit 302 quits work, and voltage VDCout is by non-activation.In addition, though register 266 is configured in the inside of VDC circuit 302 in Figure 22, also can be configured in logical circuit 304 inside.
Logical circuit 304 also comprises the 4th register 294 and the 5th register 296 except that comprising the 1st～the 3rd register, this point is one of feature of embodiment 15.The higher limit of supply voltage VCC is stored in the 4th register 294, and the lower limit of supply voltage VCC is stored in the 5th register 296.In addition, if the value of storage is not in by the scope between two values of the 4th register 294 and 296 appointments of the 5th register in the 1st register 84, it is effective that then logical circuit 304 makes the mark of storage in NG flag register 298.
The following describes the overall work of semiconductor integrated circuit 300.
The data of having used when in flash memory 224, having disposed the performed instruction column of CPU 308 and having carried out these instructions.Being used for carrying out instruction column (program) that the CPU of the work of embodiment 15 uses and the parameter of using in these instructions (data) also is stored in the flash memory 224.When the power connection of semiconductor integrated circuit 300, when resetting, perhaps during this program of program start beyond this program of customer requirements, can carry out program in flash memory 224 stored.
By carrying out the control of the CPU 308 of work, value is write in the register 266 of Control work pattern by means of the program that starts in such a manner.
At first, when the VDC normal operation mode, VDC circuit 302 carries out the work that illustrated in embodiment 5 grades.
Secondly, when being set at the VDC direct mode operation, 302 outputs of VDC circuit equate with supply voltage VCC that roughly the voltage of (low slightly) is as voltage VDCout.
Be used for selection signal ADSEL0 that the input of A/D converter 22 is selected from logical circuit 304 output, in view of the above, the input node AN0 ' of 52 pairs of A/D converters 22 of selector applies voltage VDCout.Voltage VDCout is carried out the A/D conversion by A/D converter, and its result is stored in the register 32.The value of register 32 is read by logical circuit 304, and the digital value corresponding with voltage VDCout is stored in the 1st memory 84.
The content of the 1st register 84 of logical circuit 304 inside can be read through terminal 100～102 from the outside of semiconductor integrated circuit 300.
When being set at the VDC stop mode, voltage conversion circuit 306 is driving voltage VDCout not.Therefore, logical circuit 304 can not be worked.At this moment, input resets (not shown), connects once more after perhaps closing supply voltage VCC once.
When under the VDC direct mode operation, working, the content of the 1st register 84 and the value of the 4th register 294 and the value of the 5th register 296 are compared.If when the value of the 1st register 84 was not a value between the value of the value of the 4th register 294 and the 5th register 296, the NG mark became effectively.The content of the value of each register or NG mark can be passed through input, lead-out terminal 16～18, or the terminal 100～102 that data/address bus connected exports the outside of semiconductor integrated circuit 300 to.
As previously discussed, in embodiment 15, can the VDC direct mode operation be set to VDC circuit 302, VCC observes from the outside as digital value with supply voltage.Meanwhile, by the CPU that carries out work by means of program stored in flash memory is installed, can easily manage supply voltage VCC.That is,, can change higher limit, the lower limit of supply voltage VCC according to system by changing the parameter in the flash memory.
In addition, reduce, in the time of can not obtaining under normal mode, making the required voltage VDCout of VDC circuit 302 work, can switch to the VDC direct mode operation, improve service voltage, the information of necessity is retreated in the flash memory logical circuit 304 at supply voltage VCC.
Embodiment 16
Figure 24 is the block diagram of structure that the semiconductor integrated circuit 350 of embodiment 16 is shown.
With reference to Figure 24, semiconductor integrated circuit 350 comprises: VDC circuit 302; A/D converter 22; Logical circuit 352; And selector 52 and 72, these circuit are integrated on the 1 block semiconductor chip.Each circuit has special-purpose separately input, lead-out terminal.
Now power supply is described.VDC circuit 302 is accepted supply voltage VCC through terminal 2.A/D converter 22 is accepted supply voltage AVCC through terminal 12.The logical circuit 352 that comprises CPU 356 is accepted voltage VDCout as the output of VDC circuit 302 as supply voltage.That is, each circuit block acceptance supply voltage separately carries out work.Here, earthed voltage VSS is public to each circuit block just.
VDC circuit 302 comprises: reference voltage generating circuit 98; Differential amplifier 147; Voltage conversion circuit 306 and register 96,146 and 266.VDC circuit 302 is accepted supply voltage VCC from the outside, output is as the reference voltage V DCref of the output of reference voltage generating circuit 98 with as the voltage VDCout of the output of voltage conversion circuit 306.
A/D converter 22 is accepted supply voltage AVCC as working power voltage.Then, A/D converter 22 is accepted the reference voltage Avref of A/D conversion usefulness through terminal 14.
Selector 52 is selected some analog signal AN0 and the voltage VDCout according to the signal ADSEL0 that applies from logical circuit 352, is applied to the input node AN0 ' of A/D converter 22.Selector 72 some according among signal ADSEL1 selection reference voltage VDCref and the analog signal AN1 is applied to the input node AN1 ' of A/D converter 22.
Logical circuit 352 comprises CPU356, the 1st register the 84, the 2nd register the 86, the 3rd register 88, SRAM 254 and mask rom 354.Signal I/O1～the I/On as control signal or data is imported, exported to logical circuit 352 through n the terminal 16～18 and the outside of semiconductor integrated circuit 350.In addition, logical circuit 352 data of reading/writing through the data of m terminal 100～102 exchange registers or by CPU 356 are as data D1～Dm.In addition, logical circuit 352 is exported address value A1～Ak that CPU 356 are exported through terminal 230～232.
Reference voltage generating circuit 98 becomes the reference voltage V DCref of benchmark of the output voltage V DCout of VDC circuit 302.Differential amplifier 147 is accepted voltage VDCref and voltage VDCout, and it is compared.
If voltage VDCout is lower than voltage VDCref, then differential amplifier 147 is so that the mode that voltage VDCout raises is sent to voltage conversion circuit 306 with control signal.On the other hand, if voltage VDCout is higher than voltage VDCref, then differential amplifier 147 is sent to voltage conversion circuit 306 in the mode that voltage VDCout is raise with control signal.
Voltage conversion circuit 306 generates than its low assigned voltage VDCout from supply voltage VCC according to the control signal from differential amplifier 147.
A/D converter 22 can carry out work according to the signal from logical circuit 352 and set.22 pairs of analog signals from input node AN0 ', AN1 ' input of A/D converter are carried out the A/D conversion, and transformation result is kept in the register 32 as digital quantity.
Logical circuit 352 output is used for signal ADSEL0, ADSEL1 that the input of selector 52,72 is selected.In addition, logical circuit 352 can also be read the value of the register 32 of A/D converter 22 inside.In addition, logical circuit 352 result that deducts the value of the reference voltage V DCref that the 2nd register 86 kept can the value with the voltage VDCout that kept from the 1st register 84 stores in the 3rd register 88.This work can be carried out by means of the subtraction function that CPU 356 is had.
The structure of reference voltage generating circuit 98 and voltage conversion circuit 306 is illustrated with Fig. 7 and Figure 23, so do not repeat its explanation.
Voltage conversion circuit 306 comprises a plurality of driving transistors, and the driving that becomes the number of benchmark is usually carried out work with transistor.The driving of work can change by means of the value of register 146 with transistorized number.Voltage conversion circuit 306 is worked as follows: when the value of register 146 when negative, driving with transistorized number increases, and when this value is timing, drives with transistorized number minimizing.In addition, register 146 also can be stored the transistorized number of current drives of work, constitutes voltage conversion circuit 306 in the mode of being carried out work by the transistor of the number of register 146 appointments.
In addition, though register 146 is configured in the inside of VDC circuit 302 in Figure 24, it also can be configured in the inside of logical circuit 352 or zone in addition.In addition, the logical circuit 352 that the value of storage can involved CPU 356 in register 146 is read and is write.
Be configured in register 266 in the VDC circuit 302 and be storage and be used to change the register of controlling value of the mode of operation of VDC circuit.Utilization is set in the value in the register 266, can select a kind in these 3 kinds of patterns of VDC normal operation mode, VDC direct mode operation and VDC stop mode.
Under the VDC normal operation mode, VDC circuit 302 carries out above-mentioned common work.Under the straight-through pattern of VDC, reference voltage generating circuit 26 and differential amplifier 147 quit work, and voltage conversion circuit 306 does not carry out voltage transitions, basically the supply voltage VCC that is imported is directly exported as voltage VDCout.Under the VDC stop mode, VDC circuit 302 quits work, and voltage VDCout is by non-activation.In addition, though register 266 is configured in the inside of VDC circuit 302 in Figure 24, also can be configured in the inside of logical circuit 352.
Logical circuit 352 also comprises the 4th register 294 and the 5th register 296 except that comprising the 1st～the 3rd register, this point is one of feature of embodiment 16.The higher limit of supply voltage VCC is stored in the 4th register 294, and the lower limit of supply voltage VCC is stored in the 5th register 296.In addition, if the value of storage is not in by the scope between two values of the 4th register 294 and 296 appointments of the 5th register in the 1st register 84, it is effective that then logical circuit 352 makes the mark of storage in NG flag register 298.
The following describes the overall work of semiconductor integrated circuit 350.
The storage of using during these instructions of instruction column that CPU 356 carries out and execution is in the memory devices such as EEPROM (not shown) that are disposed at semiconductor integrated circuit 350 outsides.
In mask rom 354, disposed and be used for the instruction column in the above-mentioned memory device and data load, the work of CPU 356 has been moved into the program (boot) in the program of this loading to SRAM 254.
When semiconductor integrated circuit 350 resets, this boot work when perhaps other programs in the mask rom require this boot to start.Below the work that guides to the program in the SRAM 254 by this boot when resetting is described.
By carrying out the control of the CPU 356 of work by means of the program that starts in such a manner, the information that will be used for the pattern of setting writes register 266.
At first, VDC circuit 302 carries out the work that illustrated in embodiment 5 grades when the VDC normal operation mode.
Secondly, when being set at the VDC direct mode operation, 302 outputs of VDC circuit equate with supply voltage VCC that roughly the voltage of (low slightly) is as voltage VDCout.
Be used for selection signal ADSEL0 that the input of A/D converter 22 is selected from logical circuit 352 output, in view of the above, the input node AN0 ' of 52 pairs of A/D converters 22 of selector applies voltage VDCout.Voltage VDCout is carried out the A/D conversion by A/D converter, and its result is stored in the register 32.The value of register 32 is read by logical circuit 352, and the digital value corresponding with voltage VDCout is stored in the 1st memory 84.
The content of the 1st register 84 of logical circuit 352 inside can be read through terminal 100～102 from the outside of semiconductor integrated circuit 350.
When being set at the VDC stop mode, voltage conversion circuit 306 is driving voltage VDCout not.Therefore, logical circuit 352 can not be worked.At this moment, input resets (not shown), connects once more after perhaps closing supply voltage VCC once.
When under the VDC direct mode operation, working, the content of the 1st register 84 and the value of the 4th register 294 and the value of the 5th register 296 are compared.If when the value of the 1st register 84 was not a value between the value of the value of the 4th register 294 and the 5th register 296, the NG mark became effectively.The content of the value of each register or NG mark can be passed through input, lead-out terminal 16～18, or the terminal 100～102 that data/address bus connected exports the outside of semiconductor integrated circuit 350 to.
As mentioned above, in embodiment 16, VDC circuit 302 is provided with the VDC direct mode operation.In view of the above, the supply voltage VCC of input VDC circuit can be observed as digital value.Meanwhile, on mask rom 354, disposed boot, regulated procedure has been loaded among the SRAM 254.By the CPU 356 that carries out work by means of the program of this loading is installed, can easily manage supply voltage VCC.That is, can detect supply voltage VCC and reduce etc. unusually, in addition,, can change higher limit and the lower limit of supply voltage VCC according to system by the parameter of change in the EEPROM of the exterior arrangement of semiconductor integrated circuit 350.
In addition, in embodiment 16, owing to by means of the boot on the mask rom 354 program is loaded into from be configured in outside EEPROM etc. and is carried out by CPU356 among the built-in SRAM 254,, can reduce the process number of processing of wafers so compare with the situation that flash memory is installed.Therefore, can reduce the manufacturing cost of semiconductor integrated circuit.
Though explain and show the present invention, these are exemplary, rather than restrictive, and the spirit and scope of invention are only limited by appended claim scope.Be intended to comprise with claim equivalence and scope in all changes.

Claims (15)

1. semiconductor integrated circuit,
Possess:
The 1st terminal of the outer power voltage that acceptance applies from the outside;
Reduce the voltage generating circuit of said external supply voltage, generation builtin voltage;
Use the internal circuit of above-mentioned builtin voltage;
Above-mentioned builtin voltage is converted to the A/D change-over circuit of digital value to outside output digital signal from the analogue value; And
Be used for exporting above-mentioned digital signal to outside the 2nd terminal.
2. semiconductor integrated circuit as claimed in claim 1,
Above-mentioned builtin voltage is the working power voltage of above-mentioned internal circuit,
Above-mentioned voltage generating circuit comprises:
Produce the reference voltage generating circuit of the reference voltage of above-mentioned working power voltage;
Accept the differential amplifier circuit of above-mentioned working power voltage and said reference voltage at 2 inputs of complementation; And
Output according to above-mentioned differential amplifier circuit is changed the said external supply voltage, exports the voltage conversion circuit of above-mentioned working power voltage.
3. semiconductor integrated circuit as claimed in claim 1,
Above-mentioned builtin voltage is the reference voltage of benchmark that becomes the working power voltage of above-mentioned internal circuit,
Above-mentioned voltage generating circuit comprises:
Produce the reference voltage generating circuit of said reference voltage;
Accept the differential amplifier circuit of above-mentioned working power voltage and said reference voltage at 2 inputs of complementation; And
Output according to above-mentioned differential amplifier circuit is changed the said external supply voltage, exports the voltage conversion circuit of above-mentioned working power voltage.
4. semiconductor integrated circuit as claimed in claim 1,
Above-mentioned semiconductor integrated circuit also possesses:
The 3rd terminal that is used for input analog voltage; And
Select the side in above-mentioned builtin voltage and the above-mentioned aanalogvoltage, the selector that above-mentioned A/D change-over circuit is applied.
5. semiconductor integrated circuit as claimed in claim 1,
Above-mentioned builtin voltage is the working power voltage of above-mentioned internal circuit,
Above-mentioned voltage generating circuit comprises:
Produce the reference voltage generating circuit of reference voltage;
Accept the differential amplifier circuit of above-mentioned working power voltage and said reference voltage at 2 inputs of complementation; And
Output according to above-mentioned differential amplifier circuit is changed the said external supply voltage, exports the voltage conversion circuit of above-mentioned working power voltage,
The the 1st, the 2nd input node of above-mentioned A/D change-over circuit is accepted above-mentioned working power voltage, said reference voltage respectively, and above-mentioned working power voltage, said reference voltage are converted to the 1st, the 2nd digital value respectively,
Above-mentioned internal circuit comprises:
Temporary transient the 1st, the 2nd register that keeps above-mentioned the 1st, the 2nd digital value;
The computing circuit that the difference that remains on above-mentioned the 1st, the 2nd digital value in above-mentioned the 1st, the 2nd register is respectively exported as the 3rd digital value; And
Temporary transient the 3rd register that keeps above-mentioned the 3rd digital value,
The retention value of above-mentioned the 1st～the 3rd register is exported from above-mentioned the 2nd terminal.
6. semiconductor integrated circuit as claimed in claim 5,
Above-mentioned voltage generating circuit also comprises the 4th register,
The said reference voltage generating circuit is adjusted said reference voltage according to the retention value of above-mentioned the 4th register.
7. semiconductor integrated circuit as claimed in claim 5,
Above-mentioned voltage generating circuit also comprises the 4th register,
Above-mentioned voltage conversion circuit is adjusted the driving force that the node that is used to export above-mentioned internal power source voltage drives according to the retention value adjustment of above-mentioned the 4th register.
8. semiconductor integrated circuit as claimed in claim 5,
Above-mentioned voltage generating circuit also comprises the Zapping circuit that can change its setting non-volatilely,
The said reference voltage generating circuit is adjusted said reference voltage according to the setting of above-mentioned Zapping circuit.
9. semiconductor integrated circuit as claimed in claim 5,
Above-mentioned voltage generating circuit also comprises the Zapping circuit that can change its setting non-volatilely,
The driving force that above-mentioned voltage conversion circuit drives the node that is used to export above-mentioned internal power source voltage according to the setting adjustment of above-mentioned Zapping circuit.
10. semiconductor integrated circuit as claimed in claim 5,
Above-mentioned computing circuit is the central arithmetic processing apparatus that carries out computing according to instruction column,
Above-mentioned semiconductor integrated circuit also possesses the non-volatile memory of the above-mentioned instruction column of storage.
11. semiconductor integrated circuit as claimed in claim 10,
The 4th register of the adjusted value of the above-mentioned builtin voltage that above-mentioned voltage generating circuit also comprises maintenance and produced,
Above-mentioned non-volatile memory also keeps the initial value of above-mentioned adjusted value,
Above-mentioned central arithmetic processing apparatus is rewritten the retention value of above-mentioned the 4th register according to the retention value of above-mentioned the 3rd register.
12. semiconductor integrated circuit as claimed in claim 10,
Also possess the input terminal of setting for mode switch,
Above-mentioned central arithmetic processing apparatus has as mode of operation: normal mode; And the special pattern of exporting as the 3rd digital value with the difference that remains on above-mentioned the 1st, the 2nd digital value in above-mentioned the 1st, the 2nd register respectively, the setting of the above-mentioned input terminal during according to power supply opening is transferred to above-mentioned special pattern.
13. semiconductor integrated circuit as claimed in claim 5,
Above-mentioned computing circuit is the central arithmetic processing apparatus that carries out computing according to instruction column,
Above-mentioned semiconductor integrated circuit also possesses:
Store the non-volatile memory of the information of above-mentioned instruction column and regulation; And
The volatile memory that is connected with above-mentioned central arithmetic unit, afore mentioned rules information is loaded from above-mentioned non-volatile memory by means of boot as the part of above-mentioned instruction column.
14. semiconductor integrated circuit as claimed in claim 5,
Above-mentioned voltage conversion circuit has as mode of operation: the normal mode that reduces the said external supply voltage; And the said external supply voltage is not changed and with the special pattern of its output,
Under above-mentioned special pattern, above-mentioned the 1st digital value is corresponding with the said external supply voltage, and from above-mentioned the 2nd terminal output.
15. semiconductor integrated circuit as claimed in claim 5,
Above-mentioned internal circuit also comprises:
The 4th register that keeps the upper limit standard value of above-mentioned internal power source voltage; And
The 5th register that keeps the lower limit standard value of above-mentioned internal power source voltage,
When the retention value of above-mentioned the 1st register is not between above-mentioned upper limit standard value and above-mentioned lower limit standard value, above-mentioned computing circuit output abnormality mark.
CNA2004100617474A 2003-09-10 2004-06-30 Semiconductor integrated circuit in which voltage down converter output can be observed as digital value Pending CN1595807A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003318749A JP2005086108A (en) 2003-09-10 2003-09-10 Semiconductor integrated circuit
JP318749/2003 2003-09-10

Publications (1)

Publication Number Publication Date
CN1595807A true CN1595807A (en) 2005-03-16

Family

ID=34225336

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2004100617474A Pending CN1595807A (en) 2003-09-10 2004-06-30 Semiconductor integrated circuit in which voltage down converter output can be observed as digital value

Country Status (5)

Country Link
US (1) US7173549B2 (en)
JP (1) JP2005086108A (en)
KR (1) KR100600219B1 (en)
CN (1) CN1595807A (en)
DE (1) DE102004031146A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103246308A (en) * 2013-01-25 2013-08-14 钰创科技股份有限公司 Multi-input low-voltage drop voltage stabilizer

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3861874B2 (en) * 2003-12-16 2006-12-27 株式会社デンソー AD converter failure detection device
US7935377B2 (en) * 2004-06-04 2011-05-03 Ajinomoto Co., Inc. Crystals of free (2R, 4R)-monatin and use thereof
JP5347270B2 (en) * 2008-01-08 2013-11-20 富士通セミコンダクター株式会社 Semiconductor device and control method thereof
WO2010113263A1 (en) * 2009-03-31 2010-10-07 富士通株式会社 Semiconductor integrated circuit and power source voltage control method
JP2011053957A (en) * 2009-09-02 2011-03-17 Toshiba Corp Reference current generating circuit
JP5308298B2 (en) * 2009-09-29 2013-10-09 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー Reset circuit
JP5569245B2 (en) * 2010-08-17 2014-08-13 セイコーエプソン株式会社 Integrated circuit device and electronic apparatus
JP5981815B2 (en) 2012-09-18 2016-08-31 キヤノン株式会社 Printhead substrate and printing apparatus
KR102073966B1 (en) * 2013-12-11 2020-02-06 삼성디스플레이 주식회사 System for inspection a display panel
US9853652B2 (en) * 2015-07-22 2017-12-26 Samsung Electronics Co., Ltd Semiconductor device performing common mode voltage compensation using analog-to-digital converter
JP6302513B2 (en) * 2016-07-13 2018-03-28 キヤノン株式会社 Printhead substrate and printing apparatus
JP6470858B2 (en) * 2018-02-22 2019-02-13 キヤノン株式会社 Substrate, liquid discharge head, and liquid discharge apparatus

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4005409A (en) * 1975-03-10 1977-01-25 Robertshaw Controls Company Multiple mode input analog controller having standby power supply and absence-of-input sensing
US5329111A (en) * 1991-06-27 1994-07-12 Omron Corporation Image reader with adjustable contrast range
US5254992A (en) * 1991-10-31 1993-10-19 Fairbanks Inc. Low power electronic measuring system
JPH05325580A (en) 1992-05-28 1993-12-10 Mitsubishi Electric Corp Nonvolatile memory
US5764541A (en) * 1995-12-22 1998-06-09 Hermann Finance Corporation Ltd. Microprocessor controlled sensor signal conditioning circuit
US6801247B1 (en) * 1996-12-12 2004-10-05 Nikon Corporation Vibration reduction device and vibration detecting device and micro signal processing device for use in vibration reduction device
JPH1166890A (en) * 1997-08-12 1999-03-09 Mitsubishi Electric Corp Semiconductor integrated circuit device
JP4229482B2 (en) * 1997-10-24 2009-02-25 株式会社ルネサステクノロジ Microcomputer with built-in flash memory
US6285191B1 (en) * 1999-10-08 2001-09-04 Alliedsignal Inc. Measurement of current in a vehicle using battery cable as a shunt
WO2003012376A1 (en) * 2000-05-15 2003-02-13 Hitachi, Ltd. Thermal air flow rate measuring apparatus and its flowmeter and internal combustion engine and thermal air flow rate measuring method using it
JP4047558B2 (en) * 2001-05-29 2008-02-13 松下電器産業株式会社 Battery voltage detector
JP4130877B2 (en) * 2002-06-19 2008-08-06 株式会社日立製作所 Flow meter and flow meter system
US6801146B2 (en) * 2002-11-14 2004-10-05 Fyre Storm, Inc. Sample and hold circuit including a multiplexer
US6906500B2 (en) * 2002-11-14 2005-06-14 Fyre Storm, Inc. Method of operating a switching power converter
US6873271B2 (en) * 2003-08-05 2005-03-29 Lucent Technologies Inc. Power supply

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103246308A (en) * 2013-01-25 2013-08-14 钰创科技股份有限公司 Multi-input low-voltage drop voltage stabilizer
TWI474149B (en) * 2013-01-25 2015-02-21 Etron Technology Inc Multi-input low dropout regulator

Also Published As

Publication number Publication date
US20050052307A1 (en) 2005-03-10
JP2005086108A (en) 2005-03-31
KR20050026848A (en) 2005-03-16
KR100600219B1 (en) 2006-07-13
US7173549B2 (en) 2007-02-06
DE102004031146A1 (en) 2005-05-04

Similar Documents

Publication Publication Date Title
CN1232986C (en) Internal voltage level control circuit semiconductor memory device and their control method
CN1123892C (en) Non-volatile semi-conductor storage
CN1252914C (en) Differential circuit, amplifying circuit, driving circuit and display device using them
CN100345294C (en) Fuse circuit
CN1120425C (en) Memory controller and memory control system
CN1206657C (en) Flash memory
CN1677570A (en) Nonvolatile semiconductor memory device for writing multivalued data
CN1277247C (en) Electrical level shifting circuit and display device including it
CN1262066C (en) Timer circuit and semiconductor memory incorporating the timer circuit
CN1130775C (en) Medium voltage generating circuit and nonvolatile semiconductor memory containing same
CN1948974A (en) Semiconductor integrated circuit device and electronic equipment
CN1976229A (en) Semiconductor integrated circuit and method of reducing leakage current
CN1975931A (en) Non-volatile semiconductor memory device
CN1925058A (en) Semiconductor device
CN1595807A (en) Semiconductor integrated circuit in which voltage down converter output can be observed as digital value
CN1201519C (en) Data consistance checking device and data sorting device
CN1263042C (en) Fetch circuit, reference circuit and semiconductor storage device
CN1568569A (en) Voltage detection circuit and internal voltage generation circuit using same
CN1629760A (en) Current amplifying circuit with stabilized output voltage and liquid crystal display including the same
CN1905075A (en) Semiconductor memory device
CN1119816C (en) Synchronous semiconductor storage device having timed circuit of controlling activation/non-activation of word line
CN1905057A (en) Memory
CN1661661A (en) Liquid crystal display device
CN1099761C (en) Output circuit and electronic device using the circuit
CN1480948A (en) Semiconductor memory able to reduce input/output terminal

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication