CN1585312A - Method for converting asynchronous clock zone into synchronous one - Google Patents
Method for converting asynchronous clock zone into synchronous one Download PDFInfo
- Publication number
- CN1585312A CN1585312A CN 03153668 CN03153668A CN1585312A CN 1585312 A CN1585312 A CN 1585312A CN 03153668 CN03153668 CN 03153668 CN 03153668 A CN03153668 A CN 03153668A CN 1585312 A CN1585312 A CN 1585312A
- Authority
- CN
- China
- Prior art keywords
- address
- signal
- reading
- asynchronous
- write address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
- Time-Division Multiplex Systems (AREA)
Abstract
The invention supplies the method of converting the asynchronous timing into the synchronizing timing. Directly utilize the synchronizing timing to sample the asynchronous addressing status signal with the predetermined regulation. On the specific addressing position, the addressing of the synchronizing time is adjusted, thus achieves the conversion of the asynchronous timing and the processing of the different asynchronous frame simultaneously.
Description
Technical field
The present invention relates to clock zone switch technology field, be meant a kind of method that asynchronous clock domain is converted to the synchronised clock territory especially.
Background technology
In the interface chip logical design, entering signal that chip internal handles from interface all is that form with Frame transmits, and is asynchronous signal for the main processing clock of chip.Owing to can have certain differing or frequency jitter in short-term between the different clocks, can steady operation in order to make chip, asynchronous signal need be transformed into the synchronised clock territory from asynchronous clock domain, to obtain stable synchronizing signal, afterwards, carry out subsequent treatment again.
Because the frame head between the asynchronous signal does not normally line up, and the inner signal that needs to handle the frame head complete matching of interface chip, therefore, finish the conversion of clock zone at this asynchronous signal after, also to do the processing of frame head alignment again.
Be example with up master, diversity signal in broadband CDMA (WCDMA) system below, specify this asynchronous signal is transformed into the synchronised clock territory from asynchronous clock domain, and realize the method for frame head alignment.
Generally transferring asynchronous clock domain to the synchronised clock territory adopts the method for double-interface RAM buffer data to realize usually.Figure 1 shows that the implementation structure figure of asynchronous signal clock zone conversion in the prior art.Produce the dual port RAM write address with asynchronous clock signal, with the address of reading that synchronised clock produces dual port RAM, this dual port RAM degree of depth is that the scope of tolerating as required of frequency difference is in short-term determined.Respectively read/write address is converted to corresponding Gray code, again with synchronised clock sampling and compare, to judge that distance between the read/write address is whether less than the minimum range that the reading and writing conflict may take place, i.e. " risk distance ", if, then will read the address and jump turnback, and be about to read the address and jump to behind current location address farthest, carry out read operation again; Read the address otherwise needn't adjust, directly carry out read operation.The data that read out like this are stable and correct, and have shielded phase difference between asynchronous clock and the local synchronous clock and of short duration frequency jitter.
The above-mentioned method of reading to jump turnback in the address is: establishing and reading the address is r_add, and the RAM degree of depth is a, as r_add＞=a/2, and between the read/write address during less than risk distance, reads the address and jumps to the r_add-a/2 place; As r_add＜a/2, and between the read/write address during, read the address and jump to the r_add+a/2 place less than risk distance.For example, suppose that write address is 13, reading the address is 11, and " risk distance " is decided to be 3, and the RAM degree of depth is 16, because | 13-11|＜3, and 11＞16/2=8, therefore reading the address need adjust to 11-16/2=3.
The general two paths of data frame head registration process that realizes is to adopt the method for 2 grades of dual port RAMs.What Figure 2 shows that prior art is the structure chart that example realizes the frame head alignment with up master, diversity frame head.For convenience of description, suppose that frame length is 8, the dual port RAM degree of depth is 16.Owing to will satisfy the requirement of frame head alignment, therefore must know the particular location of frame head in dual port RAM, for making things convenient for the processing of frame head alignment, the dual port RAM degree of depth is got the integral multiple of frame length usually.For master, diversity data, be switched in the synchronised clock territory this moment, therefore, master, diversity frame head are carried out mould 2 countings respectively, according to the frame head count results counter is taken place in corresponding address and carry out set, its concrete set rule is as follows: the frame head count value is 0 and corresponding frame head when arriving, and appropriate address generation counter is changed to 8; The frame head count value is 1 and corresponding frame head when arriving, and appropriate address generation counter is changed to 0, and the write address of the value of counter as corresponding dual port RAM takes place in this address through set, and first data of each frame all are on address 0 or address 8 like this; The address of reading of dual port RAM only produces with the counter of a mould 16, similarly, local synchronizing frame head signal is carried out mould 2 countings, according to the frame head count results read address counter is carried out set, its set rule is the same, first data of so local synchronizing frame head also always from the address 0 or address 8 read; The initial value of write address counter is changed to 0, the initial condition of read address counter is changed to 8, thereby guaranteed that the read/write address distance just differs maximum in beginning, and realized the processing of frame head alignment.
The defective of said method is: the clock zone conversion need divide two steps to finish with the frame head registration process, can not realize data frame head registration process when finishing the clock zone conversion.And realize comparatively complexity, be difficult for understanding and causing the wasting of resources.
Summary of the invention
In view of this, the object of the present invention is to provide a kind ofly to convert asynchronous clock domain the method for synchronised clock territory to, when finishing the clock zone conversion, realize the processing of frame head alignment.
Technical scheme of the present invention is achieved in that in order to achieve the above object
A kind ofly convert asynchronous clock domain the method for synchronised clock territory to, this method may further comprise the steps:
Counter takes place in a, the corresponding address of each asynchronous signal that is provided with in the asynchronous clock domain, and counter takes place to its pairing address and carries out cycle set in the header signal of each asynchronous signal, with this value that counter takes place through address of set as each asynchronous signal the write address of corresponding dual port RAM, and the write address condition indicative signal of this dual port RAM is set according to the write address of dual port RAM;
B, asynchronous write address state index signal is sampled, obtain synchronous write address state index signal with synchronised clock;
Generation counter in the address of equal number in setting and the asynchronous clock domain in c, the synchronised clock territory, counter takes place to its pairing address and carries out cycle set in the header signal of each synchronizing signal, and the value that counter takes place for this address as each synchronizing signal corresponding dual port RAM read the address, according to synchronous write address state index signal, determine to read the judgement position of address according to preset rule, and adjust accordingly reading the address.
Preferably, described cycle set further may further comprise the steps:
It is that a is that frame length is the positive integer times t of K that the dual port RAM degree of depth is set, and frame head is carried out mould t counting;
When the frame head count value subtracts 1 value less than t, and when running into frame head, the value that counter taken place in the address be changed to the frame head count value add 1 on duty with frame length K; When the frame head count value is that t subtracts 1, and when running into frame head, the value that the address is taken place counter is changed to 0.
Preferably, the write address condition indicative signal that described write address according to dual port RAM is provided with this dual port RAM is: the write address condition indicative signal that write address header signal correspondence is set is a high level, and the length of write address condition indicative signal is greater than the length of pairing write address header signal.
Preferably, the frame length of asynchronous signal was more than or equal to 4 o'clock, the described method of determining to read the judgement position of address according to preset rule of step c is: the judgement position of reading the address equals n multiply by frame length K and subtracts 1 again, and n is smaller or equal to the natural number of dual port RAM degree of depth a divided by frame length K;
Step c is described to the corresponding method of adjustment of reading the address to be: judge that whether the distance of reading between address r_add and the write address w_add is smaller or equal to predefined risk distance L reading judging on the position of address, if, then the corresponding address of reading of order and this asynchronous signal equals to read the address and deducts frame length K and add 1 again, otherwise does not adjust to reading the address.
Preferably, described predefined risk distance L is less than half of frame length.
Preferably, the frame length of asynchronous signal is less than 4 o'clock,
The described method of determining to read the judgement position of address according to preset rule of step c is: the judgement position of reading the address be multiply by frame length K at n and is subtracted in 1 with cK uniformly-spaced again and extract, and n is smaller or equal to the natural number of dual port RAM degree of depth a divided by frame length K;
Step c is described to the corresponding method of adjustment of reading the address to be: judge that whether the distance of reading between address r_add and the write address w_add is smaller or equal to predefined risk distance L reading judging on the position of address, if, then the corresponding address of reading of order and this asynchronous signal equals to read the address and deducts and extract at interval that cK adds 1 again, otherwise does not adjust to reading the address.
Preferably, described predefined risk distance L is less than extracting half of spacing value.
Preferably, the asynchronous signal in the described asynchronous clock domain is two or more.
Use the present invention, directly use the asynchronous write state signal of the address in the synchronised clock sampling asynchronous clock domain, and application preset rule, in the specific address location of reading to reading address adjustment in the synchronised clock territory, make when realizing the conversion of asynchronous signal clock zone, realized the processing of the frame head alignment between the different asynchronous data frame.Use the present invention, implementation structure is simple, understands easily, has avoided complex process such as Gray code conversion, makes design cycle simplify greatly, has saved the logical resource of realizing.
Description of drawings
Fig. 1 is the implementation structure figure of asynchronous signal clock zone conversion in the prior art;
Fig. 2 is the structure chart that example realizes the frame head alignment for prior art with WCDMA system uplink master, diversity frame head;
Fig. 3 is the structure chart that example realizes clock zone conversion and frame head alignment simultaneously for using of the present invention with WCDMA system uplink master, diversity frame head;
Fig. 4 judges timing diagram for using write address of the present invention;
Fig. 5 is for using the schematic diagram of synchronised clock of the present invention to the sampling of asynchronous write address state index signal;
Fig. 6 is for using the adjusted sequential chart in address of reading of the present invention;
Embodiment
The present invention is further described in more detail below in conjunction with drawings and the specific embodiments.
Thinking of the present invention is: counter takes place in the corresponding address of each asynchronous clock signal in the asynchronous clock domain, and counter takes place to its pairing address and carries out cycle set in the header signal of each asynchronous signal, with this through the value of the counter of set as each asynchronous signal the write address of corresponding dual port RAM, and the asynchronous write address state index signal of this dual port RAM is set according to the write address of dual port RAM; With synchronised clock asynchronous write address state index signal is sampled, obtain synchronous write address state index signal; Generation counter in the address of equal number in setting and the asynchronous clock domain in the synchronised clock territory, counter takes place to its pairing address and carries out cycle set in the header signal of each synchronizing signal, the value of this counter as its corresponding dual port RAM read the address, according to synchronous write address state index signal, determine to read the judgement position of address according to preset rule, and adjust accordingly reading the address.
According to header signal to the rule that counter carries out cycle set be: establishing the RAM degree of depth is a, and frame length is K, and a=tK, t is a positive integer, frame head is carried out the counting of mould t, when the frame head count value is m, m＜t-1 and when running into frame head, the value that the address is taken place counter is changed to (m+1) K; M is t-1 when the frame head count value, and when running into frame head, because the count value cycle count, the value that therefore counter the address is taken place is changed to 0.
Be example with the up master in the WCDMA system, diversity signal below, specify its implementation.In the present embodiment, still setting frame length is 8, and the degree of depth of dual port RAM is 16, and the minimum " risk distance " that read/write conflict may take place is 3, and then t=16/8=2 only has two frames owing among each RAM, and therefore, frame head count value m can only be 0 and 1.
Figure 3 shows that the structure chart of the conversion of realization clock zone and the frame head alignment of present embodiment.Counter (cnt16 301 and cnt16302) takes place in the address that utilizes asynchronous clock to start two moulds 16 at asynchronous clock domain, and master, diversity frame head are carried out mould 2 respectively count, according to the frame head count results counter is taken place in corresponding address and carry out cycle set, the value of the counter of this process set is as the write address of the dual port RAM that is attached thereto; Write address state to two dual port RAMs carries out the state judgement respectively simultaneously, to obtain the write address condition indicative signal of two dual port RAMs respectively; Synchronised clock is sampled respectively to asynchronous write address state index signal, thereby obtains synchronous write address state index signal; Synchronised clock drives the address generation counter (cnt16 303 and cnt16 304) of two moulds 16 in the synchronised clock territory, simultaneously local synchronizing frame head is carried out mould 2 countings, according to the frame head count results counter is taken place in corresponding address and carry out set, the value of the counter of this process set is as the address of reading of the dual port RAM that is attached thereto, according to synchronous write address state index signal, and corresponding dual port RAM is with it read address adjustment according to preset rule.Specify with regard to each step below:
At first, counter cnt16301 and cnt16 302 take place in the address that asynchronous clock domain utilizes asynchronous clock to start two moulds 16, simultaneously master, diversity header signal are carried out mould 2 countings respectively, respectively counter is taken place in the address of the mould 16 of correspondence according to the frame head count results and carry out cycle set, promptly be 0 (when m＜t-1) and frame head arrive as frame head count value m, mould 16 counters of correspondence are changed to (0+1) * 8=8, when frame head count value m is 1 (m=n-1) and frame head when arriving, mould 16 counters of correspondence are changed to 0.The value of counter is judged respectively the write address state of two RAM simultaneously as the write address of two dual port RAMs after this process cycle set operation, obtains the write address condition indicative signal of two dual port RAMs respectively.As shown in Figure 4, because the two-way asynchronous signal frame length of coming in is 8, and the mould that counter takes place in the address is 16, therefore, the position that frame head writes can only be on the address 0 or address 8 of dual port RAM, because each asynchronous signal writes twice, with two write address condition indicative signals is that write address condition indicative signal 1 (state_ind1) and write address condition indicative signal 2 (state_ind2) are represented this two states that write respectively, state_ind1 represents near the state of the write address asynchronous data frame head of second frame, and state_ind2 represents near the state of the write address asynchronous data frame head of first frame, in the present embodiment, write address is { 6,7,8,9, during 10}, state_ind1 is a high level, and write address is { 14,15,0,1, during 2}, state_ind2 is a high level.
Secondly, asynchronous write address state index signal is sampled, obtain synchronous write address state index signal with synchronised clock.Figure 5 shows that and use the schematic diagram of synchronised clock of the present invention the sampling of asynchronous write address state index signal.Because the header signal of expression asynchronous write address state has 1 bit, and the duration is longer, so can be by synchronised clock to this asynchronous write address state index signal Direct Sampling, simultaneously, owing to be to the signal sampling in the asynchronous clock domain with synchronised clock, therefore can there be certain fringe in signal collected edge, it is the dash area among Fig. 5, but since should fuzzy part only influence to read the address be this time or adjusting next time, in a single day adjust and read the address, then should fuzzy part for the correct conversion of data without any influence.
At last, counter cnt16 303 and cnt16304 take place in the address that drives two moulds 16 with synchronised clock, simultaneously local synchronizing frame head signal is carried out mould 2 countings, carry out cycle set and handle according to the count results of local synchronizing frame head to the address of its pairing two moulds 16 counter is taken place, promptly be 0 (when m＜n-1) and frame head arrive as frame head count value m, mould 16 counters of correspondence are changed to 8 ((m+1) * 8), when frame head count value m is 1 (m=n-1) and frame head when arriving, mould 16 counters of correspondence are changed to 0.The value of this counter after set operation is as the address of reading of dual port RAM, according to synchronous write address state index signal dual port RAM read address adjustment.Figure 6 shows that and use the adjusted sequential chart in address of reading of the present invention.Because it is corresponding with an address generation counter in the asynchronous clock domain that counter takes place each address in the synchronised clock territory, that is to say that the corresponding asynchronous signal of counter takes place in each address in synchronised clock territory, its specifically adjustment scheme is:
Determine to read the judgement position of address, concrete definite method is n to be set for smaller or equal to the natural number of RAM degree of depth a divided by frame length K, and wherein, the RAM degree of depth is the integral multiple of frame length; The judgement position of reading the address is that n multiply by frame length and subtracts 1 again, and the judgement position of promptly reading the address is nK-1, and n＜=a/K, and n is a natural number.
Judge that whether the distance of reading between address r_add and the write address w_add is smaller or equal to predefined risk distance L reading judging on the position of address, this predefined risk distance L need satisfy 2L＜K, if | r_add-w_add|＜=L, then order is read the address and is equaled to read the address and deduct frame length K and add 1 again, even r_add=r_add-K+1 does not adjust otherwise this is read the address.
In the present embodiment, a=16, K=8, L=3, then n=2;
The judgement position of reading the address is 8-1=7,2 * 8-1=15;
When reading the address is 7, and | w_add-7|＜=3 o'clock, judge whether synchronous write address state index signal 1 (sync_state_ind1) is high level, if, then will be adjusted into r_add=7-8+1=0, not adjust otherwise this is read the address with the corresponding address of reading of this asynchronous signal;
When reading the address is 15, and | w_add-15|＜=3 o'clock, judge whether synchronous write address state index signal 2 (sync_state_ind2) is high level, if, then will read the address and be adjusted into r_add=15-8+1=8, otherwise being read the address, this does not adjust.
Through after such adjustment, make the data of from the RAM that stores master, diversity data, reading when finishing the clock zone conversion, realized the processing that master, diversity data frame head align.
Formula in the above-mentioned adjustment scheme only is applicable to that frame length is more than or equal to 4 situation, if frame length less than 4, then should be determined the adjustment position of reading the judgement position of address and reading the address in the following method.
When determining to read the judgement position of address, it is smaller or equal to the natural number of RAM degree of depth a divided by frame length K, wherein that n is set, the RAM degree of depth is the integral multiple of frame length, and the judgement position of reading the address is that n multiply by frame length and subtracts 1 again, and the judgement position of promptly reading the address is nK-1, and n＜=a/K, n are natural number.Because frame length is shorter, therefore, the judgement position of reading the address can be from K-1,2K-1,3K-1 ... with uniformly-spaced cK extraction, the position of then reading to judge the address is cK-1,2cK-1 among the nK-1 ... rcK-1, (r＜n).
Judge that whether the distance of reading between address r_add and the write address w_add is smaller or equal to predefined risk distance L reading judging on the position of address, this predefined risk distance L will satisfy 2L＜ck, if | w_add-r_add|＜=L, then the corresponding address of reading of order and this asynchronous signal equals to read the address and deducts and extract at interval that the value of cK adds 1 again, even r_add=r_add-cK+1, otherwise do not adjust to reading the address.
For example, a=16 is set, K=2, n=2 then, and establish L=1, ck=4,
The judgement position of reading the address can be 3,7,11,15;
The position of reading may adjust the address is:
When | w_add-3|＜=1, r_add=3-4+1=0;
When | w_add-7|＜=1, r_add=7-4+1=4;
When | w_add-11|＜=1, r_add=11-4+1=8;
When | w_add-15|＜=1, r_add=15-4+1=12;
It is two situation that the present invention is not only applicable to asynchronous signal, for plural asynchronous signal being converted to same clock zone and making the situation of its frame head alignment suitable equally.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1, a kind ofly convert asynchronous clock domain the method for synchronised clock territory to, it is characterized in that this method may further comprise the steps:
Counter takes place in a, the corresponding address of each asynchronous signal that is provided with in the asynchronous clock domain, and counter takes place to its pairing address and carries out cycle set in the header signal of each asynchronous signal, with this value that counter takes place through address of set as each asynchronous signal the write address of corresponding dual port RAM, and the write address condition indicative signal of this dual port RAM is set according to the write address of dual port RAM;
B, asynchronous write address state index signal is sampled, obtain synchronous write address state index signal with synchronised clock;
Generation counter in the address of equal number in setting and the asynchronous clock domain in c, the synchronised clock territory, counter takes place to its pairing address and carries out cycle set in the header signal of each synchronizing signal, and the value that counter takes place for this address as each synchronizing signal corresponding dual port RAM read the address, according to synchronous write address state index signal, determine to read the judgement position of address according to preset rule, and adjust accordingly reading the address.
2, method according to claim 1 is characterized in that, described cycle set further may further comprise the steps:
It is that a is that frame length is the positive integer times t of K that the dual port RAM degree of depth is set, and frame head is carried out mould t counting;
When the frame head count value subtracts 1 value less than t, and when running into frame head, the value that counter taken place in the address be changed to the frame head count value add 1 on duty with frame length K; When the frame head count value is that t subtracts 1, and when running into frame head, the value that the address is taken place counter is changed to 0.
3, method according to claim 1, it is characterized in that, the write address condition indicative signal that described write address according to dual port RAM is provided with this dual port RAM is: the write address condition indicative signal that write address header signal correspondence is set is a high level, and the length of write address condition indicative signal is greater than the length of pairing write address header signal.
4, method according to claim 1, it is characterized in that, the frame length of asynchronous signal was more than or equal to 4 o'clock, the described method of determining to read the judgement position of address according to preset rule of step c is: the judgement position of reading the address equals n multiply by frame length K and subtracts 1 again, and n is smaller or equal to the natural number of dual port RAM degree of depth a divided by frame length K;
Step c is described to the corresponding method of adjustment of reading the address to be: judge that whether the distance of reading between address r_add and the write address w_add is smaller or equal to predefined risk distance L reading judging on the position of address, if, then the corresponding address of reading of order and this asynchronous signal equals to read the address and deducts frame length K and add 1 again, otherwise does not adjust to reading the address.
5, method according to claim 4 is characterized in that, described predefined risk distance L is less than half of frame length.
6, method according to claim 1 is characterized in that, the frame length of asynchronous signal is less than 4 o'clock,
The described method of determining to read the judgement position of address according to preset rule of step c is: the judgement position of reading the address be multiply by frame length K at n and is subtracted in 1 with cK uniformly-spaced again and extract, and n is smaller or equal to the natural number of dual port RAM degree of depth a divided by frame length K;
Step c is described to the corresponding method of adjustment of reading the address to be: judge that whether the distance of reading between address r_add and the write address w_add is smaller or equal to predefined risk distance L reading judging on the position of address, if, then the corresponding address of reading of order and this asynchronous signal equals to read the address and deducts and extract at interval that cK adds 1 again, otherwise does not adjust to reading the address.
7, method according to claim 6 is characterized in that, described predefined risk distance L is less than extracting half of spacing value.
8, method according to claim 1 is characterized in that, the asynchronous signal in the described asynchronous clock domain is two or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031536689A CN100499420C (en) | 2003-08-19 | 2003-08-19 | Method for converting asynchronous clock zone into synchronous one |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031536689A CN100499420C (en) | 2003-08-19 | 2003-08-19 | Method for converting asynchronous clock zone into synchronous one |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1585312A true CN1585312A (en) | 2005-02-23 |
| CN100499420C CN100499420C (en) | 2009-06-10 |
Family
ID=34597804
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031536689A Expired - Fee Related CN100499420C (en) | 2003-08-19 | 2003-08-19 | Method for converting asynchronous clock zone into synchronous one |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100499420C (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1829129B (en) * | 2005-03-04 | 2010-12-22 | Ut斯达康通讯有限公司 | Method and apparatus for eliminating transmission delay difference in multipath synchronous data transmission |
| CN101056164B (en) * | 2007-05-31 | 2011-04-27 | 北京中星微电子有限公司 | A synchronization device across asynchronization clock domain signals |
| CN1859052B (en) * | 2005-12-29 | 2011-06-15 | 华为技术有限公司 | Asynchronous clock domain signal processing method and system |
| CN101253724B (en) * | 2005-08-01 | 2011-08-31 | Ati科技公司 | Bit-deskewing IO method and system |
| CN102708086A (en) * | 2012-05-10 | 2012-10-03 | 无锡华大国奇科技有限公司 | Elastic buffer structure and method applied to universal serial bus 3.0 (USB 3.0) |
| CN103576738A (en) * | 2012-08-01 | 2014-02-12 | 中兴通讯股份有限公司 | Method and device for clock domain crossing processing of asynchronous signals |
| CN105225533A (en) * | 2015-09-29 | 2016-01-06 | 成都川睿科技有限公司 | A kind of intelligent transportation communication system based on data first in first out |
-
2003
- 2003-08-19 CN CNB031536689A patent/CN100499420C/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1829129B (en) * | 2005-03-04 | 2010-12-22 | Ut斯达康通讯有限公司 | Method and apparatus for eliminating transmission delay difference in multipath synchronous data transmission |
| CN101253724B (en) * | 2005-08-01 | 2011-08-31 | Ati科技公司 | Bit-deskewing IO method and system |
| CN1859052B (en) * | 2005-12-29 | 2011-06-15 | 华为技术有限公司 | Asynchronous clock domain signal processing method and system |
| CN101056164B (en) * | 2007-05-31 | 2011-04-27 | 北京中星微电子有限公司 | A synchronization device across asynchronization clock domain signals |
| CN102708086A (en) * | 2012-05-10 | 2012-10-03 | 无锡华大国奇科技有限公司 | Elastic buffer structure and method applied to universal serial bus 3.0 (USB 3.0) |
| CN102708086B (en) * | 2012-05-10 | 2015-05-20 | 无锡华大国奇科技有限公司 | Elastic buffer structure and method applied to universal serial bus 3.0 (USB 3.0) |
| CN103576738A (en) * | 2012-08-01 | 2014-02-12 | 中兴通讯股份有限公司 | Method and device for clock domain crossing processing of asynchronous signals |
| CN105225533A (en) * | 2015-09-29 | 2016-01-06 | 成都川睿科技有限公司 | A kind of intelligent transportation communication system based on data first in first out |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100499420C (en) | 2009-06-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1905435A (en) | Methods and apparatus for clock synchronization | |
| CN1149801C (en) | Composition of sampling frequency offset and local oscillator frequency offset in OFDM receiver | |
| CN1149791C (en) | Data communication device | |
| CN1585312A (en) | Method for converting asynchronous clock zone into synchronous one | |
| CN1681249A (en) | Asynchronous data segmentation/transmission method for synchronous Ethernet and data structure used therein | |
| CN108833366B (en) | Control frame compression method based on AS6802 protocol | |
| CN1832351A (en) | General clock synchronizer and general clock synchronism method | |
| CN1298180C (en) | Mobile communication system, radio control device and mobile station | |
| CN1086533C (en) | A transmission circuit of a line encoded signal on a telephone line | |
| CN103957139A (en) | Ten-Gigabit Ethernet frame analyzing method based on FPGA | |
| CN1842070A (en) | Timing recovery circuit with multiple stages | |
| CN1132313C (en) | Over-sampling type clock recovery circuit with power consumption reduced | |
| CN1115779C (en) | Digital phase locked loop circuit and method therefor | |
| CN111049772A (en) | System and method for realizing 5G signal synchronous processing applied to vector signal analyzer platform | |
| CN1770634A (en) | Clock phase-locked loop apparatus | |
| CN1283060C (en) | Data receiving method based on clock signal and apparatus thereof | |
| CN1385972A (en) | Up high-speed data synchronous receiving method and circuit in optical communication system | |
| CN103036671B (en) | Without the bit synchronization system of Clock Extraction in all-digital demodulation | |
| CN101076002A (en) | Method and apparatus for acquiring circulating prefix-length information | |
| CN1897583A (en) | Multi-phase orthogonal clock generating circuit based on phase interpolation selection | |
| CN1862960A (en) | Fraction double interpolation multi-phase filter and filtering method | |
| CN1841978A (en) | Method and apparatus for realizing multipath signal re-timing | |
| CN1213916A (en) | Method and apparatus for detecting timeout of ATM reception packet | |
| CN1859052A (en) | Asynchronous clock domain signal processing method and system | |
| CN1556603A (en) | PHS system position synchronous method based on digital lock phase ring and realizing device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090610 Termination date: 20200819 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |