CN1567212A - Testing method for instruction cache - Google Patents
Testing method for instruction cache Download PDFInfo
- Publication number
- CN1567212A CN1567212A CN 03148716 CN03148716A CN1567212A CN 1567212 A CN1567212 A CN 1567212A CN 03148716 CN03148716 CN 03148716 CN 03148716 A CN03148716 A CN 03148716A CN 1567212 A CN1567212 A CN 1567212A
- Authority
- CN
- China
- Prior art keywords
- test
- machine code
- testing
- code
- instruction cache
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
Abstract
It is a kind of testing method of instruction cache. It generates testing function by writing the executable machine code to memory directly. So the code volume of testing machine code is variable and under control. It comprises the following steps: first, it assigns a section of memory space for testing. Then it writes executable machine code to the memory space, and tests the executable machine code as the testing function. Further it verifies the execution result of testing function. At last it releases the memory space.
Description
Technical field
The present invention relates to a kind of method of testing of instruction cache, be meant especially a kind ofly to generate trial function by directly in internal memory, writing executable machine code, thus the variable and in check instruction cache method of testing of size of code of machine when making test.
Background technology
High-speed cache (Cache) is a requisite ingredient in the current central processing unit (CPU), because in the computer system, the processing speed of internal memory (Memory) in order to remedy both speed differences, just must increase Cache far below CPU in CPU.The foundation that increases the Cache function is a principle of locality, and promptly the address access stream of program has very strong sequential correlativity, and the most of situation of the next internal storage location that CPU will visit is near the address of last once visit.
The Cache function mainly comprises correctly to be read and write, and this function is finished by hardware fully.General CPU is divided into two kinds to the visit of internal memory, and a kind of is to obtain next bar instruction (machine code), and another kind is to obtain data.Cache in CPU is divided into two-stage, in one-level Cache, is divided into instruction cache (Code Cache) and data cache (Data Cache) again, corresponds respectively to above-mentioned two kinds of needs.When in one-level Cache, obtaining desired content, (be not called and hit), can in second-level cache, seek.Second-level cache is not distinguished instruction (Code) and data (Data) usually, as still miss, then really seeks in internal memory.For virtual memory system, also might finally in disk, seek.
CPU generally will be through hardware based Cache test when dispatching from the factory, but in order to guarantee that CPU is assembled in the computing machine, and on computers behind the installing operating system, its Cache still can operate as normal, just need utilize software that Cache is tested in the environment of complete machine.Because the work of Cache is based on hardware mode, so just can only adopt indirect method when utilizing software that it is tested.Wherein, instruction cache is a high-speed cache of depositing the operation part of executable program specially, usually under operating system, the method that it is tested is to utilize assembly routine to write a series of special functions, be compiled in the executable program, whether change the value of certain register repeatedly, be that anticipation is worth to judge whether the Cache function is normal, the effect that Cache played when the verification content comprised the read and write internal memory by this value of verification at last.
Yet, the method of testing to instruction cache of prior art has fairly obvious defective, at first, the code size of the machine code that assembly routine generates is not directly controlled, and the Cache of different CPU phasing not of uniform size together, the Cache of the different sizes of test need use the code of different sizes, at this situation, classic method can only be write several different static function, generate different big or small machine code collection, but this method of testing obviously can not satisfy the Cache of continuous upgrading, and the test instruction high-speed cache requires the size of code of machine code can dynamic change and control when operation; Secondly, under most of operating system, the above operating system of Windows95 for example, concurrent mechanisms such as multi-process and multithreading are arranged, and the virtual memory mechanism of utilizing the magnetic disk memory Extended RAM, like this, can move a plurality of programs simultaneously under the system, the program that CPU meeting time-division operation is moving, as CPU during from a process switch to another process, content in its instruction cache can be refreshed, however since this refresh uncontrolled, so test procedure can not be controlled fully to the code of the current operation of system.
Variable and the in check instruction cache method of testing of the size of code of machine addresses the above problem when at this moment, just needing a kind of the test.
Summary of the invention
In view of this, technical matters to be solved by this invention is the method for testing that proposes a kind of instruction cache, and the size of code of machine code is variable and controlled when making test, thereby makes test result more reliable.
To achieve these goals, the present invention proposes a kind of method of testing of instruction cache, this method comprises the steps: at first to distribute one section memory headroom for test, in this memory headroom, write executable machine code then, again this executable machine code is used as trial function and carries out test, next, verify the execution result of this trial function, discharge this section memory headroom at last.
Compare with existing method, method provided by the invention generates trial function by directly write executable machine code in internal memory, the size of code of machine code is variable and controlled when making test, avoided the deviation of the test result that may cause because the hardware environment of test is different, solved also simultaneously that test machine sign indicating number size of code can not change flexibly and the uncontrolled problem of test process, thereby can better simulate actual operating condition, improve the efficient and the quality of test.
Relevant detailed content of the present invention and method, existing conjunction with figs. and embodiment are described as follows.
Description of drawings
Fig. 1 is the overview flow chart of the method for testing of instruction cache of the present invention;
Fig. 2 is the process flow diagram that writes executable machine code in this memory headroom proposed by the invention;
Fig. 3 proposed by the invention is used as the process flow diagram that trial function is carried out test to this executable machine code;
Fig. 4 is the process flow diagram of this section of release memory headroom proposed by the invention;
Fig. 5 is that the run time version under prior art of example proposed by the invention is from the process flow diagram of revising (CodeSelf-Modifying) test; And
Fig. 6 is that the use of example proposed by the invention method of the present invention is carried out from the process flow diagram of revising (SelfModifying) test.
Wherein, description of reference numerals is as follows:
Step 110 is distributed one section memory headroom for test
Step 120 writes executable machine code in this memory headroom
The execution result of this trial function of step 140 checking
Step 150 discharges this section memory headroom
The on-the-spot machine code of step 240 write recovery
If step 410 test is not finished as yet, then be returned as the step that test distributes one section memory headroom, continue to carry out other trial function
If step 420 test is all finished, then finish test
Step 610 is distributed one section memory headroom for test
Step 620 writes the code (machine code) of Code Self-Modifying test in internal memory
Step 630 is carried out the test procedure of Code Self-Modifying
The execution result of step 640 validation test
Step 650 discharges this section memory headroom
Embodiment
The present invention is described in detail below in conjunction with accompanying drawing:
Illustrate that by Fig. 1 this figure is the overview flow chart of the method for testing of instruction cache of the present invention, is described as follows:
At first, test in this memory headroom, writes executable machine code (step 120) then for distributing one section memory headroom (step 110); Again this executable machine code is used as trial function and carries out test (step 130) next, verify the execution result (step 140) of this trial function; Discharge this section memory headroom (step 150) at last.
Method of testing provided by the present invention, the size of code of machine is variable and controlled when making test by directly write mechanism that executable machine code generates trial function in internal memory.This trial function is a kinematic function, and it can when carrying out test, at first distribute one section memory headroom for test in storehouse (Heap) on the operating system basis; The one section executable machine code of writing direct then, this machine code meets the standard of function, wherein contain the pop down instruction and return (ret) instruction, be used to carry out the machine code of corresponding function test, for example this machine code can perhaps be the functional test code of other instruction cache for the machine code code of code from modification test (Code Self-Modifying); At last this machine code is used as trial function and carries out test.
Wherein, when writing machine code in internal memory, pairing trial function pattern can change according to the demand of test, comprises two kinds of fixed mode and random patterns: will generate fixed size test machine sign indicating number under fixed mode; Change big or small test machine sign indicating number arbitrarily and under random pattern, will generate.Simultaneously, the register that will rewrite of trial function also can be formulated according to demand and be identical or different registers.
After test finishes, need verify it is whether correct by the content in the check register, thereby determine whether Cache is working properly test result.
Below, further specify flow process of the present invention.
See also Fig. 2, this figure is the process flow diagram that writes executable machine code in this memory headroom proposed by the invention, is described as follows:
At first write protection scene and initialization of register machine code (step 210); Repeat to write trial function Principal machine sign indicating number (step 220) then; Write again and deposit register value in the stack machine code (step 230); The on-the-spot machine code (step 240) of write recovery; Write link order (step 250) at last.
In the initialization machine code of this trial function, contain the pop down instruction, it is used for keeping the scene intact, with content pop down in the current register.
The number of times that repeats to write the test machine sign indicating number in memory headroom is with relevant to the requirement of test machine code length, and when requiring this machine code longer, the number of times that writes and carry out is corresponding more, otherwise then number of times is less.If when this test machine sign indicating number was the code of regular length, then this number of times was certain.
Wherein, the action that step 220 is described to repeat to write machine code is meant and repeats to write function body, promptly repeatedly repeats to write identical Principal machine sign indicating number, controls the length of the corresponding machine code of whole function with writing indegree.Under the random writing pattern, produce a random number, it is distributed a memory headroom that adapts with its size, according to the size of this memory headroom, determine to write the number of times of machine code, can fill up this memory headroom until the machine code that writes; In like manner, can also be to increase progressively or fixed mode.But, then only need write once for function header and function tail.
Afterwards, write one section the register value of function after complete be retained in machine code in the stack,, verify again so that in the future they are deposited in the specified memory.
At last, write one section register reverted to the machine code and the link order of the numerical value before this trial function is carried out, thereby recover on-the-spot, withdraw from function.
See also Fig. 3, this figure proposed by the invention is used as the process flow diagram that trial function is carried out test to this executable machine code, is described as follows:
At first with the memory address pop down (step 310) of appointment; Carry out the execution (step 320) that the machine code that writes is finished trial function then; At last register value is popped, deposit in the specified memory (step 330).
See also Fig. 4, this figure is the execution in step process flow diagram behind this section of release memory headroom proposed by the invention, is described as follows:
If test is not finished as yet, then be returned as the step that test distributes one section memory headroom, continue to carry out the step (step 410) of other trial function; If test is all finished, then finish the step of test
(step 420).
After one section test was finished, trial function will confirm test case, when all tests all tested finish after, will finish this test; Otherwise will proceed test, till test is all finished again for the test of not carrying out as yet distributes one section memory headroom.
With a kind of preferable example flow process of the present invention is described below.
Method to the instruction cache test has code reset test (Code ReplacementTest) usually, and code is from revising test (Code Self-Modifying Test) and code monitoring test methods such as (CodeSnoop Test).As embodiment process of the present invention is described from revising test (Code Self-Modifying Test) with code below.
See also Fig. 5, this figure be the run time version under prior art of example proposed by the invention from the process flow diagram of revising test (Code Self-Modifying), be described as follows:
Under prior art, the conventional test methodologies flow process is to carry out different codes from revising test procedure, these programs are the execution bodies that vary in size of using foreign currency in advance and writing and compiling, can not change size according to the test case of reality, generate the execution body that varies in size in real time, its implementation is as follows: run time version is from the test procedure 1 (step 510) of revising test; Run time version is from the test procedure 2 (step 520) of revising test; Run time version is from the test procedure 3 (step 530) of revising test.Till the test procedure of oneself modification test of all codes is finished.
Simultaneously, code is more approaching from test procedure and the procedure subject of revising test, and during program run, program only needs to jump to from main body to move in this function and gets final product, the two address in internal memory might be very near, thereby the content in the instruction cache may not refresh.
See also Fig. 6, this figure is that example proposed by the invention uses method run time version of the present invention from the process flow diagram of revising test, is described as follows:
Method provided by the present invention, its implementation is as follows:
At first distribute one section memory headroom (step 610) for test; In internal memory, write the Code code then from the code (machine code) (step 620) of revising test (Self-Modifying); Run time version is from the test procedure (step 630) of revising test (Code Self-Modifying) again; Next, the execution result (step 640) of validation test; Discharge this section memory headroom (step 650) at last.
Wherein, write and run time version also comprises the steps: at first to write the initialized machine code of function from the test procedure of revising test (Code Self-Modifying), as instructions such as pop downs; Repeat write activity then, all write from the machine code of revising test (Self-Modifying Code) until code, it is write indegree and decides according to desired code length; Write again register value is deposited in the machine code in the stack and recovers machine code on-the-spot and that return; Carry out trial function again, after returning register value being popped deposits in the specified memory; Carry out other processing such as verification at last.
Code is a kind of special function from revising test code (Self-Modifying Code), and code will be changed code itself during execution, and for example, its code is as follows:
Add edx, 0Ch obtains
*The address of instruction
And dword ptr[edx], ebx changes
*Instruction subtracts 1 certainly and becomes from adding 1
The nop blank operation
*Dec eax register eax is from subtracting 1
The nop blank operation
Shown in above-mentioned code, second code will be changed the 4th, and original eax register is changed into from adding 1 from subtracting 1.This process is by first addition instruction (add) the 4th instruction (to be with
*Number statement) the address put the edx register, and instruction (and) by second content that this address is pointed to and the content in the ebx register are carried out and computing then, like this, just changed the content of the 4th instruction, in the present embodiment, be that former the 4th instruction (dec eax) that subtracts certainly is revised as from adding 1 instruction (inc eax); Whether the content by verification eax register is correct at last, determines whether the Cache function is normal.Above-mentioned code will constantly repeat, and it is carried out test and is determined by code length.
When needs are realized test to Cache function different aspect, can use other code instead and replace code from revising test code (Self-Modifying Code), same, can control overall code length by the control number of occurrence.
When test procedure moves, storage allocation at first, in the storehouse of system, distribute, want the machine code carried out to wherein writing again, program jumps in the storehouse (Heap) and carries out then, get back to redirect place after being finished and carry out the instruction of back, carry out this module once more, perhaps discharge internal memory and the termination routine that is distributed.So each redirect meeting is to different core positions, and the content in the instruction cache can be refreshed, thus more effective the test.
The above is preferred embodiment of the present invention only, is not to be used for limiting practical range of the present invention; All equalizations of being done according to instructions of the present invention and accompanying drawing content change and modify, and all are included in the claim of the present invention.
Claims (11)
1, a kind of method of testing of instruction cache is characterized in that, this method may further comprise the steps at least:
For test distributes one section memory headroom;
In this memory headroom, write executable machine code;
This executable machine code is used as trial function carries out test;
Verify the execution result of this trial function; And
Discharge this section memory headroom.
2, the method for testing of instruction cache as claimed in claim 1 is characterized in that, is to distribute one section memory headroom for this test in the storehouse of system for test distributes one section memory headroom.
3, the method for testing of instruction cache as claimed in claim 1 is characterized in that, this executable machine code is the standard that meets function, can carry out the machine code of corresponding function test.
4, the method for testing of instruction cache as claimed in claim 1 is characterized in that, the step that writes executable machine code in this memory headroom is further comprising the steps of:
Write protection scene and initialization of register machine code;
Repeat to write trial function Principal machine sign indicating number;
Write and deposit register value in the stack machine code;
The on-the-spot machine code of write recovery; And
Write link order.
5, the method for testing of instruction cache as claimed in claim 4 is characterized in that, contains the pop down instruction in this initialization machine code.
6, the method for testing of instruction cache as claimed in claim 4 is characterized in that, repeats to write trial function Principal machine sign indicating number and is length according to required test machine sign indicating number and decide and repeat the number of times that writes and carry out.
7, the method for testing of instruction cache as claimed in claim 4 is characterized in that, writing link order is the step of returning the execution result of carrying out this trial function of checking.
8, the method for testing of instruction cache as claimed in claim 1 is characterized in that, this executable machine code is used as trial function carries out the step of test and more may further comprise the steps:
Memory address pop down with appointment;
Carry out this section machine code and finish the execution of trial function; And
Register value is popped, deposit in the specified memory.
9, the method for testing of instruction cache as claimed in claim 1 is characterized in that, the execution result of verifying this trial function is a working condition of determining high-speed cache by the content in the checking register.
10, the method for testing of instruction cache as claimed in claim 1, it is characterized in that, discharge and also comprise after the step of this section memory headroom, then be returned as the step that test distributes one section memory headroom, continue to carry out the step of other trial function if test as yet and do not finish.
11, the method for testing of instruction cache as claimed in claim 1 is characterized in that, discharges also to comprise after the step of this section memory headroom if test all and finish, and then finishes the step of test.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03148716 CN1567212A (en) | 2003-06-24 | 2003-06-24 | Testing method for instruction cache |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03148716 CN1567212A (en) | 2003-06-24 | 2003-06-24 | Testing method for instruction cache |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1567212A true CN1567212A (en) | 2005-01-19 |
Family
ID=34472357
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 03148716 Pending CN1567212A (en) | 2003-06-24 | 2003-06-24 | Testing method for instruction cache |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1567212A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102147757B (en) * | 2010-02-08 | 2013-07-31 | 安凯(广州)微电子技术有限公司 | Test device and method |
-
2003
- 2003-06-24 CN CN 03148716 patent/CN1567212A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102147757B (en) * | 2010-02-08 | 2013-07-31 | 安凯(广州)微电子技术有限公司 | Test device and method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1299201C (en) | Methods and apparatus for improving throughput of cache-based embedded processors by switching tasks in response to a cache miss | |
| Kamil et al. | Impact of modern memory subsystems on cache optimizations for stencil computations | |
| CN1171147C (en) | Automatic continued software/adaptor generator | |
| CN100492295C (en) | Method and device for re-ordering instructions using pointers | |
| CN101063979A (en) | MPU FPGA verification device supporting stochastic instruction testing | |
| CN101558390B (en) | Configurable cache for a microprocessor | |
| CN103092810A (en) | Processor with programmable virtual ports | |
| CN1862495A (en) | Method and apparatus for maintaining context while executing translated instructions | |
| CN1313957C (en) | Hardware-assisted disign verification system using a packet-based protocol logic synthesized for efficient data loading and unloading | |
| Lee et al. | ActiveSort: Efficient external sorting using active SSDs in the MapReduce framework | |
| CN102270158A (en) | Application program multiprocess running method and device | |
| CN105739992B (en) | The method and system of software control memory partition and mapping based on GCC compiler | |
| CN1975693A (en) | Command simulation analytic system with automatic driving function and realizing method thereof | |
| Haque et al. | Dew: A fast level 1 cache simulation approach for embedded processors with fifo replacement policy | |
| CN1945531A (en) | Design method of inter-operation system | |
| Huo et al. | Porting irregular reductions on heterogeneous CPU-GPU configurations | |
| Lu et al. | Will supercomputers be super-data and super-AI machines? | |
| CN109656868B (en) | Memory data transfer method between CPU and GPU | |
| CN105335656A (en) | Software security enhancing method based on binary rewrite and dynamic randomization | |
| CN1295778C (en) | Method for verifying consistency of chip hardware behavior and software simulation behavior | |
| CN1567212A (en) | Testing method for instruction cache | |
| US20070179772A1 (en) | Method and apparatus for increasing the efficiency of an emulation engine | |
| CN106569961A (en) | Access address continuity-based cache module and access method thereof | |
| CN1244059C (en) | Method for retrieving a reset vector after a reset | |
| CN114416031B (en) | Operating system for supporting RISC-V processor facing AIoT scene |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |