CN1555558A - Apparatus and method for a memory storage cell leakage cancellation scheme - Google Patents
Apparatus and method for a memory storage cell leakage cancellation scheme Download PDFInfo
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- CN1555558A CN1555558A CNA028107055A CN02810705A CN1555558A CN 1555558 A CN1555558 A CN 1555558A CN A028107055 A CNA028107055 A CN A028107055A CN 02810705 A CN02810705 A CN 02810705A CN 1555558 A CN1555558 A CN 1555558A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
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Abstract
An apparatus is described having a plurality of storage cells coupled between a first bit line and a second bit line. The apparatus also has a first transistor that pre-charges the first bit line and provides a first supply of current for one or more leakage currents drawn from the first bit line by any of the plurality of storage cells. The apparatus also has a second transistor that pre-charges the second bit line and provides a second supply of current for one or more leakage currents drawn from the second bit line by any of the plurality of storage cells.
Description
Invention field
The present invention relates generally to semiconductor memory technologies; More specifically, relate to equipment and the method that is used for memory storage cell leakage cancellation scheme.
Background
Fig. 1 shows prior art random-access memory (ram) unit 100.The prior art ram cell 100 of Fig. 1 comprises a plurality of " N " storage unit S
1To S
N(each is corresponding to static RAM (SRAM) (SRAM) unit).Storage unit S
1To S
NEach storage unit store a Bit data.Data are (for example, to be used for storage unit S by the corresponding word line (WL) that drives it
1WL
1, be used for the WL of storage unit S2
2, or the like) and be read out from specific storage unit.Read run duration at typical storage unit, bit line 101,102 is pre-charged to " height " voltage.
The word line of the storage unit that is read out (for example, is used for storage unit S
1Word line WL
1) be driven (for example, with " height " voltage), and the word line that is used for remaining " unread " storage unit (for example, distributes and is used for storage unit S
1To S
NWord line WL
1To WL
N) be turned off (for example, with " low " voltage).(for example, be used for storage unit S at the word line that drives the storage unit that will be read out
1Word line WL
1) after, the storage unit that be read out is driven into " low " voltage to a bit lines.
For example, if at storage unit S
1In the data of storage corresponding to " 1 ", storage unit S then
1Bit line 102 is driven into " low " voltage, and bit line 101 remains on pre-charge " height " voltage.On the contrary, if at storage unit S
1In the data of storage corresponding to " 0 ", storage unit S then
1Bit line 101 is driven into " low " voltage, and bit line 102 remains on pre-charge " height " voltage.Fig. 1 shows example (that is storage unit S, of a kind of situation in back
1Store one " 0 ") because drive current Isc is observed to by storage unit S
1Driven from bit line 101.
Because at the voltage on bit line 101,102 between the storage unit reading duration is different (that is, a voltage is high, and another voltage is low), we can say, on bit line 101,102, there is differential voltage.The differential voltage that provides on bit line 101,102 can be represented as:
Signal=V1-V2 (1)
Wherein V1 is the voltage on bit line 101, and V2 is the voltage on bit line 102.High and the low voltage that should be pointed out that the reality on bit line can change with different embodiment.And, should be pointed out that the difference between V1 and the V2 is big more, then observed differential voltage is big more on bit line 101,102.
Storage unit leaks and can cause in the generation time quantum that differential voltage spent increase on bit line 101,102 between the bit cell reading duration.Like this, the travelling speed of ram cell 100 can be subjected to the injurious effects that storage unit leaks.Under the situation that does not have storage unit to leak, the speed of setting up differential voltage during the storage unit readout can be represented as:
Dv/Dt＝Isc/(Cb+2Cc) (2)
Wherein: (1) Cb is by the electric capacity of drop-down bit line; (2) Cc is the electric capacity between the bit line 101,102; And (3) Isc is the amount of drive current of being pulled out by the storage unit that is being read out.
From formula (2), can see that along with Isc increases, the speed that differential voltage is established increases.Storage unit leaks has the effect that reduces the Isc item in the formula (2), like this, reduces the speed that differential voltage is established.It is the storage unit that is not read out is pulled out electric current from bit line trend that storage unit leaks.When the number of " not reading " unit increased, the influence of the speed of setting up for differential voltage worsened.
Example ground shows worse case condition on Fig. 1.Particularly, at the storage unit S that pulls out electric current I sc from low bit line 101
1Between reading duration, each remaining N-1 storage unit (is storage unit S
2To S
N) pull out electric current I from high bit line 102
LEach leakage current I from high bit line 102
LTo cause the voltage drop on high bit line 102.Like this, from N-1 leakage current I of high bit line 102
L(as seeing on Fig. 1) is corresponding to the voltage drop of situation the worst on high bit line 102.
From the differential voltage of between pair of bit lines 101 and 102, setting up, when high bit line 102 voltages because N-1 leakage current I
LAnd when descending, the effect that reduces low bit line 101 by drive current Isc reduces.This reduces corresponding to differential signal voltage, and it reduces corresponding to the speed of setting up differential signal voltage.
Just, for the worst situation shown in Figure 1, when having storage unit to leak, the speed of setting up differential voltage during the storage unit readout can be represented as:
Dv/Dt＝(Isc-(N-1)I
L)/(Cb+2Cc) (3)
Wherein: (1) Cb is by the electric capacity of drop-down bit line; (2) Cc is the electric capacity between the bit line 101,102; (3) Isc is the amount of drive current of being pulled out by the storage unit that is being read out; And (4) (N-1) I
LIt is the total amount of the leakage current that is drawn out from high bit line 102.As what can see from formula (3), leakage current item (N-1) I
LFrom drive current item Isc, deducted.The decline of the speed that this is established corresponding to differential voltage.As what discuss, this is corresponding to the decline of the speed of ram cell 100.
The accompanying drawing summary
The present invention describes by the example on the figure of accompanying drawing (but not restriction), and identical label is represented identical unit on the figure, wherein
Fig. 1 shows the prior art ram cell.
Fig. 2 shows the embodiment of improved ram cell.
Fig. 3 is presented in the improved ram cell of Fig. 2 and can be used for from the embodiment of the control line signaling of storage unit sense data.
Fig. 4 shows another embodiment of improved ram cell.
Describe in detail
The elimination electric current is provided on bit line, eliminate effectively above in background one joint differential signal quality that describe, that reduce.Embodiment 200 leakage current, improved ram cell is offset in Fig. 2 demonstration effectively.Fig. 3 is presented in the improved ram cell of Fig. 2 and can be used for from the embodiment of the control line signaling of storage unit sense data.
With reference to Fig. 2 and 3, the reading operation and can be looked at as by the stage and take place of storage unit.Balanced and pre-charge bit line 201,202 of phase one (for example, between the time T 0 and T1 of Fig. 3).Subordinate phase (for example, between the time T 1 and T2 of Fig. 3) is leaked supplemental current I by providing individually on each bit line 201,202
L1, I
L2, and approximate influence of offsetting any leakage current that on bit line 201,202, may exist.Phase III (for example, between the time T 2 and T3 of Fig. 3) keeps leaking supplemental current I
L1, I
L2, and while bit line 201,202 is once more by equilibrium.Quadravalence section (for example, between the time T 3 and T4 of Fig. 3) is from the storage unit sense data.
Balanced and pre-charge bit line 201,202 of phase one (for example, between the time T 0 and T1 of Fig. 3).Bit line the 201, the 202nd, by transistor Q5 conducting by balanced.Transistor Q5 is switched on by equilibrium line 203,303 is driven into electronegative potential.Transistor Q5 conducting causes the short circuit between the bit line 201,202 effectively, makes bit line 201,202 have approximately equalised voltage.This action can be called as balanced bit line 201,202.
Balanced bit line 201,202 helps the ram cell 200 " zero clearing " effectively former storage unit read.For example, if storage unit on Fig. 3 from being read out to time T0 in the past, then bit line 201,202 can remain on the differential voltage when reading.Just, a bit line can be to be in low-voltage, and another bit line can be to be in high voltage.Drive equilibrium line 203 to electronegative potential, make bit line 201,202 reach common voltage.
When sense line 204,304 was driven to electronegative potential, bit line 201,202 was also by pre-charge.In the embodiment of Fig. 2, pre-charge bit line 201,202 is equivalent to bit line 201,202 is become high voltage.Subsequently, from (for example between the time T 3 and T4 at Fig. 4) between the storage unit reading duration, from the storage unit of wherein reading one bit lines of pre-charge is moved to low-voltage.
In the embodiment of Fig. 2, bit line the 201, the 202nd, by transistor Q1 and Q2 conducting and by pre-charge.Transistor Q1 and Q2 in the embodiment of Fig. 2, are switched on by sense line 203,304 is driven into electronegative potential.Should be pointed out that in the embodiment of Fig. 2 the grid of each transistor Q1 and Q2 and drain electrode can be by transistor " short circuits ".Just, grid and the drain electrode of the grid of transistor Q3 short-circuit transistor Q1 and drain electrode and transistor Q4 short-circuit transistor Q2.With grid and the drain short circuit of each transistor Q1 and Q2, make these transistors Q1, Q2 become effectively (active) load.
Just, sense line 204,304 is driven into electronegative potential, makes transistor Q3 and Q4 conducting, they make respectively that again transistor Q1 and Q2 become service load.The source electrode of service load is to drain voltage V
SDCan be approximately:
V
SD＝V
SG＝V
T+(I
SD/B)
0.5 (4)
Wherein: (1) V
SGBe that source electrode is to grid voltage; (2) V
TIt is threshold voltage; (3) I
SDBe that source electrode is to drain current; And (4) B is mutual conductance.For little source electrode to drain current I
SD, should be noted that source electrode is to drain voltage V
SDApproach V
TLike this, in the embodiment of Fig. 2, the voltage of the pre-charge on bit line 201,202 can be typically corresponding near V
CC-V
TVoltage.Fig. 3 shows the bit-line levels for pre-charge voltage 301, example on the bit line 201 of Fig. 2.
In the embodiment that replaces (in order to quicken bit line by the speed of pre-charge), during the phase one between time T 0 and the T1, the grid voltage of Q1 and Q2 can be driven into electronegative potential forcibly, and transistor Q3 and Q4 keep turn-offing.For example, between time T 0 and T1, sensing voltage can be set at high voltage (it turn-offs transistor Q3 and Q4), and the grid voltage of transistor Q1 and Q2 can be grounded.
This transistor Q1 and Q2 are arranged on " high electric current " output state, and this allows their to drive the electric capacity relevant with bit line 201,202.This allows the voltage of bit line 201,202 to reach the voltage of their pre-charge more quickly compared with pure running load.Like this, with reference to Fig. 3, the voltage 304 of sense line 204 can be in one embodiment: (1) is in high logic level between time T 0 and T1; (2) be switched to low logic level in time T 1.
Equilibrium between time T 0 and T1 also can be eliminated, because needn't be based upon the voltage of the pre-charge that equates on the bit line 201,202 between time T 0 and T1.Just, the action of pre-charge bit line 201,202 effectively " removing " they, their up-to-date storage unit read messages are disposed.In the embodiment of another replacement, transistor Q3 and Q4 can replace with transmission gate, to protect low bit line 201,202 voltages.Transmission gate is the transistorized Parallel coupled of nmos pass transistor and PMOS, and like this, when one " connection ", two all is " connection ", and when being " shutoff " for one, two all is " shutoff ".
During subordinate phase (for example, between the time T 1 and T2 of Fig. 3), leak supplemental current I by on each bit line 201,202, providing individually in the influence of any leakage current that may exist on the bit line 201,202
L1, I
L2And approximate being cancelled.This is to finish by the equilibrium of cancelling between bit line 201,202.In the embodiment of Fig. 2, the equilibrium of cancelling between bit line 201,202 is finished by turn-offing transistor Q5, turn-offs transistor Q5 and finishes by equilibrium line 203,303 is driven into high level again.
By cancelling equilibrium, bit line 201,202 is kept apart mutually.Like this, transistor Q1 and Q2 replenish the leakage current that may exist on their bit lines 201,202 separately individually.Just, transistor Q1 provides electric current I
L1It replenishes any leakage current I that flows out from bit line 201
L1(such as leakage current I
La).Transistor Q2 provide electric current I
L2, it replenishes any leakage current I that flows out from bit line 202
L2(such as leakage current I
Lb).
If the storage unit of the X in ram cell 200 leaks from bit line 201, and the storage unit of the Y in ram cell 200 leaks from bit line 202, then (supposes for each leakage of storage unit leakage current I corresponding to same amount for simplicity,
L) I
L1=XI
LAnd I
L2=YI
LAs what discuss in more detail below, on each bit line 201,202, replenish leakage current individually, offset them approx for influence at the differential signal of between bit line 201,202, setting up between the storage unit reading duration.
Should be noted that from formula 4, if I
L1Be not equal to I
L2, the source electrode of transistor Q1 and Q2 is exactly different to grid voltage.Suppose if I
L1Be not equal to I
L2, the source electrode of transistor Q1 and Q2 may be different to grid voltage, should be noted that (it seems from formula 4 once more) result, the voltage on the bit line 201,202 can be different.Just, when being made, effective load has V
SG=V
SDThe time, source electrode arrives the difference of drain voltage corresponding to source electrode to the difference of grid voltage.This will cause the different voltage between pair of bit lines 201,202.
During the phase III (for example, between the time T 2 and T3 of Fig. 3), bit line 201,202 is by balanced, and leakage supplemental current I
L1, I
L2Be held.For the difference of the voltage between equilibrium (it is to finish by the voltage on the equilibrium line 203,303 is reduced to low-voltage in the embodiment of Fig. 2 and 3) " fixing " pair of bit lines 201,202 of ram cell 200, this voltage difference is (as above firm description) that produces owing to the corresponding leakage current that replenishes them individually.
Like this, if voltage difference produces on bit line 201,202, then equilibrium will force bit line 201,202 voltages to be approximately equal.Leak supplemental current I
L1, I
L2Also be held by turn-offing transistor Q3 and Q4 (this finishes by sense line 204,304 is risen to high voltage in the embodiment of Fig. 2 and 3).Shutoff transistor Q3 and Q4 remove the short circuit that exists between the grid of transistor Q1 and Q2 and source electrode.
Yet,, leak supplemental current I owing to have capacitor C1 and C2
L1, I
L2(they flow through transistor Q1 and Q2 respectively) remains unchanged basically.Like this, leak supplemental current and can be called as " maintained ".Recall, the difference of bit line 201,202 voltages is owing to replenish leakage current (as shown in Figure 3, between T1 and T2) and generation individually for each bit line.As what discuss, the result, the grid voltage of Q1 and Q2 can be different.
Generating leakage supplemental current I
L1, I
L2During (as shown in Figure 3, between T1 and T2), will distinguish " rising on the slope " to the voltage on their bit lines separately (because of the short circuit of setting up) by transistor Q3 and Q4 at the voltage on capacitor C 1, the C2.Just, capacitor C 1 slope rises at voltage that keeps on the bit line 201 and capacitor C 2 slopes and rise to the voltage that keeps on bit line 202.Also have, when transistor Q3 and Q4 were switched on, this was and V for each transistor Q1 and Q2
SD=V
SGConsistent.
When transistor Q3 and Q4 are turned off (as shown in Figure 3, between time T 2 and T3), capacitor C 1, their voltage of C2 " maintenance ".Like this, leak supplemental current I
L1, I
L2Continue to be generated from transistor Q1 and Q2 respectively.This is corresponding to leaking supplemental current I
L1, I
L2" being held " like that as discussed above.When transistor Q5 is switched on (as shown in Figure 3, between time T 2 and T3), bit line 201,202 beginnings are by balanced.After reaching stable state, bit line 201,202 has approximately equalised voltage, and leaks supplemental current I
L1, I
L2Continue to be generated from transistor Q1 and Q2 respectively.
Quadravalence section (for example, as shown in Figure 3, between time T 3 and T4), from specific storage unit sense data.Like this, for from the storage unit sense data, the equilibrium of bit line 201,202 is terminated, so that allow to produce differential voltage on bit line.So, should be pointed out that Fig. 3 represents, the voltage 303 on equilibrium line 203 is caused, so that transistor Q5 is turned off.
In the exemplary embodiment of Fig. 2, storage unit S
1Be read out (for example, by driving 308 its corresponding word line WL
1), and it comprises the numerical information corresponding to " 0 ".Like this, storage unit S
1Pull out drive current from bit line 201, the voltage 301 on this bit line 201 of leaving behind.As the leakage supplemental current I of each leakage current by providing by transistor Q1 and Q2
L1, I
L2When being calculated, the differential voltage on bit line with " speed fully " the same generation apace that originally provided by formula 2.
Fig. 4 shows the embodiment of replacement, and it improves bit line 401,402 by the speed of pre-charge.The embodiment 400 of Fig. 4 is added to transistor Q6 and Q7 the embodiment 200 of Fig. 2.Transistor Q6 and Q7 further quicken, and can be used for the bitline precharge activity that further acceleration takes place in (and/or between time T 2 and T3 at Fig. 3) between the time T 0 and T1 of Fig. 3.When no matter when voltage 303 was reduced to low-voltage on the equilibrium line 403, transistor Q6 and Q7 were " connections ", and the electric capacity that this drives bit line 401,402 effectively causes the quick increase of the voltage of bit line 401,402.
Above-mentioned design and method can be at storage component parts, such as being utilized in the semiconductor memory chips.Semi-conductor chip can be implemented in the system such such as computing system or network system then.For example, storage component part can be coupled to: (1) general processor; Or (2) digital signal processor or traditional logical circuit (for example, special IC (ASIC)); Or (3) bus structure (for example, pci bus).In other were used, design discussed above and method can be used in the memory application of embedding.In the memory application that embeds, the zone of storer is structured in the bigger semi-conductor chip (for example, as " on the circuit board " ultra-high access memory or as the memory resource (SoC) in system on a chip).
The embodiment that should also be noted that this explanation singly can not be implemented in semi-conductor chip, also can be implemented in machine-readable medium.For example, design discussed above can be stored in or be embedded in the machine-readable medium relevant with the design tool that is used in designing semiconductor device.Example comprises with VHSIC hardware description language (VHDL), the net list (netlist) of Verilog language or SPICE language formatization.The example of some net list comprises: performance class net list, register transfer rank (RTL) net list, other net list of gate leve and transistor rank net list.Machine-readable medium also comprise the medium with layout information, such as the GDS-II file.And, be used for the net list file of semiconductor chip design or the readable medium of other machines can be used for carrying out above-mentioned instruction under simulated environment method.
Therefore, it is also understood that embodiments of the invention can be used as or be supported in the software program that the processing core of some form (such as the CPU of computing machine) go up to be carried out, or otherwise on machine-readable medium or in be implemented or be implemented.Machine-readable medium comprise any mechanism that is used for storage of the readable form of machine (for example, computing machine) or transmission information.For example, machine-readable medium comprise ROM (read-only memory) (ROM); Random-access memory (ram); The disk storage medium; The light storage medium; Flash memory device; The electricity of the signal of propagating, light, sound or other form (for example, carrier wave, infrared signal, digital signal or the like); Or the like.
In above technical descriptioon, the present invention describes with reference to specific exemplary embodiment.Yet, it will be appreciated that, under the prerequisite that does not deviate from spirit and scope widely that set forth in the claims, of the present invention, can make various corrections and change.Therefore, instructions and accompanying drawing are looked at as illustrative, rather than restrictive.
Claims (19)
1. equipment comprises:
(a) a plurality of storage units are coupling between first bit line and second bit line;
(b) the first transistor, described first bit line of pre-charge and for providing first supplemental current from one or more leakage currents that first bit line extracts by any described a plurality of storage units; And
(c) transistor seconds, described second bit line of pre-charge and for providing second supplemental current from one or more leakage currents that second bit line extracts by any described a plurality of storage units.
2. the equipment of claim 1, also comprise the equilibrium line that is coupled to described first and second bit lines, wherein first voltage on described equilibrium line makes described first and second bit lines reach identical voltage, and second voltage on described equilibrium line makes described first and second bit lines keep different voltage.
3. the equipment of claim 2, wherein said equilibrium line is coupled to described first and second bit lines by the 3rd transistor, described the 3rd transistor has the drain electrode that is coupled to a described bit line, is coupled to the source electrode of another described bit line, is coupled to the grid of described equilibrium line.
4. the equipment of claim 3, also comprise the 4th transistor, for the described pre-charge of described first bit line provides electric current, described the 4th transistor is coupled to described first bit line and described equilibrium line, described equipment also comprises the 5th transistor, for the described pre-charge of described second bit line provides electric current, described the 5th transistor is coupled to described second bit line and described equilibrium line.
5. the equipment of claim 1, wherein said equipment is corresponding to static RAM (SRAM) unit.
6. the equipment of claim 1, also comprise sense line, described sense line is coupled to described first and second transistors, wherein first voltage on described sense line causes the described pre-charge of described first and second bit lines, and makes described first and second supplemental current be held when described storage unit is read out at second voltage on the described sense line.
7. the equipment of claim 6, wherein said sense line is coupled to described the first transistor by the 3rd transistor, and be coupled to described transistor seconds by the 4th transistor, described the 3rd transistor has the first node that is coupled to described first bit line and is coupled to the Section Point of the grid of described the first transistor, described the 3rd transistor has the grid that is coupled to described sense line, described the 4th transistor has the first node that is coupled to described second bit line and is coupled to the Section Point of the grid of described transistor seconds, and described the 4th transistor has the grid that is coupled to described sense line.
8. the equipment of claim 1 also comprises first capacitor, is kept for the grid voltage of described the first transistor, so that described first supplemental current is held when described storage unit is read.
9. the equipment of claim 8 also comprises second capacitor, is kept for the grid voltage of described transistor seconds, so that described second supplemental current is held when described storage unit is read.
10. method comprises:
(a) use electric current pre-charge first bit line that provides by the first transistor;
(b) use electric current pre-charge second bit line that provides by transistor seconds;
(c) extract first from described the first transistor and leak supplemental current, to replenish the one or more leakage currents that extract from described first bit line by the one or more storage units that are coupled to described first bit line;
(d) extract second from described transistor seconds and leak supplemental current, to replenish the one or more leakage currents that extract from described second bit line by the one or more storage units that are coupled to described second bit line; And
(e) between described storage unit reading duration, keep described first and second to leak supplemental current.
11. the method for claim 10, wherein said pre-charge first bit line and described pre-charge second bit line take place simultaneously.
12. the method for claim 10, wherein said extraction first are leaked supplemental current and the described extraction second leakage supplemental current takes place simultaneously.
13. the method for claim 12, wherein said pre-charge first bit line and described pre-charge second bit line take place simultaneously.
14. the method for claim 10 also is included in described first and second bit lines of the described first and second bit line post-equalizations of described pre-charge, described equilibrium took place before described reading.
Remain on primary grid voltage on the described the first transistor 15. the method for claim 10, wherein said maintenance also comprise with first capacitor, and remain on second grid voltage on the described transistor seconds with second capacitor.
16. an equipment comprises:
Be coupled to the storer of processor, described storer also comprises:
(a) a plurality of storage units are coupling between first bit line and second bit line;
(b) the first transistor, described first bit line of pre-charge and for providing first supplemental current from one or more leakage currents that first bit line extracts by any described a plurality of storage units; And
(c) transistor seconds, described second bit line of pre-charge and for providing second supplemental current from one or more leakage currents that second bit line extracts by any described a plurality of storage units.
17. the equipment of claim 16, wherein said processor is a general processor.
18. the equipment of claim 16, wherein said processor is a digital signal processor.
19. the equipment of claim 16 also comprises the bus that is coupled to described storer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/823,575 | 2001-03-30 | ||
| US09/823,575 US6608786B2 (en) | 2001-03-30 | 2001-03-30 | Apparatus and method for a memory storage cell leakage cancellation scheme |
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| CN100419914C CN100419914C (en) | 2008-09-17 |
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| US (2) | US6608786B2 (en) |
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| JP3560266B2 (en) * | 1995-08-31 | 2004-09-02 | 株式会社ルネサステクノロジ | Semiconductor device and semiconductor data device |
| DE69626099T2 (en) * | 1996-03-29 | 2003-11-27 | St Microelectronics Srl | Sense amplifiers with gain modulation, in particular for memory arrangements |
| DE69631123D1 (en) * | 1996-06-18 | 2004-01-29 | St Microelectronics Srl | Method and circuit for reading non-volatile memory cells with a low supply voltage |
| JP3360717B2 (en) * | 1997-09-29 | 2002-12-24 | 日本電気株式会社 | Dynamic semiconductor memory device |
| US6075744A (en) * | 1997-10-10 | 2000-06-13 | Rambus Inc. | Dram core refresh with reduced spike current |
| US5959913A (en) * | 1998-02-19 | 1999-09-28 | Micron Technology, Inc. | Device and method for stress testing a semiconductor memory |
| JP3183245B2 (en) * | 1998-03-06 | 2001-07-09 | 日本電気株式会社 | Semiconductor storage device |
| US6049492A (en) * | 1998-06-29 | 2000-04-11 | Siemens Aktiengesellschaft | Interleaved sense amplifier with a single-sided precharge device |
| JP2001006370A (en) * | 1999-06-17 | 2001-01-12 | Nec Corp | Sram circuit |
| JP4024975B2 (en) * | 2000-01-07 | 2007-12-19 | 株式会社東芝 | Data transmission circuit |
| JP3326560B2 (en) * | 2000-03-21 | 2002-09-24 | 日本テキサス・インスツルメンツ株式会社 | Semiconductor memory device |
| KR100370164B1 (en) * | 2000-12-20 | 2003-01-30 | 주식회사 하이닉스반도체 | Pull-up Scheme Compensable Leakage Current in Bit Lines |
-
2001
- 2001-03-30 US US09/823,575 patent/US6608786B2/en not_active Expired - Lifetime
- 2001-12-28 TW TW90132778A patent/TW574707B/en not_active IP Right Cessation
-
2002
- 2002-02-11 WO PCT/US2002/021653 patent/WO2002095761A2/en not_active Application Discontinuation
- 2002-02-11 CN CNB028107055A patent/CN100419914C/en not_active Expired - Fee Related
-
2003
- 2003-06-13 US US10/461,293 patent/US6801465B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105810250A (en) * | 2014-12-29 | 2016-07-27 | 展讯通信（上海）有限公司 | Data reading method and apparatus |
| CN105810250B (en) * | 2014-12-29 | 2019-06-04 | 展讯通信（上海）有限公司 | A kind of method for reading data and device |
Also Published As
| Publication number | Publication date |
|---|---|
| TW574707B (en) | 2004-02-01 |
| WO2002095761A2 (en) | 2002-11-28 |
| US20020141265A1 (en) | 2002-10-03 |
| US6608786B2 (en) | 2003-08-19 |
| CN100419914C (en) | 2008-09-17 |
| WO2002095761A3 (en) | 2003-10-30 |
| US20030206468A1 (en) | 2003-11-06 |
| US6801465B2 (en) | 2004-10-05 |
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