CN1555169A - Multiple queue sequential buffer managing circuit and method based on pipeline - Google Patents
Multiple queue sequential buffer managing circuit and method based on pipeline Download PDFInfo
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Abstract
This invention discloses a multi-queue sequence buffer management circuit and a method based on a pipeline applying a pipeline structure including: an arbitration circuit selecting one for process from read, write and distribution buffer requests, a buffer slot state module designing state of the slot requiring operation and queue numbers and assigning idle slots, a buffer slot filter module filtering the slot, a buffer slot filter module filtering the slot states not belonging to the current operation queues nor idle aligned in terms of the head pointer, a queue slot selection module computing continuous idle slot numbers from the slot pointed by the head pointer and refreshing the head pointer and selecting preparing slots, a queue slot prior queuing module refreshing the read pointer and result numbers of the current operation queues with the pointer of the first prepare slots and their numbers which can support multi-queue to share one buffer space, queues can access the buffer in overlap.
Description
Technical field
The present invention relates to all kinds of chip designs in the field of network communication, relate in particular to cache management circuit and method thereof in the chip with pipeline organization.
Background technology
In the design of communication chip, the storage buffering is shared often, and this has just proposed to cushion the demand of many queue sequenceization management.So-called many queue sequenceization management is exactly that a plurality of formations are shared a buffer-stored space in the mode of sharing fully, and group mode of joining the team out of each queuing data is deferred to the principle of first in first out.
For example, in a kind of communication chip CHIP, its structure as shown in Figure 1.CHIP receives various instructions by host interface 11 from main frame, read as memory, the read and write access of control register, the look-up command of multiple algorithm etc., deposit instruction buffer 12 in, by the operation of instruction process unit 13 these orders of execution, after instruction is finished, the operating result of instruction leaves the result in and cushions in 14, is fetched by main frame.
Remove the instruction of read-write control register, other each class instructions form an independent formation in result's buffering.Because entering the instruction of CHIP is executed in parallel in CHIP, the operating result of instruction is made up of 8 32BIT words, so need be to the writing and read separately and independently control of this 9 class instruction execution result, guarantee that every class instruction results writes according to the CHIP processing sequence to read; And only have and all write in the buffering at operating result, just can read, after operating result is all read, this as a result notch just can be used; In addition, also the instruction that must guarantee to enter CHIP is after being finished, and result's buffering is had living space and stored the operating result of this instruction, so before instruction is operated, must be earlier its operating result memory allocated space in result's buffering.
Prior art, there is following problem in general buffering control assembly: can't distinguish different types of order; Can't distribute the corresponding results memory space for different instruction; Can't change all kinds of command result notches of management in proper order.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of many queue sequenceization cache management circuit based on streamline, support the different instruction formation to share result's buffering with complete sharing mode, all kinds of instruction queues can be carried out interleaving access to buffering, and writing of instruction results are read carry out the order management.
In order to solve the problems of the technologies described above, the invention provides a kind of many queue sequenceization cache management circuit based on streamline, adopt pipeline organization, comprise arbitration circuit, buffering notch state setting module, buffering notch filtering module, formation notch selection module and formation notch priority queue module, wherein:
Described arbitration circuit, receive and to read request as a result, write request as a result, the distributing buffer request and and the corresponding instruction queue of each request number, notch numbering, from request signal, choose one the tunnel and handle;
Described buffering notch state setting module is provided with the notch state and the queue number of solicit operation, buffering less than the time, be that the distributing buffer request distributes idle notch that tail pointer points to and the tail pointer that upgrades the buffering notch;
Described buffering notch filtering module, filtering do not belong to current operation queue and are not the notch states of Idle state, then the notch state that obtains are alignd according to the head pointer that cushions notch;
Described formation notch is selected module, in the notch state after alignment, calculates from described head pointer and points to continuous idle notch number that notch begins and upgrade described head pointer with this, and the notch that will be in the preparation attitude is simultaneously selected;
Described formation notch priority queue module, selection is pointed to first preparing slot that notch begins from described head pointer, and upgrade the read pointer of current operation queue with the pointer of this notch, add up the quantity of preparing slot simultaneously and upgrade the number of results of current operation queue.
Above-mentioned cache management circuit can have following characteristics: inserted some grades of registers in the built-up circuit of described buffering notch state setting module, buffering notch filtering module, formation notch selection module and formation notch priority queue module, be divided into four pipelining segments, synchronous working under the clock signal effect.
Above-mentioned cache management circuit can have following characteristics: select the built-up circuit of module and formation notch priority queue module to be divided into four pipelining segments, synchronous working under the clock signal effect by described buffering notch state setting module, buffering notch filtering module, formation notch.
Above-mentioned cache management circuit can have following characteristics: described formation notch selects module to comprise at least: the head pointer updating block, be used for the continuous idle notch number that will obtain and described head pointer in the adder addition, as the input of head pointer register in the described buffering notch state setting module; And the preparing slot selected cell, be used for preparing slot and other state notch are differentiated.
Above-mentioned cache management circuit can have following characteristics: described formation notch priority queue module comprises at least: the read pointer updating block, be used for calculating the sequence number of first preparing slot according to the output of described preparing slot selected cell, obtain the pointer of this notch with described head pointer addition, under the enable signal effect of current queue, upgrade the head pointer of current queue in the formation read pointer register; The number of results updating block is used for calculating according to the output of described preparing slot selected cell the quantity of preparing slot, and upgrades the number of results of current queue in the formation number of results register under the enable signal effect of current queue; And read selected cell, by linking to each other with the formation read pointer register, receive two multi-selection devices reading result queue's signal input and form with described formation number of results register.
Above-mentioned cache management circuit can have following characteristics: when there was multiple request at the same time in described arbitration circuit, the preferential selection read request as a result, secondly is to write request as a result, is the distributing buffer request at last.
The another technical problem that the present invention will solve provides a kind of many queue sequenceization amortization management method based on streamline, support the different instruction formation to share result's buffering with complete sharing mode, all kinds of instruction queues can be carried out interleaving access to buffering, and writing of instruction results are read carry out the order management.
In order to solve the problems of the technologies described above, the invention provides a kind of many queue sequenceization amortization management method based on streamline, may further comprise the steps:
(a) receive read request as a result, write request as a result, the distributing buffer request and and the corresponding instruction queue of each request number, notch numbering, from request signal, choose one the tunnel and handle;
(b) the notch state and the queue number of solicit operation are set, buffering less than the time, be that the distributing buffer request distributes idle notch that tail pointer points to and the tail pointer that upgrades the buffering notch;
(c) filtering does not belong to current operation queue and is not the notch state of Idle state, then the notch state that obtains is alignd according to the head pointer that cushions notch;
(d) in the notch state after alignment, calculate from described head pointer and point to continuous idle notch number that notch begins and upgrade described head pointer with this, the notch that will be in the preparation attitude is simultaneously selected;
(e) select to point to first preparing slot that notch begins, and upgrade the read pointer of current operation queue, add up the quantity of preparing slot simultaneously and upgrade the number of results of current operation queue with the pointer of this notch from described head pointer;
(f) when the number of results of this formation is non-vanishing, obtain effective slogan of groove as a result of one of foremost in this formation according to the read pointer of this formation, read the instruction results that mouth is read this notch by result's buffering;
Described step (b) is to the mode executed in parallel of step (e) with streamline.
Above-mentioned amortization management method can have following characteristics: in the described step (a), described distributing buffer request was submitted to before instruction is carried out by the CHIP processing unit, describedly write request as a result and submit to during for the last character in the write operation of this instruction results, the request as a result of reading is submitted to during for the last character in read operation.
Above-mentioned amortization management method can have following characteristics: in the described step (a), judge whether full standard is buffering: if described tail pointer and head pointer equate that then buffering is full, otherwise the end is full.
Above-mentioned amortization management method can have following characteristics: described streamline is the level Four streamline.
Above-mentioned amortization management method can have following characteristics: in the described step (f) same formation Different Results is read the spacing that will exist at least with streamline hop count same number of cycles.
Above-mentioned amortization management method can have following characteristics: when receiving a plurality of request at the same time, the preferential selection read request as a result, secondly is to write request as a result, is the distributing buffer request at last.
Above-mentioned amortization management method can have following characteristics: in the described step (c), by will not belonging to current operation queue and not being that the notch state of Idle state changes another into and " takies " attitude, finish the filtering function to the notch state.
As from the foregoing, cache management circuit of the present invention and method can support a plurality of formations to share a cushion space with complete sharing mode, for different instruction results distributes corresponding memory space fully, support individual queue that buffering is carried out interleaving access, do not have mutual obstruction between the formation.By to the orderly distribution of buffering with to the ordering of notch state, make writing of instruction results read the order that first-in first-out is followed in strictness.In addition, the design of streamline can improve the concurrency of buffer operation, makes circuit have more high efficiency.
Description of drawings
Fig. 1 is the bright structural representation of chip CHIP;
Fig. 2 is the schematic diagram of notch state transitions of the present invention;
Fig. 3 is the structured flowchart of embodiment of the invention cache management circuit;
Fig. 4 is the realization circuit diagram of embodiment of the invention cache management circuit;
Fig. 5 is the flow chart of embodiment of the invention amortization management method.
Embodiment
Below in conjunction with accompanying drawing specific embodiments of the invention are elaborated.
In the present embodiment, adopt the dual-port read-write on-chip SRAM of 64 bit wides to do buffer storage as a result, the degree of depth of this buffering is 64 double words.Be example with the chip among Fig. 1 still, the result space of every instruction is about 4 double words (a double word 64BIT), and result's buffering can be held 16 instruction results altogether, and we are called a notch with the memory space as a result of an instruction.The notch of each instruction constitutes an instruction results formation, and in CHIP, we need handle 9 instruction results formations, also can be according to the formation of concrete application extension to 16.Certainly when reality is used, might not there be the instruction results formation of all classes in the buffering simultaneously.
In the present embodiment, notch has three kinds of states, and the schematic diagram of its state transitions please refer to Fig. 2, when not having store instruction as a result in the notch, its state is an Idle state, and after should the free time notch when receiving the distributing buffer request distributing, the state of this notch becomes the use attitude; Receive this notch write as a result request signal after, this notch state is changed into the preparation attitude, promptly can read; Receive this notch read as a result request signal after, this notch state is changed into Idle state, again sub-distribution.In addition, in the process that the cache management circuit manages, also there is an occupied state in notch, will introduce in detail more in the following description.
The cache management circuit includes the sequencing circuit of 9 formations, and the responsible state information that produces each formation notch, its external interface signals, structured flowchart comprise arbitration circuit 21, buffering notch state setting module 22, buffering notch filtering module 23, formation notch selection module 24, formation notch priority queue module 25 as shown in Figure 3.Please be simultaneously with reference to the specific implementation circuit of Fig. 4, there is shown the main hardware unit of present embodiment, between each parts of cache management circuit with mode synchronous working under the clock signal effect of streamline, be divided into and be level Four flowing water, the circuit of wherein pipelining segment is divided into circuit No. 1～No. 4 with number designation respectively, wherein No. 1 circuit is used to finish the function that cushions notch state setting module 22, No. 2 circuit are used to finish the function of buffering notch filtering module 23, No. 3 circuit are used to finish the function that the formation notch is selected module 24, and No. 4 circuit are used to finish the function of formation notch priority queue module 25.Need to prove that circuit is not strict corresponding with above-mentioned module among the figure.
For the distributing buffer request, before being carried out by the CHIP processing unit, instruction submits to, provide the allocation result queue number simultaneously.By allocating in advance of notch, after the assurance instruction executed, the result can write in result's buffering.
For writing request as a result, to be written into pre-assigned notch by buffer write mouth as a result from the instruction results of CHIP processing unit, when the write operation of this instruction results is the last character, request signal is as a result write in submission, also comprised instruction queue number and the corresponding numbering of writing notch simultaneously.
For reading request as a result, main frame is read the instruction results that mouth is read this notch by buffering, when read operation is the last character, submits reading request signal to, comprises instruction queue number and the corresponding notch numbering of reading simultaneously.
Three request signals from the outside may be submitted to simultaneously, but any one constantly can only have a request processed, and in the present embodiment, the priority of reading request as a result is the highest, and the request as a result of writing is taken second place, and the buffering request for allocation is minimum.Arbitration circuit selects one tunnel request to send into first order flowing water according to the fixed priority order from three tunnel requests, and provides corresponding request confirmation signal.The priority of reading request as a result is decided to be the highest instruction results that can make from buffering, reads as early as possible, to improve the utilization ratio of buffering.
Buffering notch state setting module 22 is provided with the notch state and the queue number of solicit operation, buffering less than the time, be that the distributing buffer request distributes idle notch that tail pointer points to and the tail pointer that upgrades the buffering notch.
After receiving the distributing buffer request, if buffering full scale will indication buffering less than, then the idle notch that tail pointer is pointed to returns its numbering as distribution rebates, and tail pointer maker 31 upgrades the rear of queue pointer according to the distributing buffer confirmation signal, and the counting of tail pointer register 32 is added 1; (coherent signal is that this module is sent among the figure)
Present embodiment judges whether full standard is buffering: if tail pointer (pointing to Next Command result's storage notch) and head pointer equate that then buffering is full.This function is finished according to a buffering of the input generation full scale will of first head pointer register 34 and tail pointer register 32 by empty full scale will generation unit 33.Among the present invention, utilize the setting of head pointer tail pointer and the distribution principle of buffering, guaranteed that each formation result can realize first-in first-out, the requirement of operation in tandem when reading.
An example below in conjunction with each the notch state in the table 1 describes, among the figure, suppose 0～No. 15 and have two formation A, B in totally 16 notches, this handles No. 1 notch of front pointed, tail pointer points to No. 9 notches, suppose that arbitration circuit selected the request as a result of reading of notch 1 (A formation), the state of notch 1 will become the free time from preparation.The state variation of state representation in this processing procedure after "--〉".
Table 1
| ?15 | Queue number is to be allocated-free time |
| ?14 | Queue number is to be allocated-free time |
| ?13 | Queue number is to be allocated-free time |
| ?12 | Queue number is to be allocated-free time |
| ?11 | Queue number is to be allocated-free time |
| ?10 | Queue number is to be allocated-free time |
| ?9 | The B-free time--〉free time |
| ?8 | The B-free time--〉free time |
| ?7 | B-uses--〉takies |
| ?6 | A-uses |
| ?5 | B-uses--〉takies |
| ?4 | The A-preparation |
| ?3 | The B-preparation--〉take |
| ?2 | The A-preparation |
| ?1 | The A-preparation--〉free time |
| ?0 | The A-free time |
-tail pointer
-head pointer
Among Fig. 4,4BIT register 35 in No. 1 circuit is the current queue register, be used to store current queue A, the 16x4BIT register is a notch queue number register 36, be used to store the instruction queue number of each notch, the 16x2BIT register is a notch status register 37, is used to store the state of each notch, and three registers all output to 16 bit comparators 41 of next module.
Buffering notch filtering module 23, filtering does not belong to current operation queue and is not the notch state of Idle state, then the notch state that obtains is alignd according to the head pointer that cushions notch;
Among Fig. 4,16x comparator 41 in No. 2 circuit is according to the queue number of the selected notch of request, at first, the queue number of 16 notches and the queue number of the selected notch of current request are compared, the filtering notch does not belong to current queue and is not the notch state of Idle state, and the state of replacing this notch with seizure condition is as shift unit 42 inputs.His-and-hers watches 1, the notch of B formation were replaced by and take except that the free time, and the notch of A formation and unallocated formation then maintains the original state constant.
Then, shift unit 42 aligns the head pointer of the state of each notch input according to input, the notch state after the alignment is deposited in notch status register 43 after the processing of 16x2BIT.Before the displacement, the notch state is tactic by 0～No. 15 notch, for idle, idle, preparation ... Deng, after the displacement, under the situation of table 1, change into by 1,2 ...～, the order of 15, No. 0 notches arranges, changed into idle, preparation, preparation ... Deng.Output to the notch priority decoder and the queue priority decoder of No. 3 circuit then.
The formation notch is selected module 24, in the notch state after alignment, calculates continuous idle notch number that pointed notch from the beginning begins and upgrades described head pointer with this, and the notch that will be in the preparation attitude is simultaneously selected.
Among Fig. 4, the notch priority decoder 51 of No. 3 circuit is used from the continuous idle notch number that acquisition begins from head pointer with the highest and several 1 circuit 52 1 of notch priority that head pointer points to, as the input of first adder 53, with the addition of current notch head pointer, obtain new notch head pointer.In the table 1, continuous idle notch number is 1, during input summer 53 and the output addition of second head pointer register 44, the value of the new head pointer register that obtains should be pointed to notch 2, and this value will be imported into first head pointer register 34 in the circuit No. 1 at next beat.
If the state of No. 2 No. 3 notches is the free time in the table 1, then continuous idle notch number is 3, and head pointer should point to notch No. 4.If but the notch that this moment, head pointer pointed to is not idle notch, even 2, No. 3 notches all are idle notches, can not be released,
Formation notch priority queue module 25 is selected in this formation from head pointer first preparing slot backward, and upgrades the read pointer of current operation queue with the pointer of this notch, adds up the quantity of preparing slot simultaneously and upgrades the number of results of current operation queue.
Queue priority queue circuit 61 in No. 4 circuit is in the notch of 1 position representative from 16BIT preparation attitude mask register 55, select a top notch in the current queue in order, obtain the sequence number of this notch in current queue by decoder 63 then, in 64 li of second adders and the 56 output valve additions of the 3rd head pointer register, just obtained in the current queue pointer of previous preparing slot.With table 1 is example, the most previous handle in the preparation attitude notch be No. 2 notches, current serial number is 1 (counting from zero) because and the also renewal of the value of the 3rd head pointer register that adder is connected in No. 4 circuit, thereby the pointer that adder is exported will point to notch No. 2.Encoder 65 in No. 4 circuit receives the current queue that passes over one by one from No. 1 circuit 4BIT register number, generates the enable signal of writing of respective queue read pointer register.Thereby the read pointer of A formation in the 9x4BIT formation read pointer register 66 is updated to No. 2 notches of sensing.
Simultaneously, whether also have the result not read in order when main frame reads, to discern a certain class instruction queue, several 1 circuit 62 in No. 4 circuit calculate that 16BIT register intermediate value is the number of " 1 " in No. 3 circuit, and upgrade the number of results of this formation in the 9x4BIT formation number of results register 67 with the output of encoder.Table 1 situation, the number of results of A formation is updated to 2.
Main frame is according to reading result queue's signal, the information that has how many such instruction results in obtaining cushioning from formation number of results register 67 by second multi-selection device 72, when addressable number as a result in certain formation greater than zero the time, main frame obtains effective slogan of groove as a result of one of foremost in this instruction queue according to reading result queue's signal by first multi-selection device 71 from the formation read pointer register 66 of No. 4 circuit, read a mouthful instruction results of reading this notch by result's buffering.
In table 1, if arbitration circuit 21 handles is the request as a result of writing at No. 6 notches of A formation, the state of No. 6 notches can become the preparation attitude, then through after 4 grades of stream treatment, head, tail pointer is all constant, and the number of results of A formation adds 1, and the read pointer of A formation can not change yet.
Consider that above-mentioned realization component logic path is very long, present embodiment has inserted some grades of registers in circuit, and has formed and be divided into four sections streamline.In fact, in the present embodiment, read request and write request order will could be reflected in the result on formation number of results register and the formation read pointer register with 4 cycles, and the notch head pointer register is 3 cycles.Head pointer needs the loop of feedback in three request result of calculations, because the value of the head pointer that uses on the shift unit will upgrade according to the output of No. 3 circuit adders, and keeps consistent with the input head pointer value of two adders in 3, No. 4 circuit.The input head pointer value of these two adders is all transmitted by section on streamline by register.
In addition, because the memory read instruction will use the formation read pointer to begin transfer of data, and the result of this instruction wants four cycles just can be reflected in the register, reads the spacing that will keep four cycles at least so will arrange the Different Results of twice pair of same formation of main frame.Consider the result who reads generally all more than four words, and software can be a plurality of ports intersect and read, so this condition is content with very little.
By foregoing description, can obtain the flow process of the embodiment of the invention, as shown in Figure 5, may further comprise the steps:
Reception is read request as a result, is write request as a result, the distributing buffer request and and the corresponding instruction queue of each request number, notch numbering, from request signal, choose one the tunnel and handle; Step 100
The notch state and the queue number of solicit operation are set, buffering less than the time, be that the distributing buffer request distributes idle notch that tail pointer points to and the tail pointer that upgrades the buffering notch; Step 110
Filtering does not belong to current operation queue and is not the notch state of Idle state, then the notch state that obtains is alignd according to the head pointer that cushions notch; Step 120
In the notch state after alignment, calculate from described head pointer and point to continuous idle notch number that notch begins and upgrade described head pointer with this, the notch that will be in the preparation attitude is simultaneously selected; Step 130
Selection is pointed to first preparing slot that notch begins from described head pointer, and upgrades the read pointer of current operation queue with the pointer of this notch, adds up the quantity of preparing slot simultaneously and upgrades the number of results of current operation queue; Step 140
When the number of results of this formation is non-vanishing, obtain effective slogan of groove as a result of one of foremost in this formation according to the read pointer of this formation, read the instruction results that mouth is read this notch by result's buffering.Step 150
On the basis of the foregoing description, the present invention can also do various conversion, can be according to the performance requirement decision of using as the formation number average of buffer depth of the present invention, management.The full criterion of above-mentioned buffering when buffered segment is used, just be not by head, whether tail pointer equates has judged.In addition, the division of pipelining segment is not limited to the mode of embodiment.
Claims (13)
1, a kind of many queue sequenceization cache management circuit based on streamline, it is characterized in that, adopt pipeline organization, comprise arbitration circuit, buffering notch state setting module, buffering notch filtering module, formation notch selection module and formation notch priority queue module, wherein:
Described arbitration circuit, receive and to read request as a result, write request as a result, the distributing buffer request and and the corresponding instruction queue of each request number, notch numbering, from request signal, choose one the tunnel and handle;
Described buffering notch state setting module is provided with the notch state and the queue number of solicit operation, buffering less than the time, be that the distributing buffer request distributes idle notch that tail pointer points to and the tail pointer that upgrades the buffering notch;
Described buffering notch filtering module, filtering do not belong to current operation queue and are not the notch states of Idle state, then the notch state that obtains are alignd according to the head pointer that cushions notch;
Described formation notch is selected module, in the notch state after alignment, calculates from described head pointer and points to continuous idle notch number that notch begins and upgrade described head pointer with this, and the notch that will be in the preparation attitude is simultaneously selected;
Described formation notch priority queue module, selection is pointed to first preparing slot that notch begins from described head pointer, and upgrade the read pointer of current operation queue with the pointer of this notch, add up the quantity of preparing slot simultaneously and upgrade the number of results of current operation queue.
2, cache management circuit as claimed in claim 1, it is characterized in that, select the built-up circuit of module and formation notch priority queue module to be divided into four pipelining segments, synchronous working under the clock signal effect by described buffering notch state setting module, buffering notch filtering module, formation notch.
3, cache management circuit as claimed in claim 2, it is characterized in that, described buffering notch state setting module comprises at least: the register of storing notch state, queue number and current queue number respectively, the tail pointer maker, head pointer, tail pointer register and the empty full scale will generation unit that links to each other with head, tail pointer register, this generation unit produce buffering full scale will at head, when tail pointer is identical.
4, cache management circuit as claimed in claim 3, it is characterized in that, described formation notch selects module to comprise at least: the head pointer updating block, be used for the continuous idle notch number that will obtain and described head pointer in the adder addition, as the input of head pointer register in the described buffering notch state setting module; And the preparing slot selected cell, be used for preparing slot and other state notch are differentiated.
5, cache management circuit as claimed in claim 4, it is characterized in that, described formation notch priority queue module comprises at least: the read pointer updating block, be used for calculating the sequence number of first preparing slot according to the output of described preparing slot selected cell, obtain the pointer of this notch with described head pointer addition, under the enable signal effect of current queue, upgrade the head pointer of current queue in the formation read pointer register; The number of results updating block is used for calculating according to the output of described preparing slot selected cell the quantity of preparing slot, and upgrades the number of results of current queue in the formation number of results register under the enable signal effect of current queue; And read selected cell, by linking to each other with the formation read pointer register, receive two multi-selection devices reading result queue's signal input and form with described formation number of results register.
6, cache management circuit as claimed in claim 1 is characterized in that, when there was multiple request at the same time in described arbitration circuit, the preferential selection read request as a result, secondly is to write request as a result, is the distributing buffer request at last.
7, a kind of many queue sequenceization amortization management method based on streamline may further comprise the steps:
(a) receive read request as a result, write request as a result, the distributing buffer request and and the corresponding instruction queue of each request number, notch numbering, from request signal, choose one the tunnel and handle;
(b) the notch state and the queue number of solicit operation are set, buffering less than the time, be that the distributing buffer request distributes idle notch that tail pointer points to and the tail pointer that upgrades the buffering notch;
(c) filtering does not belong to current operation queue and is not the notch state of Idle state, then the notch state that obtains is alignd according to the head pointer that cushions notch;
(d) in the notch state after alignment, calculate from described head pointer and point to continuous idle notch number that notch begins and upgrade described head pointer with this, the notch that will be in the preparation attitude is simultaneously selected;
(e) select to point to first preparing slot that notch begins, and upgrade the read pointer of current operation queue, add up the quantity of preparing slot simultaneously and upgrade the number of results of current operation queue with the pointer of this notch from described head pointer;
(f) when the number of results of this formation is non-vanishing, obtain effective slogan of groove as a result of one of foremost in this formation according to the read pointer of this formation, read the instruction results that mouth is read this notch by result's buffering;
Described step (b) is to the mode executed in parallel of step (e) with streamline.
8, amortization management method as claimed in claim 7, it is characterized in that, in the described step (a), described distributing buffer request was submitted to before instruction is carried out by the CHIP processing unit, describedly write request as a result and submit to during for the last character in the write operation of this instruction results, the request as a result of reading is submitted to during for the last character in read operation.
9, amortization management method as claimed in claim 7 is characterized in that, in the described step (a), judge whether full standard is buffering: if described tail pointer and head pointer equate that then buffering is full, otherwise the end is full.
10, amortization management method as claimed in claim 7 is characterized in that, described streamline is the level Four streamline.
11, amortization management method as claimed in claim 7 is characterized in that, in the described step (f) same formation Different Results is read the spacing that will exist at least with streamline hop count same number of cycles.
12, amortization management method as claimed in claim 7 is characterized in that, when receiving a plurality of request at the same time, the preferential selection read request as a result, secondly is to write request as a result, is the distributing buffer request at last.
13, amortization management method as claimed in claim 7 is characterized in that, in the described step (c), by will not belonging to current operation queue and not being that the notch state of Idle state changes another into and " takies " attitude, finishes the filtering function to the notch state.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101963896A (en) * | 2010-08-20 | 2011-02-02 | 中国科学院计算技术研究所 | Memory device with quadratic index structure and operation method thereof |
| CN103166873A (en) * | 2011-12-12 | 2013-06-19 | 中兴通讯股份有限公司 | Inter-core communication method and core processor |
| CN111625377A (en) * | 2017-04-01 | 2020-09-04 | 北京忆芯科技有限公司 | Agent and method for adding entries to a queue |
| CN112562165A (en) * | 2020-12-08 | 2021-03-26 | 石家庄通合电子科技股份有限公司 | Charging queue and module allocation algorithm |
| CN114185513A (en) * | 2022-02-17 | 2022-03-15 | 沐曦集成电路(上海)有限公司 | Data caching device and chip |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11184695A (en) * | 1997-12-19 | 1999-07-09 | Nec Corp | Cache memory and method for access to the same |
| US6272609B1 (en) * | 1998-07-31 | 2001-08-07 | Micron Electronics, Inc. | Pipelined memory controller |
| CN1380609A (en) * | 2001-04-11 | 2002-11-20 | 矽统科技股份有限公司 | Method for predicating access request sequence of storage unit |
-
2003
- 2003-12-29 CN CNB2003101129736A patent/CN100362839C/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101963896A (en) * | 2010-08-20 | 2011-02-02 | 中国科学院计算技术研究所 | Memory device with quadratic index structure and operation method thereof |
| CN101963896B (en) * | 2010-08-20 | 2012-11-14 | 中国科学院计算技术研究所 | Memory device with quadratic index structure and operation method thereof |
| CN103166873A (en) * | 2011-12-12 | 2013-06-19 | 中兴通讯股份有限公司 | Inter-core communication method and core processor |
| CN111625377A (en) * | 2017-04-01 | 2020-09-04 | 北京忆芯科技有限公司 | Agent and method for adding entries to a queue |
| CN111625377B (en) * | 2017-04-01 | 2023-11-28 | 北京忆芯科技有限公司 | Agent and method for adding items to queue |
| CN112562165A (en) * | 2020-12-08 | 2021-03-26 | 石家庄通合电子科技股份有限公司 | Charging queue and module allocation algorithm |
| CN112562165B (en) * | 2020-12-08 | 2023-02-03 | 石家庄通合电子科技股份有限公司 | Charging queue and module allocation algorithm |
| CN114185513A (en) * | 2022-02-17 | 2022-03-15 | 沐曦集成电路(上海)有限公司 | Data caching device and chip |
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| Publication number | Publication date |
|---|---|
| CN100362839C (en) | 2008-01-16 |
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