CN1540537A - Method and device of reusing MPEG transmission stream for high-speed Ethernet port - Google Patents
Method and device of reusing MPEG transmission stream for high-speed Ethernet port Download PDFInfo
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Abstract
The device includes following parts: a CPU carries out reuse calculation for MPEG stream from Ethernet port and from serial-parallel signal interface; a storage module connected to CPU includes a input FIFO, an output FIFO and multiple SDRAM; a FPGA module contains sub modules of input data packet filtering, calculation of input speed rate, bus processing, input control, output control and output clock control. Speed rate of transmission reaches 50Mbps. The device implements reuse of MPEG transmission stream independently, providing features of close fitting between FAGAN and CPU in design, optimized algorithm and clear flow in software design, and controlling capability and data reuse provided by Ethernet interface.
Description
Technical field
The present invention relates to have in a kind of digital television broadcasting the multiplexing again method and the corresponding device thereof thereof of mpeg data stream of Fast Ethernet input interface.
Background technology
At present, the digitizing of radio and television is in the ascendant in the whole world, and various specialized digital broadcast television equipment are widely used; Meanwhile, computer technology also is applied to field of broadcast televisions increasingly extensively.(transport stream is a kind of data stream format of mpeg compliant to transmit flow data to the MPEG (Motion Picture Experts Group-motion picture expert group (global image/sound/system compresses standard)) of storage or generation in the computing machine, be mainly used in the transmission of radio and television digital signal, be different from the program stream format that is used for VCD, DVD laser disc) how to be multiplexed into other transport stream easily and effectively and just to become a urgent problem.The dedicated transmissions stream re-multiplexer that at present more domestic and international main broadcasting equipment manufacturers provide all adopts real-time parallel or serial data interface, even the Ethernet interface that possesses the connection computing machine that has also all is the low rate control interface, can't be as video transmission flow data inlet at a high speed.So if realize data flow data and other data stream of computer-internal multiplexing, common way is exactly special-purpose PCI (the PCI-Peripheral Component Interconnection-Peripheral Component Interconnect standard of inserting in computing machine both at home and abroad at present, technology) interface card, real-time continuous ground is forwarded to dedicated serial or parallel data grabbing card after will be from the data flow data buffer memory of pci interface on the card, and then by re-multiplexer different transmission flow multiplexes is arrived together.Directly do not import because present multiplexing equipment is not considered the computing machine transmit flow data, though so the many specific aims of input interface but not strong, the while is bulky, price is high.It is the difficulty that the service provider of important information source has brought cost and operation aspect with computer data that the twists and turns of data channel and device itself huge and complicated given those undoubtedly.In order to overcome these difficulties, the present invention proposes a kind of transmission stream remultiplexing device and remultiplexing method thereof that possesses high speed (100Mbps) (bps-Bit per second-bits per second) Ethernet interface and Asynchronous Serial Interface or synchronous parallel interface simultaneously, this device has been realized between Ethernet interface and the computing machine connection at a high speed, realizes from multiplexing again from the transport stream of dedicated serial interface of the transmit flow data of Ethernet interface and other in that device is inner.
Summary of the invention
The purpose of this invention is to provide a kind of to from the transmit flow data of (100Mbps) Ethernet interface at a high speed and and carry out again multiplexing method and apparatus from the transmit flow data of Asynchronous Serial Interface or synchronous parallel interface (hereinafter to be referred as the serial parallel signaling interface), wherein the Fast Ethernet interface is used for the connection between device and the computing machine, not only as control interface also as the mpeg transport stream input interface; Inner at device, the multiplexing again back that can carry out any appointment of user with the transmit flow data from the serial parallel signaling interface from the transmit flow data of Fast Ethernet generates one tunnel new mpeg transport stream by the output of another one dedicated serial interface.
For reaching above-mentioned purpose, technical scheme of the present invention is:
A kind of to the mpeg transport stream reuse device by the Fast Ethernet inlet, it comprises:
A central processing unit (CPU) chip, it is the control core of this device, to carrying out again multiplexing computing, and export at least one new mpeg transport stream by at least one dedicated serial interface from the mpeg transport stream of at least one Ethernet port with from the transmit flow data of at least one serial parallel signal input port;
A memory module is connected with CPU, comprises at least one input FIFO (pushup storage), at least one output FIFO and at least one SDRAM composition;
At least one signal input module, each signal input module are arranged at a described serial parallel signal input port, and the signal of being imported is carried out format conversion;
At least one Fast Ethernet input interface module, each Fast Ethernet input interface module is arranged at a described Ethernet port, and is connected with described central processing unit, realizes communicating by letter between central processing unit and the Ethernet;
Between described signal input module and CPU, be connected with a field programmable gate array (FPGA) module, comprise at least in this FPGA module:
Input Packet Filtering submodule is connected with described signal input module, from input
The packet that selection needs in the transport stream of signal participates in multiplexing, and abandons other data
Bag is when needs abandon packet continuous more than 1 or 1, at the input letter
Number transport stream in insert a designation data bag at interval, this packet and general data
Be surrounded by identical byte length and grammer, its PID is set to the PID of invalid bag
(0x1fff), and in preceding 4 bytes of data load the number of discarded packets is set
Order;
The input rate calculating sub module is gathered the data from input Packet Filtering submodule,
By being counted, the clock signal in the input signal after filtering obtains to import data
The speed of stream;
The bus processing sub is connected with the input rate calculating sub module with CPU, handles
The bus interface signal of FPGA and CPU comprises that the speed that transmits input traffic arrives
CPU and obtain the Packet Filtering configuration information from CPU;
The input controlling sub is arranged at input Packet Filtering submodule and at least one is failed
Go into between the pushup storage (FIFO), finish this input usefulness FIFO at the beginning of
Beginningization and configuration effort, and will come from the transport stream of importing the Packet Filtering submodule
Data are written to this at least one input with in the FIFO;
Output clock control submodule is connected with the frequency synthesizer of being located at the FPGA outside,
And control this frequency synthesizer and generate the required byte clock of output signal;
The output controlling sub is obtained the byte clock from output clock control submodule,
Finish initialization and the configuration effort of output with FIFO, control output is used among the FIFO
Data are read, and assist the object transmission flow data to enter output module;
At least one signal output module, each signal output module are arranged at a described output with after the FIFO, and the object transmission flow data is carried out final coding and output.
Technical scheme of the present invention also comprises: a kind of mpeg transport stream remultiplexing method with Fast Ethernet inlet, wherein after setting up the Ethernet connection and connecting the serial parallel signal input interface, start-up control information monitoring program and multiplexing again program, to carrying out the multiplexing again of any appointment of user, generate one tunnel new mpeg transport stream and output then from the transmit flow data of Fast Ethernet with from the transmit flow data of serial parallel signal input interface;
Wherein, the control information monitoring facilities is two parallel working routines with multiplexing program again, mutually between by message communicating, and shared data packet filtering information, transport stream rate information, information on services buffer zone and PID remapping information.
Beneficial effect of the present invention is: it has realized the multiplexing again of the interior transmit flow data of computing machine and other transport stream with an independent device, multiplexing algorithm and system is compact to design and succinct again, made full use of the transmittability of Fast Ethernet, not only realized that computing machine was to the control of device but also realized the transmission of computer data and multiplexing again, this novel re-multiplexer is powerful, volume is little, and is easy to use.
Description of drawings
Fig. 1 is a system architecture block scheme of the present invention;
Fig. 2 is the central processing unit connection diagram of this device;
The process flow diagram of Fig. 3 software primary control program;
Fig. 4 is the process flow diagram of software control information monitoring program;
Fig. 5 is the software process flow diagram of multiplexing program again.
Embodiment
With a specific embodiment in detail technical scheme of the present invention is described in detail below in conjunction with accompanying drawing.
Please see Figure 1, be the block diagram of system of mpeg transport stream reuse device 100 of the present invention.In the present embodiment, comprise two-way transport stream asynchronous serial inlet---ASI (Asynchronous SerialInterface-Asynchronous Serial Interface, ASI) input interface 1, and ASI input interface 2, with one road Fast Ethernet input interface 3, come from the transmit flow data of this Fast Ethernet interface 3 with from ASI input interface 1, after 2 transmit flow data signal is imported this device, through the control of this device 100 and the processing of arithmetic core central processing unit (CPU), after carrying out any appointment of user multiplexing again, generate one tunnel new mpeg transport stream and export, thereby finish purpose of the present invention by ASI output interface 4.But, it should be noted that, input interface of the present invention and output interface are not limited to the ASI interface, can replace serial line interface load module and serial line interface output module in the practical application and be synchronous parallel interface (SPI-Synchronous Parallel Interface) load module and run simultaneously and connect output module, adopting model during enforcement respectively is that the chip of DS90C32 and DS90C31 just can be realized; Simultaneously, the present invention is not limited to have only two serial parallel signal input interfaces, can comprise a plurality of input interfaces or a plurality of Ethernet input interface or a plurality of serial parallel signal output interface in actual applications.
The present invention includes hardware and software two parts, hardware components i.e. as shown in Figure 1 mpeg transport stream reuse device 100 of the present invention, and software section is then for solidifying the working procedure in the EPROM (EPROM) of the central processing unit (CPU) of device 100.Below respectively this two part is described in detail:
Hardware components
As shown in Figure 1, the hardware of mpeg transport stream reuse device 100 of the present invention comprises: central processing unit 110, memory module 120, serial line interface load module 130, FPGA (Field ProgrammableGate Array, field programmable gate array) module 140, Fast Ethernet interface module 150 and serial line interface output module 160.Wherein:
One, central processing unit (CPU) 110 is the control and the arithmetic core of this device 100, by it
The software of inside solidification carries out multiplexing calculating, this software to the signal of importing this device 100
Flow process repeats after holding; This cpu chip can adopt the XPC8245-350 of motorola inc
Processor, high primary frequency reaches 350MHz, possesses 32 pci interfaces and 32 bit data
Memory interface.
Two, memory module 120, comprise SDRAM (Synchronous Dynamic Random Access
The Memory-Synchronous Dynamic Random Access Memory) group 1201, input FIFO 1, FIFO
2 and output (FIFO-First In First Out memory-goes into earlier with FIFO 3
Go out storer earlier), wherein SDRAM group 1201 is important external devices of CPU 110, uses
The data and the program of coming buffer memory CPU to handle; Input is used for the buffer memory warp with FIFO 1, FIFO 2
Will enter the transmit flow data of CPU after the processing; Output is used for buffer memory CPU place with FIFO 3
Will enter the transmit flow data of output module after the reason.
Three, the serial line interface load module 130, and its major function is to finish the format conversion of input signal; With
Two groups of inputs in the present embodiment are corresponding, and this module 130 also comprises two groups of circuits, every group
Circuit comprises an input coupling Shaping Module 1301 and line decoding module 1302, respectively
The ASI form that will come from the input signal of ASI input interface 1,2 is changed; This ASI
Signal is the signal of serial 270Mbps, and input coupling Shaping Module 1301 is finished the coupling of signal
Close and shaping, it is PE65508 pulse transformer chip that present embodiment adopts model, and circuit is separated
Sign indicating number module 1302 adopts an ASIC (Application Specific Integrated
The Circuit-special IC) finish bit clock and recover, the decoding of signal reaches
10bit/8bit conversion is exported after converting thereof into parallel signal, in the present embodiment, and should
It is the chip of CY7C933 that line decoding module 1302 adopts model.
Four, field programmable gate array (FPGA) module 140, can adopt XILINX company
XC2S100PQ208, inside comprises two input Packet Filterings 1401, input rates and calculates
1402, bus processing sub 1403, input control 1404, output control 1405, output
A little module is further described:
Input Packet Filtering submodule 1401 is used for selecting the elementary stream of needs to participate in multiplexing from the transport stream of input; Corresponding with two groups of inputs in the serial line interface load module 130, present embodiment has designed two input Packet Filterings 1401, is connected with two groups of inputs respectively; Different elementary streams is that bag identification field (PID, Packet Identifier-Packet Identifier) with the packet head is discerned in the transport stream, and the elementary stream of need selecting is exactly to make to specify the packet of PID to pass through, and abandons other packet; Owing in subsequent reuse work, need to understand the position of each packet in former transport stream, therefore adopt a kind of bag replacement technology here, specific practice is: when needs abandon packet continuous more than 1 or 1, insert a designation data bag at interval, this packet is surrounded by identical byte length and grammer with general data, its PID is set to the PID (0x1fff) of invalid bag, and in preceding 4 bytes of data load the number of discarded packets is set; So both obtain the positional information that effectively wraps in the primary flow, kept the synchronous of transport stream again;
Input rate calculating sub module 1402 is connected with input Packet Filtering submodule 1401, and the clock signal in the parallel signal that comes from serial line interface load module 130 is counted to obtain the speed of input traffic, to offer CPU; Reference clock is local master clock (frequency is 27MHz), it just in time was 1 second that master clock count down to 27000000 process from 1, be exactly total the current byte-rate of the number input signal that the clock line pulse arrives in per 1 second kind counting input parallel signal is only added up the speed that all packets of choosing arrive here;
Input controlling sub 1404, the buffer memory of the transmit flow data behind the responsible controlled filter; Transmit flow data after filtering is write input FIFO 1 and FIFO 2, and control the initialization of FIFO 1 and FIFO 2 and FIFO 1 is set and the full scale register of FIFO 2, FIFO 1 and FIFO 2 link to each other full scale will signal respectively with the interrupt pin of CPU, when data reach certain full level, will cause that a signal wire level changes, trigger CPU and interrupt; So the data in FIFO 1 and FIFO 2 reach certain full level, CPU
Just can be in the interrupt response program with data from FIFO storer FIFO 1 and FIFO 2
Middle transfer is also read in;
Output controlling sub 1405 connects output with FIFO 3, controls answering from CPU
With the buffer memory of result data, this submodule 1405 obtains from output clock control submodule 1405
The byte clock signal, be responsible for reading of control FIFO 3, and the reciprocal of duty cycle that FIFO 3 is set is posted
Storage, when data are read out certain degree, promptly Cun Chu data reduce to certain degree
The time, will cause that a signal wire level changes, another of this signal wire and CPU interrupts please
Ask pin to connect, can trigger CPU and interrupt.So the data in FIFO are read out one
Fixed degree, CPU just can be written to FIFO 3 with multiplexing result data in the interrupt response program
In;
Output clock control submodule 1406 is connected with a frequency synthesizer 1407, and is main
It is needed to be that controlled frequency compositor 1407 makes it to generate output signal according to user's setting value
Byte output clock.Frequency synthesizer 1407 can adopt the AD9850 chip of AD company.
Five, the Fast Ethernet interface module 150, realize the ether between this device 100 and the outer computer
Net connects; This module 150 adopts the Intel 82559er network interface core of Intel company
Sheet, one end are 100M Ethernet interface signals, and the other end is the pci interface signal, by
32 pci buss are connected with central processing unit, realize between central processing unit and the Ethernet
Communication.
Six, the serial line interface output module 160, receive the data of reading and finish the output letter from FIFO 3
The conversion of number form; Here adopted a special IC 1601---CY7C923 line
The road scrambler is finished the coding of data flow data to the ASI signal, the serial of output 270Mbps
Signal, export coupling drive circuit 1602 in addition in addition---PE65508 pulse transformer core
Sheet is finished the driving and the coupling output of ASI signal; Because of this part is a prior art, and non-
The emphasis of invention is so repeat no more.
As shown in Figure 2, Fig. 2 is the central processing unit connection diagram of this device; In this device, FPGA module, input all are articulated on the memory bus of CPU as the peripheral memory devices of 16 bit data with FIFO with FIFO and output, and SDRAM then directly links to each other with the sdram interface bus of CPU.
Software section
Described software mainly comprises following 5 parts under primary control program: transmission flow multiplex program, control information monitoring facilities, reference clock revision program, information on services generator program and transmit flow data written-out program.
Be described in detail the characteristic and the course of work thereof of CPU program each several part of the present invention below in conjunction with Fig. 3-5:
At first please see primary control program, this program is the master routine of CPU software, also is father's program of other program.Fig. 3 is the process flow diagram of primary control program, and its function is soft, the hardware parameter of initialization, sets up Ethernet and connects, then start-up control information monitoring program and multiplexing again program.As shown in Figure 3, the concrete job step of primary control program is as follows:
210: program begins;
220: soft, the hardware parameter of initialization;
230: set up Ethernet and connect;
240: start-up control information monitoring program; Its intrinsic call information on services generator program;
250: start multiplexing again program; Its intrinsic call reference clock revision program and transmit flow data written-out program.
In above-mentioned steps 240 and 250, the control information monitoring facilities is two parallel working routines with multiplexing program again, pass through message communicating mutually, and public variable or buffer zones such as shared data packet filtering information, transport stream rate information, information on services buffer zone and PID remapping information.Below divide 5 parts to introduce subroutine of the present invention:
One, control information monitoring facilities
After the start-up control information monitoring program in above-mentioned steps 240 (its main body is the control information monitoring facilities), can the control signal from Ethernet be monitored that Fig. 4 is the process flow diagram of this program, its job step is as follows:
241. whether the monitoring Ethernet port receives the TCP message that comprises control information;
242. obtain the information content of control port;
243. the control information content of being obtained is judged:
If 244. control information comprises " starting multiplexing " or " stopping multiplexing " order, this program sends corresponding message and arrives multiplexing program more so.
If 245. control information comprise be " renewal job information " order, so its concrete update content can comprise in the Packet Filtering information of upgrading, transport stream rate information, PID remapping information and the service message buffer any one or a plurality of, one or more in the following action of corresponding employing:
2451. selection information configuration Packet Filtering module according to PID;
2452. record is from the original rate of the transport stream of Ethernet;
2453. dispose the PID replay firing table that the transmission flow multiplex program is used according to the PID remapping information;
2454. call information on services generator program (the information on services generator program also is a submodule of the present invention, is detailed later) and update service information.
Two, transmission flow multiplex program
11, realizing main multiplexing operation, is the core of system.Fig. 5 is the process flow diagram of multiplexing program (its main body is the transmission flow multiplex program).Its job step is as follows:
2501. constantly supervisory messages formation goes on foot if receive " starting multiplexing " message then enter 251;
251. the transport stream port that Ethernet connects is monitored, if receive the TCP message that comprises transmit flow data, then read Ethernet transport stream port data, and transmit flow data is transferred to No. 1 " but backrush " (recycling) buffer zone that is arranged in SDRAM shown in Figure 1 1201.
252. in the interrupt response program of input FIFO, two inputs are read in DMA (visit of Direct Memory Access-direct memory) mode with the data of storer FIFO 1, FIFO 2 (respectively corresponding two different transport stream enter the mouth) among the SDRAM 1201 No. 2 and No. 3 " but backrush " buffer zones in.
253. from data source, read a packet; The data source of multiplexing object flow is stored among the SDRAM 1201, and from 5 parts, they are: 3 " but backrush " buffer zones, information on services buffer zone and empty bag tucker (the sky bag that it is 0x1fff that empty bag tucker is deposited a PID).The speed of multiplexing object transmission stream should add information on services speed more than or equal to 3 input transport stream speed sums, fills speed=object transmission flow rate-three input transport stream speed sum-information on services speed of empty bag.Multiplexing operation is exactly the speed proportionate relationship according to each circuit-switched data source of having known, reads a packet from data source at every turn, makes the sum of each buffer zone sense data bag be directly proportional with the speed of each road transport stream;
254. judge that then the PID of this packet needs to remap?
255. if the PID of the packet that multiplexing operation the time is read appears in the PID replay firing table, so just the value of this PID is modified as the value of appointment in the mapping table; Otherwise just directly carry out next step.
256. the PID of the packet of reading when then judging multiplexing the operation includes PCR (ProgramClock Reference-program clock reference)?
257. if then call the reference clock revision program PCR revised; If not, then directly carry out next step.
258. then amended packet is put into the buffer zone of object transmission stream.
259. call the transport stream written-out program object transmission stream is written to output FIFO from buffer zone;
2502. the inspection message queue, and if received " stopping multiplexing " message would enter 2501 the step, otherwise enter 251 the step.
Three, reference clock revision program
The reference clock revision program of above-mentioned steps 257 is used for adjusting the value of PCR, because in original data stream, comprised the original reference clock information of MPEG video encoding, in multiplexing process, change has taken place in the order of packet, could guarantee that demoder correctly recovers the original coding clock so must revise the numerical value of PCR.Its concrete job step is:
2601. according to the original transmitted speed that byte location difference and the PCR numerical value difference of the adjacent PCR in per two front and back in the inlet flow can calculate the transport stream that comprises this PCR, computing formula is:
Original transmitted speed=PCR byte location difference ÷ PCR numerical value difference * 27000000
2602. can calculate the ideal position of PCR in the object flow according to the difference of the position of PCR in the inlet flow and inlet flow and object flow transfer rate, computing formula is:
PCR ideal position=PCR original position * object flow speed ÷ original transmitted speed
2603. according to actual multiplexing position and the difference of the ideal position correction difference that can calculate PCR of PCR in object flow, computing formula is:
PCR correction difference=
(the actual multiplexing position of PCR-PCR ideal position) ÷ object flow speed * 27000000
2604. revise PCR numerical value, computing formula is:
Object flow PCR newly is worth=and inlet flow PCR numerical value+PCR revises difference
Four, information on services generator program
This program is a subroutine in the control information monitoring facilities, shown in the step 2454 among Fig. 4, the information on services generator program provides basic program service information, these information on services have set the hierarchical relationship between transport stream-program-packet, have also comprised the various supplementarys that the service provider need convey to user's decorder.The job step of this program following (not having diagram):
2701. the information on services that obtains in the control program is packaged into the form of transport stream data packet, and information on services comprises Program Association Table (PAT-Program Association Table-Program Association Table), Program Map Table (PMT-Program Map Table-Program Map Table), network information table (NIT-Network Information Table-network information table), service describing table (SDT-ServiceDescription Table-service describing table).
2702. require each packet is ordered in the information on services buffer zone according to the transmission intercal of each service information table and read for multiplexing program, the order that this packet is arranged is to determine according to the speed of each service information table and mutual proportionate relationship, the service information table packet arranging density height that speed is high, and the low service information table packet arranging density of speed is low.PAT and PMT required transmit once in per at the most 0.5 second, and NIT required transmit once in per at the most 10 seconds, and SDT required transmit once in per at the most 2 seconds.
Five, transmit flow data written-out program
Please see Figure the step 259 in 5, this transmit flow data written-out program is finished the object transmission streambuf and is transmitted with the data between the FIFO 3 to output, and its way is:
With in the interrupt response program of FIFO 3, the byte of reading fixed number with dma mode from the object flow buffer zone is written to output with among the FIFO 3 at every turn in output.
The description of comprehensive above two-part hardware and software, apparatus and method of the present invention are in concrete the application, at first be connected with netting twine between the Ethernet interface of this device and the outer computer, and connection serial parallel signal input interface, after device powers on, in house software promptly brings into operation, reception is from the external control information of Ethernet and to from the transport stream of serial parallel signal input interface with carry out multiplexingly from the transport stream of Fast Ethernet interface again, and multiplexing result transmission stream is sent by the serial parallel signal output interface.The speed of input and output transport stream of the present invention can reach 50Mbps, satisfies the requirement of 30～48Mbps speed in the field practicality of digital broadcasting and TV fully; And the present invention has realized the multiplexing again of the interior transmit flow data of computing machine and other transport stream with an independent device, aspect system design, the division of labor between FPGA and the CPU is clear and definite and cooperate tight, aspect the multiplexing again software design of CPU, the algorithm optimized and flow process have clearly been proposed, aspect Ethernet interface, not only realized that computing machine was to the control of device but also realized the transmission of computer data and multiplexing again; In a word, re-multiplexer of the present invention is powerful, and volume is little, and is easy to use, has market potential.
Claims (10)
1, a kind of mpeg transport stream reuse device with Fast Ethernet inlet, it is characterized in that: it comprises:
A central processing unit (CPU) chip, it is the control core of this device, to carrying out again multiplexing computing hereinafter to be referred as the mpeg transport stream data of serial parallel signaling interface, and export at least one new mpeg transport stream by at least one serial parallel signaling interface from the mpeg transport stream of at least one Ethernet port with from least one;
A memory module is connected with CPU, comprises at least one input FIFO (pushup storage), at least one output FIFO and a plurality of SDRAM;
At least one signal input module, each signal input module are arranged at a described serial parallel signal input port, and the signal of being imported is carried out format conversion;
At least one Fast Ethernet input interface module, each Fast Ethernet input interface module is arranged at a described Ethernet port, and is connected with described central processing unit, realizes communicating by letter between central processing unit and the Ethernet;
Between described signal input module and CPU, be connected with a field programmable gate array (FPGA) module, comprise at least in this FPGA module:
Input Packet Filtering submodule, be connected with described signal input module, the packet of need selecting from input signals stream participates in multiplexing, and abandon other packet, when needs abandon packet continuous more than 1 or 1, in input signals stream, insert a designation data bag at interval, this packet is surrounded by identical byte length and grammer with general data, its PID is set to the PID (0x1fff) of invalid bag, and in preceding 4 bytes of data load the number of discarded packets is set;
The input rate calculating sub module is gathered the data from input Packet Filtering submodule, by the clock signal of filtering in the input signal of back is counted the speed that obtains input traffic;
The bus processing sub is connected with the input rate calculating sub module with CPU, handles the bus interface signal of FPGA and CPU, comprises that the speed that transmits input traffic arrives CPU and obtains the Packet Filtering configuration information from CPU;
The input controlling sub, be arranged at input Packet Filtering submodule and at least one input with between the pushup storage (FIFO), finish this input initialization and configuration effort, and the transmit flow data that will come from input Packet Filtering submodule is written to this at least one input with in FIFO with FIFO;
Output clock control submodule is connected with the frequency synthesizer of being located at the FPGA outside, and controls the required byte clock of this frequency synthesizer generation output transport stream;
The output controlling sub is obtained the byte clock from output clock control submodule, finishes initialization and the configuration effort of output with FIFO, and control output is read with the data among the FIFO, assists the object transmission flow data to enter output module;
At least one signal output module, each signal output module are arranged at a described output with after the FIFO, and the object transmission flow data is carried out final coding and output.
2, device as claimed in claim 1 is characterized in that: this CPU operating software comprises: transmission flow multiplex program, control information monitoring facilities, reference clock revision program, information on services generator program and transmit flow data written-out program.
3, device as claimed in claim 1, it is characterized in that: each signal input module inside comprises an input coupling Shaping Module and a line decoding module, at first enter this input coupling Shaping Module from the transmit flow data of described serial parallel signal input port and carry out shaping, and then carry out format conversion by this line decoding module; FIFO in the described memory module is articulated on the memory bus of CPU as the peripheral memory devices of 16 bit data, and SDRAM then directly links to each other with the sdram interface bus of CPU; FIFO is used for the buffer memory transmit flow data, and SDRAM is used for storing working procedure and the handled data of CPU; Wherein FIFO full scale will signal is linked to each other with the interrupt pin of CPU used in input, can cause when data are filled to a certain degree in importing with FIFO that thereby this signal level variation causes CPU and interrupts, CPU will import with the data among the FIFO in interrupt handling routine and read in; Output links to each other empty marking signal with FIFO's with the interrupt pin of CPU, when output with FIFO in data can cause that thereby this signal level variation causes CPU and interrupts when reducing to a certain degree, CPU is written to the object transmission flow data to export in interrupt handling routine and uses FIFO.
4, device as claimed in claim 1, it is characterized in that: each described signal output module further comprises: line coding circuit and an output coupling drive circuit, described output is exported after through this line coding circuit, again by this output coupling drive circuit with the multiplexing result data of institute's buffer memory among the FIFO.
5, a kind of mpeg transport stream remultiplexing method with Fast Ethernet inlet, it is characterized in that: after setting up the Ethernet connection and connecting the serial parallel signal input interface, start-up control information monitoring program and multiplexing again program, to carrying out the multiplexing again of any appointment of user, generate one tunnel new mpeg transport stream and output then from the transmit flow data of Fast Ethernet with from the transmit flow data of serial parallel signal input interface;
Wherein, the control information monitoring facilities is two parallel working routines with multiplexing program again, mutually between by message communicating, and shared data packet filtering information, transport stream rate information, information on services buffer zone and PID remapping information.
6, method as claimed in claim 5 is characterized in that: the control information monitoring facilities can monitor that to the control signal from Ethernet job step is as follows:
241. whether the monitoring Ethernet port receives the TCP message that comprises control information;
242. obtain the information content of Ethernet port;
243. the control information content of being obtained is judged:
If 244. control information comprises " starting multiplexing " or " stopping multiplexing " order, this program sends corresponding message and arrives multiplexing program more so;
If 245. control information comprise be " renewal job information " order, so its concrete update content can comprise in the Packet Filtering information of upgrading, transport stream rate information, PID remapping information and the service message buffer any one or a plurality of, one or more in the following action of corresponding employing:
2451. Packet Filtering module according to the selection information configuration FPGA of PID;
2452. record is from the original rate of the transport stream of Ethernet;
2453. dispose the PID replay firing table that the transmission flow multiplex program is used according to the PID remapping information;
2454. update service information is also called the information on services generator program.
7, method as claimed in claim 6 is characterized in that: the information on services generator program in the step 2454 comprises:
2701. the information on services that obtains in the control program is packaged into the form of transport stream data packet, and information on services comprises Program Association Table (PAT), Program Map Table (PMT), network information table (NIT), service describing table (SDT);
2702. require each packet is ordered in the information on services buffer zone for multiplexing program again according to the transmission intercal of each service information table and read, the order that this packet is arranged is to determine according to the speed of each service information table and mutual proportionate relationship, the service information table packet arranging density height that speed is high, and the low service information table packet arranging density of speed is low.
8, as claim 5 or 6 described methods, it is characterized in that: multiplexing again program work step is as follows:
2501. constantly supervisory messages formation is if receive " starting multiplexing " message then enter step 251;
251. read Ethernet transport stream port data, but and transfer to a rollback buffer that is arranged in SDRAM;
252. in the interrupt response program of input, but at least one data of importing with the FIFO storer is read at least one rollback buffer that is arranged in SDRAM respectively with the FIFO storer;
253. from the data source of multiplexing object flow, read a packet; But the data source of this multiplexing object flow is from least one above-mentioned rollback buffer, information on services buffer zone and an empty bag tucker; Wherein, the speed of multiplexing object transmission stream adds information on services speed more than or equal to input transport stream speed sum, fills the speed=object transmission flow rate-input transport stream speed sum-information on services speed of empty bag; Multiplexing operation is exactly the speed proportionate relationship according to each road transport stream of having known, reads a packet from data source at every turn, makes the sum of each buffer zone sense data bag be directly proportional with the input rate of each road transport stream.
9, method as claimed in claim 8 is characterized in that: in the step 253 packet of being read is made amendment, further comprise:
254. judge that the PID of this packet needs to remap?
255. if the PID of the packet that multiplexing operation the time is read appears in the PID replay firing table, so just the value of this PID is modified as the value of appointment in the mapping table; Otherwise just directly carry out next step;
256. the PID of the packet of reading when then judging multiplexing the operation is the PID that includes the packet of PCR?
257. if then call the reference clock revision program PCR revised; If not, then directly carry out next step;
258. the content of the packet of reading during with multiplexing operation writes the object flow buffer zone;
259. call the transport stream written-out program object transmission stream is written to output FIFO from buffer zone;
2502. the inspection message queue, and if received " finishing multiplexing " message would enter 2501 the step, otherwise enter 251 the step.
10, method as claimed in claim 9 is characterized in that: described reference clock revision program comprises:
2601. according to the original transmitted speed that byte location difference and the PCR numerical value difference of the adjacent PCR in per two front and back in the inlet flow can calculate the transport stream that comprises this PCR, computing formula is:
Original transmitted speed=PCR byte location difference ÷ PCR numerical value difference * 27000000
2602. can calculate the ideal position of PCR in the object flow according to the difference of the position of PCR in the inlet flow and inlet flow and object flow transfer rate, computing formula is:
PCR ideal position=PCR original position * object flow speed ÷ original transmitted speed
2603. according to actual multiplexing position and the difference of the ideal position correction difference that can calculate PCR of PCR in object flow, computing formula is:
PCR correction difference=
(the actual multiplexing position of PCR-PCR ideal position) ÷ object flow speed * 27000000
2604. revise PCR numerical value, computing formula is:
Object flow PCR newly is worth=and inlet flow PCR numerical value+PCR revises difference
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA031240046A CN1540537A (en) | 2003-04-23 | 2003-04-23 | Method and device of reusing MPEG transmission stream for high-speed Ethernet port |
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| CNA031240046A CN1540537A (en) | 2003-04-23 | 2003-04-23 | Method and device of reusing MPEG transmission stream for high-speed Ethernet port |
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| CNA031240046A Pending CN1540537A (en) | 2003-04-23 | 2003-04-23 | Method and device of reusing MPEG transmission stream for high-speed Ethernet port |
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| CN100433697C (en) * | 2006-06-01 | 2008-11-12 | 东南大学 | Multi-channel high-speed data processor and processing method |
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| CN102761396B (en) * | 2012-07-30 | 2015-01-07 | 哈尔滨工业大学 | High-speed serial interface based on FPGA (Field Programmable Gate Array) |
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| CN104717520A (en) * | 2013-12-13 | 2015-06-17 | 远升科技股份有限公司 | Method and system for digital video broadcasting service |
| CN104717520B (en) * | 2013-12-13 | 2018-03-13 | 远升科技股份有限公司 | Method and system for DVB service integration |
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| CN103729215B (en) * | 2013-12-20 | 2017-02-01 | 江苏锐天信息科技有限公司 | Ethernet board data input/output method |
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