CN1523645A - 半导体器件 - Google Patents

半导体器件 Download PDF

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CN1523645A
CN1523645A CNA2003101006384A CN200310100638A CN1523645A CN 1523645 A CN1523645 A CN 1523645A CN A2003101006384 A CNA2003101006384 A CN A2003101006384A CN 200310100638 A CN200310100638 A CN 200310100638A CN 1523645 A CN1523645 A CN 1523645A
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semiconductor chip
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semiconductor device
sheet element
insulating properties
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�¹��̫
德光成太
清水悟
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Renesas Technology Corp
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Abstract

在切割线区域，在不除去用于形成布线等的导电膜而使之残留的状态下进行切割，切出半导体芯片(1)。从背面(1b)一侧将规定的绝缘性片构件(3)贴附在该半导体芯片(1)上，位于半导体芯片(1)的背面、侧面和沿半导体芯片(1)的周边的表面(1a)部分被绝缘性片构件(3)覆盖。在半导体芯片(1)的周边，即使在残存于切割线区域的导电膜因切割而卷起产生毛刺(7)时，该毛刺(7)也被绝缘性片构件(3)覆盖，焊丝(9)与毛刺(7)就不直接接触了。由此，可得到在不除去位于切割线区域的导电膜而防止电短路的半导体器件。

Description

半导体器件
技术领域
本发明涉及半导体器件，特别是涉及防止切割时发生的毛刺与焊丝的电短路的半导体器件。
背景技术
在半导体器件的制造中，首先通过在半导体衬底(晶片)的状态下对晶片的表面进行规定的处理，形成元件及布线等。一旦在晶片的状态下所应进行的全部处理结束，晶片就沿切割线被切割，切出一个个半导体芯片。
对已切出的一个个半导体芯片进行包含规定的小片键合工序及焊丝键合工序等的规定的封装处理，完成半导体器件。
可是，如果沿切割线切割晶片，则位于切割线区域的导电膜卷起。因此，在进行焊丝键合时，存在焊丝与卷起的导电膜的部分接触，产生电短路之类的问题。
为了解决这样的问题，例如在特开平10-154670号公报、特开平11-204525号公报中提出了在进行切割前除去位于切割线区域的导电膜的制造方法。
通过在切割前预先除去位于切割线区域的导电膜，就不会发生因切割而引起导电膜卷起的情况。其结果是，可防止通过焊丝与已卷起的导电膜的部分接触而引起的电短路。
然而，在上述半导体器件的制造方法中，有必须在晶片的状态下设置除去位于切割线区域的导电膜用的附加的工序的问题。
发明内容
本发明是为了解决上述问题而进行的，其目的在于，提供一种不除去位于切割线区域的导电膜而能防止电短路的半导体器件。
本发明的半导体器件包括半导体芯片、导线和绝缘性片构件。在半导体衬底的主表面上形成规定的元件和电极部、在切割线区域残留导电膜的状态下对半导体芯片进行切割。导线与电极部接触的绝缘性片构件覆盖住沿半导体芯片的周边残存的导电膜的部分。
按照本发明的半导体器件，在不除去位于切割线区域的导电膜而使之残留的状态下进行切割，在所切出的半导体芯片中，残存于半导体芯片的周边的导电膜的部分被绝缘性片构件覆盖。由此，不使连接到电极部的导线与残存的导电膜直接接触就可以在半导体器件中防止电短路。
本发明的上述和其它的目的、特征、方面和优点可从涉及结合附图而得到理解的本发明的下面的详细说明中变得明白。
附图说明
图1是示出本发明实施例1的半导体器件的制造方法的一道工序的斜视图。
图2是在该实施例中图1所示的工序的局部剖面图。
图3是示出在该实施例中图1所示的工序后所进行的工序的斜视图。
图4是在该实施例中图3所示的工序的局部剖面图。
图5是示出在该实施例中图3所示的工序后所进行的工序的斜视图。
图6是在该实施例中图5所示的工序的局部剖面图。
图7是示出在该实施例中图5所示的工序后所进行的工序的局部剖面图。
图8是示出本发明实施例2的半导体器件的制造方法的一道工序的斜视图。
图9是在该实施例中图8所示的工序的局部剖面图。
图10是示出在该实施例中图8所示的工序后所进行的工序的斜视图。
图11是在该实施例中图10所示的工序的局部剖面图。
图12是示出在该实施例中图11所示的工序后所进行的工序的局部剖面图。
图13是示出在该实施例中图12所示的工序后所进行的工序的局部剖面图。
图14是示出在该实施例中图13所示的工序后所进行的工序的局部剖面图。
图15是示出本发明各实施例的半导体器件的一个变例的剖面图。
图16是示出本发明各实施例的半导体器件的另一变例的剖面图。
具体实施方式
实施例1
现说明本发明实施例1的半导体器件的制造方法及用该制造方法制造的半导体器件。
首先，完成在用于在晶片上形成规定的元件及布线等的晶片的状态下应该进行的处理。这时，在晶片中的切割线区域，处于不除去用于形成布线等的导电膜而使之残留的状态。
通过对该晶片进行切割，如图1所示，切出半导体芯片1。如图2所示，半导体芯片1的表面1a被钝化膜8覆盖，在连接焊丝的部分，露出作为所谓键合区的电极部5。
另外，在半导体芯片1的周边部分，残留于切割线部分区域的导电膜存在因切割而卷起的部分(毛刺)7。再有，导电膜是用于形成电极部5及布线(未图示)等的膜。
然后，如图1所示，准备贴附在半导体芯片1上的绝缘性片构件3，以便覆盖半导体芯片1中的规定的部分。作为绝缘性片构件3的材料，可应用树脂类的片构件或橡胶类的片构件。
此时，在绝缘性片构件3上，设置贴附于半导体芯片1的背面1b部分的第1贴附部分3a、贴附于半导体芯片1的侧面部分的第2贴附部分3b、贴附在位于沿半导体芯片1的周边的表面1a部分的第3贴附部分3c。
再有，半导体芯片1的侧面是指因切割晶片而露出的晶片的剖面。
接着，如图1和图2所示，残留第2贴附部分3b、第3贴附部分3c，绝缘性片构件3的第1贴附部分3a被贴附在半导体芯片1的背面1b上。
接着，如图3和图4所示，绝缘性片构件3的第2贴附部分3b被贴附在半导体芯片1的侧面上。接着，如图5和图6所示，绝缘性片构件3的第3贴附部分3c被贴附在位于沿半导体芯片1的周边的表面1a部分。
由此，残存于半导体芯片1的周边部分的卷起了的毛刺7被绝缘性片构件3的第2贴附部分3b和第3贴附部分3c覆盖。
接着，如图7所示，焊丝9与设置在半导体芯片1的表面的电极部5键合，电极部5与规定的引线框架(未图示)电连接。其后，半导体芯片1被密封于规定的封装(未图示)内，完成半导体器件。
用上述半导体器件的制造方法，首先在晶片的切割线区域，在不除去用于形成布线等的导电膜而使之残留的状态下进行切割，切出半导体芯片1。
然后，从半导体芯片1的背面1b一侧将规定的绝缘性片构件3贴附在所切出的半导体芯片1上，位于半导体芯片1的背面、侧面和沿半导体芯片1的周边的表面1a部分被绝缘性片构件3覆盖。
因此，在半导体芯片1的周边，在残存于切割线区域的导电膜因切割而卷起产生毛刺7时，该毛刺7被绝缘性片构件3覆盖。由此，焊丝9被键合到电极部5后，焊丝9与毛刺7就不直接接触了。
其结果是，在半导体器件中，可防止例如一根焊丝与另一根焊丝经毛刺7电联结等的电短路，可提高半导体器件的可靠性。
实施例2
现说明本发明实施例2的半导体器件的制造方法和利用该制造方法制造的半导体器件。
首先，如图8所示，与上述制造方法一样，在晶片的切割线区域，在不除去用于形成布线等的导电膜而使之残留的状态下进行切割，切出半导体芯片1。
然后，如图8所示，准备贴附在半导体芯片1上的绝缘性片构件3，以便覆盖半导体芯片1中的规定部分。作为绝缘性片构件3的材料，可应用树脂类的片构件或橡胶类的片构件，如后面将要述及的，最好利用焊丝键合中的锡焊热使之熔解。
这时，在绝缘性片构件3中，设置了贴附于半导体芯片1的表面1a部分的第1贴附部分3a和贴附于半导体芯片1的侧面部分的第2贴附部分3b。
接着，如图8和图9所示，保留第2贴附部分3b，将绝缘性片构件3的第1贴附部分3a贴附于半导体芯片1的表面1a上。接着，如图10和图11所示，将绝缘性片构件3的第2贴附部分3b贴附于半导体芯片1的侧面上。
由此，残存于半导体芯片1的周边部分的卷起了的毛刺7被绝缘性片构件3的第1贴附部分3a和第2贴附部分3b覆盖。
接着，如图12所示，为了将焊丝9键合到电极部5，焊丝9的前端部分被配置在电极部5的正上方。接着，如图13所示，利用将焊丝9与电极部5锡焊时的热使位于电极部5的正上方的绝缘性片构件3的部分遭到破坏或者被熔解，以此形成开口部12。
接着，如图14所示，通过在绝缘性片构件3上形成的开口部12，将焊丝9键合到电极部5上，电极部5与规定的引线框架(未图示)进行电连接。其后，半导体芯片1被密封于规定的封装(未图示)内，完成半导体器件。
用上述的半导体器件的制造方法与用第1实施例的制造方法一样，在晶片的切割线区域，在不除去用于形成布线等的导电膜而使之残留的状态下进行切割，切出半导体芯片1。
然后，从半导体芯片1的表面1a一侧将规定的绝缘性片构件3贴附在所切出的半导体芯片1上，半导体芯片1的表面和侧面被绝缘性片构件3覆盖。
因此，在半导体芯片1的周边，即使在残存于切割线区域的导电膜因切割而卷起产生毛刺7时，该毛刺7也被绝缘性片构件3覆盖。由此，焊丝9被键合到电极部5后，焊丝9与毛刺7就不直接接触了。
其结果是，在半导体器件中，可防止例如一根焊丝与另一根焊丝经毛刺7电联结等的电短路，可提高半导体器件的可靠性。
可是，近年来伴随便携式装置的发展，对半导体元件(半导体芯片)的封装也在谋求小型化和薄型化。与此相对应，通过对半导体芯片进行研磨处理，减薄半导体芯片的厚度，提出了将该半导体芯片层叠多片的结构。
因此，首先，说明作为一个变例在实施例1中说明过的使贴附了绝缘性片构件的半导体芯片层叠的半导体器件。
如图15所示，在一个变例的半导体器件中，首先，从一个半导体芯片1的背面1b一侧贴附了绝缘性片构件3的一个半导体芯片1被固定在管芯焊区11的表面上。
然后，从另一半导体芯片2的背面2b一侧贴附了绝缘性片构件4的另一半导体芯片2被固定在一个半导体芯片1的表面1a上。
接着，说明作为另一变例在实施例2中说明过的使贴附了绝缘性片构件的半导体芯片层叠的半导体器件。
如图16所示，在另一变例的半导体器件中，首先，从一个半导体芯片1的表面1a一侧贴附了绝缘性片构件3的一个半导体芯片1夹着绝缘性片构件6被固定在管芯焊区11的表面上。
然后，从另一半导体芯片2的表面2a一侧贴附了绝缘性片构件4的另一半导体芯片2被固定在覆盖住一个半导体芯片1的表面1a的绝缘性片构件3上。
这样，在各变例的半导体器件中，通过使磨薄的、分别贴附了绝缘性片构件3、4的半导体芯片1、2层叠起来，可谋求半导体器件的小型化和薄型化。
特别是，在图16所示的另一变例的半导体器件的情况下，为了将一个半导体芯片1固定在管芯焊区11上，必须有多余的绝缘性片构件6，与此相对照，在图15所示的一个变例的半导体器件的情况下，却不需要那样的绝缘性片构件。
其结果是，一个变例的半导体器件与另一变例的半导体器件相比，作为半导体器件，可削减绝缘性片构件的块数。
虽然已详细地说明并揭示了本发明，但这仅仅是例示性的而不是限定性的，可以清楚地理解，发明的要旨和范围仅能靠所附权利要求的范围加以限定。

Claims (8)

1.一种半导体器件，其特征在于，包括：
在半导体衬底的主表面上形成规定的元件和电极部、在切割线区域残留导电膜的状态下进行切割的半导体芯片；
与上述电极部连接的导线；以及
覆盖住沿上述半导体芯片的周边残存的上述导电膜的部分的绝缘性片构件。
2.如权利要求1所述的半导体器件，其特征在于：
上述绝缘性片构件被配置成覆盖住位于上述半导体芯片的背面、上述半导体芯片的侧面和沿上述半导体芯片的周边的表面部分。
3.如权利要求2所述的半导体器件，其特征在于：
包括被上述绝缘性片构件覆盖的多个上述半导体芯片，
多个上述半导体芯片被层叠在一起。
4.如权利要求1所述的半导体器件，其特征在于：
上述绝缘性片构件被配置成覆盖住上述半导体芯片的表面和上述半导体芯片的侧面。
5.如权利要求4所述的半导体器件，其特征在于：
在上述绝缘性片构件中，包括在与上述电极部对应的位置处所形成的开口部，
上述导线通过上述开口部与上述电极部连接。
6.如权利要求5所述的半导体器件，其特征在于：
包括被上述绝缘性片构件覆盖的多个上述半导体芯片，
多个上述半导体芯片被层叠在一起。
7.如权利要求4所述的半导体器件，其特征在于：
包括被上述绝缘性片构件覆盖的多个上述半导体芯片，
多个上述半导体芯片被层叠在一起。
8.如权利要求1所述的半导体器件，其特征在于：
包括被上述绝缘性片构件覆盖的多个上述半导体芯片，
多个上述半导体芯片被层叠在一起。
CNA2003101006384A 2003-02-18 2003-10-10 半导体器件 Pending CN1523645A (zh)

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CN101911294B (zh) * 2008-01-09 2012-07-11 丰田自动车株式会社 半导体装置
CN102903645A (zh) * 2011-07-27 2013-01-30 佳邦科技股份有限公司 平面式半导体元件及其制作方法
CN107256874A (zh) * 2017-07-28 2017-10-17 京东方科技集团股份有限公司 一种基板母板及其制作方法

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US7911045B2 (en) 2007-08-17 2011-03-22 Kabushiki Kaisha Toshiba Semiconductor element and semiconductor device
JP4496241B2 (ja) * 2007-08-17 2010-07-07 株式会社東芝 半導体素子とそれを用いた半導体パッケージ
WO2013069104A1 (ja) * 2011-11-09 2013-05-16 三菱電機株式会社 回転電機

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Publication number Priority date Publication date Assignee Title
CN101911294B (zh) * 2008-01-09 2012-07-11 丰田自动车株式会社 半导体装置
CN102903645A (zh) * 2011-07-27 2013-01-30 佳邦科技股份有限公司 平面式半导体元件及其制作方法
CN102903645B (zh) * 2011-07-27 2015-04-22 佳邦科技股份有限公司 平面式半导体元件及其制作方法
CN107256874A (zh) * 2017-07-28 2017-10-17 京东方科技集团股份有限公司 一种基板母板及其制作方法

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