CN1507239A - E2 interface device and method for synchronous digital transmission system - Google Patents
E2 interface device and method for synchronous digital transmission system Download PDFInfo
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Abstract
The present invention relates to the interface device and method for realizing the transmission of E2 service in SDH synchronous digital transmission network. The device includes microprocessor control circuit, E2 receiving port circuit, multiplexing and demultiplexing circuit, PLL circuit, loop back control circuit, mapping and demapping circuit and E2 transmitting port circuit. The present invention makes available E2 interface device directly accessible when the communication network is upgraded to digital transmission and provides united dispatching, management and monitoring to partial E2 service based on united network management of SDH platform. The loop back function in the line side makes the E2 service flexible in networking and ensures the integrality of E2 service in transmission and the transparency of the transmission passage.
Description
Technical field
The present invention relates to be used for the E2 interface of SDH (Synchronous Digital Hierarchy) (SDH), E2 (8.448Mbit/s) more particularly is provided in the SDH system apparatus and method of interface.
Background technology
The SDH optical transmission device has obtained in the communications field using very widely at present, substituted original PDH (Pseudo-synchronous Digital Hierarchy) (PDH) equipment substantially fully on transport layer, but the PDH interface is seen often still on Access Layer, as interfaces such as E1, E3, T1, T3.So for compatible PDH equipment, International Telecommunication Association (ITU-T) has defined the standard of PDH business multiplexing and mapping in SDH equipment, i.e. standard G.707, but only defined T1 (15544kbit/s) in this standard, E1 (2048kbit/s), T2 (6312kbit/s), E3 (34368kbit/s), T3 (44736kbit/s), the mapping path of E4 PDH business such as (139264kbit/s), do not define the professional mapping path of E2 (8448kbit/s), do not specify the virtual container that to adorn the E2 business yet, caused the E2 business on present SDH equipment, directly to use like this.And the conduct of E2 interface is a kind of PDH interface, at present at army's net, dedicated network and ATM such as electrical network, still have certain applications in the equipment such as wireless access, therefore when these private wore networks and equipment carry out digital improvement, this part E2 interface can't directly be linked in the SDH equipment, must change by extra equipment and just may be linked in the SDH equipment, so both increased improvement cost, again because of using unified webmaster to manage, also increased maintenance cost virtually, also dumb in the networking configuration, also may destroy professional integrality simultaneously because guaranteeing the transparent transmission of E2 business.So in order to prolong the useful life of this part equipment, reduce and transform and maintenance cost, the requirement that the continuation of E2 interface equipment is used in synchronous digital transmission system has been proposed, and each communications equipment vendor current SDH synchronous digital transmission network system all can not provide this class interface at present, and patent retrieval also fails to retrieve corresponding invention and device.
Summary of the invention
Purpose of the present invention in order to overcome the shortcoming that existing E2 interface equipment can not directly insert when communication network upgrades to Digital Transmission, proposes interface arrangement and method that a kind of E2 business is transmitted just in the SDH synchronous digital transmission network.In the SDH synchronous digital transmission network, provide a transparent transmission channel for the E2 business.
The present invention is achieved in that
The described E2 interface arrangement that is used for synchronous digital transmission system comprises: microprocessor control circuit, E2 receive interface circuit, multiplexing and demultiplexing circuit, phase-locked loop circuit, loopback control circuit, mapping circuit is separated in mapping and E2 sends out interface circuit.
Microprocessor control circuit: receive the time slot up and down of the command configuration E2 business of webmaster maintenance terminal, and according to time slot and networking requirement are carried out loopback at the line side control to each E2 business up and down; This circuit also monitors the running status of whole device and this device is reported the webmaster maintenance terminal about information such as alarm and performances simultaneously;
E2 receives interface circuit: finish professional isolation and the 75 Ω impedance matchings of receiving interface of E2, and high density bipolar (HDB3) sign indicating number of line interface E2 business is converted to the unipolar code of double track, export to the loopback control circuit at last;
The multiplexing and demultiplexing circuit: the debit of this circuit is to the double track unipolar code data that receive the output of loopback control circuit, therefrom recover the line clock of 8.448MHz and decode, converting NRZ (NRZ sign indicating number) to, is 1 road E3 (34368kbit/s) signal with 4 tunnel E2 signal multiplexing again; Originating party is to being 4 road E2 signals with 1 tunnel E3 (34368kbit/s) signal demultiplexing then, and 4 road E2 signals are carried out HDB3 encode, the clock that provides according to phase-locked loop circuit is sent the E2 signal of 4 road HDB3 coding to E2 in the double track mode respectively and is sent out interface circuit then;
Phase-locked loop circuit: this circuit cooperates the multiplexing and demultiplexing circuit working, the identified result that provides according to the multiplexing and demultiplexing circuit is adjusted the output frequency of self, make it approaching with the clock that the multiplexing and demultiplexing circuit needs as far as possible, thereby the E2 signal of level and smooth multiplexing and demultiplexing circuit output, guarantee the operate as normal of multiplexing and demultiplexing circuit, prevent that the interior data buffering from overflowing;
The loopback control circuit: this circuit receives the configuration of microprocessor control circuit, each road E2 signal to transmitting-receiving carries out selectable loopback control, control types comprises loopback at the line side and end side loopback, the end side loopback uses when wherein can be used for diagnostic operation, loopback at the line side then both can be used for diagnostic operation, also can when ring network, finish the bandwidth sharing function of a plurality of website E2 business, prevent the professional situation that must bundle transmission of a plurality of E2;
Mapping circuit is separated in mapping: this circuit is finished the function of E3 signal map in the VC-4 virtual container, and mapping path meets G.707 standard: E3 → C3 → VC-3 → TU-3 → TUG-3 → VC-4, externally can provide system-side interface; This circuit is also finished the VC-4 signal and is separated the function that is mapped to the E3 signal simultaneously, and it is opposite with mapping path to separate mapping path;
E2 sends out interface circuit: this circuit is finished driving, isolation and the impedance matching of transmitter side E2 signal, and changes the unipolar code of double track into bipolarity HDB3 sign indicating number.
A kind of E2 interface method that is used for synchronous digital transmission system may further comprise the steps:
By microprocessor control circuit hardware components is detected, as find that certain hardware circuit has abnormal operating state, then send alarm, remind the user to change;
Pass through as self check, then by serial ports information such as this board type, version are reported the webmaster maintenance terminal by microprocessor control circuit, and the request configuration;
The webmaster maintenance terminal receives the veneer request, issue the time slot configuration order according to user's setting, finish command interpretation by microprocessor control circuit, and each hardware circuit carried out corresponding control: opening needs the E2 port that uses, the untapped E2 port of loopback at the line side and mapping is set separates the employed VC-3 timeslot number of mapping circuit;
Configuration finishes, beginning operate as normal, detection and report and alarm and performance.
Adopt device of the present invention can allow the PDH equipment of original use E2 interface continue in the synchronous digital hierarchy transport system, to use, thus the upgrading expense of having saved the telex network network; And provide unified webmaster that this part E2 business is carried out unified scheduling, management and monitoring based on the SDH platform; The loopback at the line side function that this device provided can make this part E2 business more flexible aspect networking, prevents the situation that a plurality of E2 business must bundle transmission; This device has also guaranteed the integrality in the professional transmission course of E2 and the transparency of transmission channel, and promptly through professional just the same with the source end of the destination E2 after this device transmission, the overhead-bits of the professional inside of E2 does not have any variation yet.
Description of drawings
Fig. 1 is the theory diagram of this device.
Service configuration method when Fig. 2 is the networking of this device.
Fig. 3 is this device workflow diagram.
Embodiment
Below in conjunction with accompanying drawing technical solutions according to the invention are done further detailed description:
The theory diagram of apparatus of the present invention comprises as shown in Figure 1:
Microprocessor control circuit 1: with 8031 Single Chip Microcomputer (SCM) system is the control circuit core, communicate by letter with the webmaster maintenance terminal by serial ports, obtain this device configuration information, and this configuration information is resolved, resolve into the configuration information of each unit module, thereby each element circuit is controlled respectively; Monitor the working condition of each element circuit simultaneously, add up various alarms and performance count, report the webmaster maintenance terminal;
E2 receives interface circuit 2: adopt transformer T1006 and resistor network to finish the function of professional isolation and 75 Ω impedance matchings, use thick film circuit HM9324 to finish the function that bipolarity HDB3 sign indicating number converts unipolar code to, the line data of going forward side by side regeneration.The E2 business of outside input will be converted the back by this circuit and become the unipolar signal of double track to export to the loopback control circuit;
Multiplexing and demultiplexing circuit 3: adopt PDH E1/E2/E3 multiplexing and demultiplexing chip GW7600 to finish this circuit function, mainly comprise: functions such as the multiplexing and demultiplexing of the HDB3 encoding and decoding of the E2 signal of double track unipolar code, the Clock Extraction of E2 signal, the output of 8.448MHz clock phase discrimination, 4 road E2 signals and 1 road E3 signal and loss of signal alarm detection.This circuit receives the E2 signal of 4 road double track unipolarities coding of loopback control circuit output, it is carried out Clock Extraction, 8.448MHz clock in promptly from the E2 signal of HDB3 coding, recovering, carry out the decoding of HDB3 again, recover E2 data wherein, at last the E2 data of 4 road NRZ are carried out multiplexingly, be multiplexed with the E3 signal of the NRZ sign indicating number of one road 34.368Mbit/s, output it to mapping and separate mapping circuit; This circuit receives the E3 signal that the NRZ sign indicating number of mapping circuit output is separated in mapping simultaneously, with this E3 signal demultiplexing E2 signal that is 4 road 8.448Mbit/s, the clock of each E2 signal is controlled by phase-locked loop circuit separately, last this circuit carries out the coding of HDB3 to these E2 signals, and it is exported to the loopback control circuit in the double track mode;
Phase-locked loop circuit 4: this circuit utilizes the low pass filter of a second order and the phase-locked function that VCXO is finished 8.448MHz.The phase discriminating pulse that circuit is exported the phase discriminator of multiplexing and demultiplexing circuit earlier is input to low pass filter and carries out filtering, phase discriminating pulse is filtered into a relatively stable level signal, control the VCXO of a 8.448MHz again by this level signal, make it export adjusted E2 clock and give the multiplexing and demultiplexing circuit, phase discriminator in the multiplexing and demultiplexing circuit will carry out phase demodulation once more to adjusted 8.448MHz clock, and export phase discriminating pulse adjustment once more, so go round and begin again, guaranteed that the clock of phase-locked loop circuit output is consistent with the 8.448MHz clock that the multiplexing and demultiplexing circuit needs basically;
Loopback control circuit 5: this circuit utilizes a slice field programmable logic array (FPGA) to realize the loop fuction of all E2 signals, comprises loopback at the line side and end side loopback.This circuit receives the configuration of microprocessor control circuit, every road E2 signal all there are two control registers, the control circuit side ring returns and the end side loopback respectively, when the loopback at the line side control register is 1, the input that FPGA gives the multiplexing and demultiplexing circuit with the E2 signal loopback of multiplexing and demultiplexing circuit output, realize the loopback at the line side function, send out interface circuit, realize E2 business function under the normal SDH otherwise the E2 signal that FPGA exports the multiplexing and demultiplexing circuit directly sends to E2; And when end side loopback control register is 1, FPGA sends out interface circuit with the E2 signal loopback that E2 receives interface circuit output to E2, realize the end side loop fuction, otherwise the E2 signal that FPGA receives interface circuit output with E2 directly sends to the input of multiplexing and demultiplexing circuit, realizes that normal E2 goes up the SDH business function;
Mapping circuit 6 is separated in mapping: adopt single channel E3 mapping chip TXC03452 to realize this partial circuit function, mapping function is separated in the mapping of finishing between one road E3 signal and VC-4 virtual container, and carries out the relevant Loss Of Pointer (LOP) of SDH, alarm indication signal (AIS), remote defect indication (rdi), unloaded (UNEQ), Payload mismatch (PLM) and wait and alarm and the monitoring of Background Block Error (BBE), far end block error performances such as (FEBE).This circuit receives the E3 signal and the clock of the NRZ sign indicating number of multiplexing and demultiplexing circuit output earlier, to its fill, processing such as mapping, by E3 → C3 → VC-3 → TU-3 → TUG-3 → VC-4 shine upon multiplexing path with single channel E3 signal map in the VC-4 virtual container, concrete VC-3 timeslot number is specified by microprocessor control circuit, and then the last bus (ADD bus) that this VC-4 signal outputs to system side is gone up further handled by other module of system; VC-4 under while this circuit receiving system side on the bus (DROP bus), map out the E3 signal by therefrom separating with the opposite path of mapping, concrete VC-3 time slot is also specified by microprocessor control circuit, then this E3 signal and clock is exported to the multiplexing and demultiplexing circuit;
E2 sends out interface circuit 7: this circuit is made up of transformer T1006, resistor network and 74HC04, and transformer is finished isolation features, and 74HC04 finishes the driving function, and resistor network then realizes sending out the impedance matching function of interface.This circuit receives the E2 signal of the double track unipolarity coding of loopback control circuit output, exports to T1006 after driving by 74HC04, sends to 75 Ω copper spindle noses at last, and the E2 business interface of standard is provided.
Website A respectively has one road E2 business to communicate with website B, C, D respectively among Fig. 2, and website D also has one road E2 business to communicate with website E.This device automatically to not carrying out loopback at the line side in this website E2 business up and down, has been finished above-mentioned networking requirement by microprocessor control circuit and loopback control circuit; Defencive function is then realized by the multiplex section protection that the SDH system provides on the ring of E2 business, reaches the guard time of 50mS;
E2 interface arrangement workflow of the present invention is described as follows:
1, at first detects, as find that certain hardware circuit has abnormal operating state, then send alarm, remind the user to change by the hardware components of microprocessor control circuit to this device;
2, pass through as self check, then by serial ports information such as this board type, version are reported the webmaster maintenance terminal by microprocessor control circuit, and the request configuration;
3, the webmaster maintenance terminal receives the veneer request, issue the time slot configuration order according to user's setting, the microprocessor control circuit of this device is finished command interpretation, and each hardware circuit carried out corresponding control: open this device and need the E2 port that uses, loopback at the line side originally installs untapped E2 port and mapping is set separates the employed VC-3 timeslot number of mapping circuit;
4, configuration finishes, this device beginning operate as normal, detection and report and alarm and performance.
Claims (13)
1 one kinds of E2 interface arrangements that are used for synchronous digital transmission system, it is characterized in that: this device comprises: microprocessor control circuit, E2 receive interface circuit, multiplexing and demultiplexing circuit, phase-locked loop circuit, loopback control circuit, mapping circuit is separated in mapping and E2 sends out interface circuit;
Described microprocessor control circuit is used to receive the time slot up and down of the command configuration E2 business of webmaster maintenance terminal, and according to time slot and networking requirement are carried out loopback at the line side control to each E2 business up and down;
Described E2 receives interface circuit, is used to finish professional isolation and the 75 Ω impedance matchings of receiving interface of E2, and high density bipolar (HDB3) sign indicating number of line interface E2 business is converted to the unipolar code of double track, exports to the loopback control circuit at last;
Described multiplexing and demultiplexing circuit, the debit of this circuit is to the double track unipolar code data that receive the output of loopback control circuit, therefrom recover the line clock of 8.448MHz and decode, convert NRZ (NRZ sign indicating number) to, be 1 road E3 (34368kbit/s) signal with 4 tunnel E2 signal multiplexing again, the originating party of this circuit is to being 4 road E2 signals with 1 tunnel E3 (34368kbit/s) signal demultiplexing then, and 4 road E2 signals are carried out HDB3 encode, the clock that provides according to phase-locked loop circuit is sent the E2 signal of 4 road HDB3 coding to E2 in the double track mode respectively and is sent out interface circuit then;
Described phase-locked loop circuit, this circuit cooperates the multiplexing and demultiplexing circuit working, the identified result that provides according to the multiplexing and demultiplexing circuit is adjusted the output frequency of self, make it approaching with the clock that the multiplexing and demultiplexing circuit needs as far as possible, thereby the E2 signal of level and smooth multiplexing and demultiplexing circuit output, guarantee the operate as normal of multiplexing and demultiplexing circuit, prevent that the interior data buffering from overflowing;
Described loopback control circuit, this circuit receives the configuration of microprocessor control circuit, and each road E2 signal of receiving and dispatching is carried out selectable loopback control, comprises loopback at the line side and end side loopback;
Mapping circuit is separated in described mapping, and this circuit is finished the function of E3 signal map in the VC-4 virtual container, and mapping path meets G.707 standard: E3 → C3 → VC-3 → TU-3 → TUG-3 → VC-4, externally can provide system-side interface;
Described E2 sends out interface circuit, and this circuit is finished driving, isolation and the impedance matching of transmitter side E2 signal, and changes the unipolar code of double track into bipolarity HDB3 sign indicating number.
2 are used for the E2 interface arrangement of synchronous digital transmission system according to claim 1, it is characterized in that described microprocessor control circuit, are used to monitor the running status of whole device and will report the webmaster maintenance terminal about information such as alarm and performances.
3 are used for the E2 interface arrangement of synchronous digital transmission system according to claim 1, and the end side loopback that it is characterized in that described loopback control circuit uses when can be used for diagnostic operation;
Loopback at the line side then both can be used for diagnostic operation, also can finish the bandwidth sharing function of a plurality of website E2 business when ring network, prevented the professional situation that must bundle transmission of a plurality of E2.
4 are used for the E2 interface arrangement of synchronous digital transmission system according to claim 1, it is characterized in that described mapping separates mapping circuit, are used to finish the VC-4 signal and separate the function that is mapped to the E3 signal, and it is opposite with mapping path to separate mapping path.
5 are used for the E2 interface arrangement of synchronous digital transmission system according to claim 1, it is characterized in that described microprocessor control circuit, adopt 8031 Single Chip Microcomputer (SCM) system, communicate by letter with the webmaster maintenance terminal by serial ports, obtain configuration information, and this configuration information resolved, resolve into the configuration information of each unit module, thereby each element circuit is controlled respectively.
6 are used for the E2 interface arrangement of synchronous digital transmission system according to claim 1, it is characterized in that described microprocessor control circuit, monitor the working condition of each element circuit, add up various alarms and performance count, report the webmaster maintenance terminal.
7 are used for the E2 interface arrangement of synchronous digital transmission system according to claim 1, it is characterized in that described E2 receives interface circuit, adopt transformer T1006 and resistor network to finish professional the isolation and 75 Ω impedance matchings;
Use thick film circuit HM9324 to finish bipolarity HDB3 sign indicating number and convert unipolar code to, the line data of going forward side by side regeneration;
Become the unipolar signal of double track to export to the loopback control circuit the professional conversion of the E2 of outside input back.
8 are used for the E2 interface arrangement of synchronous digital transmission system according to claim 1, it is characterized in that described multiplexing and demultiplexing circuit, adopt PDH E1/E2/E3 multiplexing and demultiplexing chip GW7600, comprising: the multiplexing and demultiplexing and the loss of signal alarm of the HDB3 encoding and decoding of the E2 signal of double track unipolar code, the Clock Extraction of E2 signal, the output of 8.448MHz clock phase discrimination, 4 road E2 signals and 1 road E3 signal detect;
Receive the E2 signal of 4 road double track unipolarities coding of loopback control circuit output, it is carried out Clock Extraction, 8.448MHz clock in promptly from the E2 signal of HDB3 coding, recovering, carry out the decoding of HDB3 again, recover E2 data wherein, at last the E2 data of 4 road NRZ are carried out multiplexingly, be multiplexed with the E3 signal of the NRZ sign indicating number of one road 34.368Mbit/s, output it to mapping and separate mapping circuit;
The E3 signal demultiplexing of the mapping that receives being separated the NRZ sign indicating number of mapping circuit output is the E2 signal of 4 road 8.448Mbit/s, the clock of each E2 signal is controlled by phase-locked loop circuit separately, these E2 signals are carried out the coding of HDB3, and it is exported to the loopback control circuit in the double track mode.
9 are used for the E2 interface arrangement of synchronous digital transmission system according to claim 1, it is characterized in that described phase-locked loop circuit, utilize the low pass filter of a second order and a VCXO to finish the phase-locked of 8.448MHz;
The phase discriminating pulse that circuit is exported the phase discriminator of multiplexing and demultiplexing circuit earlier is input to low pass filter and carries out filtering, phase discriminating pulse is filtered into a relatively stable level signal, control the VCXO of a 8.448MHz again by this level signal, make it export adjusted E2 clock and give the multiplexing and demultiplexing circuit, phase discriminator in the multiplexing and demultiplexing circuit will carry out phase demodulation once more to adjusted 8.448MHz clock, and export phase discriminating pulse adjustment once more, so go round and begin again, guaranteed that the clock of phase-locked loop circuit output is consistent with the 8.448MHz clock that the multiplexing and demultiplexing circuit needs basically.
10 are used for the E2 interface arrangement of synchronous digital transmission system according to claim 1, it is characterized in that described loopback control circuit, adopt field programmable logic array (FPGA) to realize the loopback of all E2 signals, comprise loopback at the line side and end side loopback;
Receive the configuration of microprocessor control circuit, every road E2 signal is all had two control registers, the control circuit side ring returns and the end side loopback respectively;
When the loopback at the line side control register is 1, the input that FPGA gives the multiplexing and demultiplexing circuit with the E2 signal loopback of multiplexing and demultiplexing circuit output, realize loopback at the line side, otherwise the E2 signal that FPGA exports the multiplexing and demultiplexing circuit directly sends to E2 and sends out interface circuit, realizes E2 business under the normal SDH (Synchronous Digital Hierarchy);
And when end side loopback control register is 1, FPGA sends out interface circuit with the E2 signal loopback that E2 receives interface circuit output to E2, realize the end side loopback, otherwise the E2 signal that FPGA receives interface circuit output with E2 directly sends to the input of multiplexing and demultiplexing circuit, realizes that normal E2 goes up service of synchronous digital system.
11 are used for the E2 interface arrangement of synchronous digital transmission system according to claim 1, it is characterized in that described mapping separates mapping circuit, adopt single channel E3 mapping chip TXC03452 to realize, mapping is separated in the mapping of finishing between one road E3 signal and MC-4 virtual container, and carries out the relevant Loss Of Pointer (LOP) of SDH, alarm indication signal (AIS), remote defect indication (rdi), unloaded (UNEQ), Payload mismatch (PLM) and wait and alarm and the monitoring of Background Block Error (BBE), far end block error performances such as (FEBE);
Receive the E3 signal and the clock of the NRZ sign indicating number of multiplexing and demultiplexing circuit output earlier, to its fill, processing such as mapping, by E3 → C3 → VC-3 → TU-3 → TUG-3 → VC-4 shine upon multiplexing path with single channel E3 signal map in the VC-4 virtual container, concrete VC-3 timeslot number is specified by microprocessor control circuit, and then the last bus (ADD bus) that this VC-4 signal outputs to system side is gone up further handled by other module of system;
The VC-4 on the bus (DROP bus) under the receiving system side simultaneously therefrom separates by the path opposite with mapping and to map out the E3 signal, and concrete VC-3 time slot is also specified by microprocessor control circuit, then this E3 signal and clock is exported to the multiplexing and demultiplexing circuit.
12 are used for the E2 interface arrangement of synchronous digital transmission system according to claim 1, it is characterized in that described E2 sends out interface circuit, form that transformer is finished isolation by transformer T1006, resistor network and 74HC04,74HC04 finishes driving, and resistor network then realizes sending out the impedance matching of interface;
Receive the E2 signal of the double track unipolarity coding of loopback control circuit output, export to T1006 after driving by 74HC04, send to 75 Ω copper spindle noses at last, the E2 business interface of standard is provided.
13 are used for the E2 interface method of synchronous digital transmission system according to claim 1, may further comprise the steps:
By microprocessor control circuit hardware components is detected, as find that certain hardware circuit has abnormal operating state, then send alarm, remind the user to change;
Pass through as self check, then by serial ports information such as this board type, version are reported the webmaster maintenance terminal by microprocessor control circuit, and the request configuration;
The webmaster maintenance terminal receives the veneer request, issue the time slot configuration order according to user's setting, finish command interpretation by microprocessor control circuit, and each hardware circuit carried out corresponding control: opening needs the E2 port that uses, the untapped E2 port of loopback at the line side and mapping is set separates the employed VC-3 timeslot number of mapping circuit;
Configuration finishes, beginning operate as normal, detection and report and alarm and performance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021551294A CN100393074C (en) | 2002-12-10 | 2002-12-10 | E2 interface device and method for synchronous digital transmission system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021551294A CN100393074C (en) | 2002-12-10 | 2002-12-10 | E2 interface device and method for synchronous digital transmission system |
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| Publication Number | Publication Date |
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| CN1507239A true CN1507239A (en) | 2004-06-23 |
| CN100393074C CN100393074C (en) | 2008-06-04 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB021551294A Expired - Fee Related CN100393074C (en) | 2002-12-10 | 2002-12-10 | E2 interface device and method for synchronous digital transmission system |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010148589A1 (en) * | 2009-06-24 | 2010-12-29 | 中兴通讯股份有限公司 | Apparatus and method for locating fault points in a transmission network |
| CN105356995A (en) * | 2015-11-24 | 2016-02-24 | 山东胜开电子科技有限公司 | Synchronous code bidirectional restoration method and circuit |
| WO2018058352A1 (en) * | 2016-09-28 | 2018-04-05 | Qualcomm Incorporated | Sub-channel mapping |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09331555A (en) * | 1996-06-10 | 1997-12-22 | Fujitsu Ltd | Transmitter |
| CN1097932C (en) * | 1997-12-31 | 2003-01-01 | 华为技术有限公司 | System communication control device for synchronous digit transferring arrangement |
-
2002
- 2002-12-10 CN CNB021551294A patent/CN100393074C/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010148589A1 (en) * | 2009-06-24 | 2010-12-29 | 中兴通讯股份有限公司 | Apparatus and method for locating fault points in a transmission network |
| CN105356995A (en) * | 2015-11-24 | 2016-02-24 | 山东胜开电子科技有限公司 | Synchronous code bidirectional restoration method and circuit |
| CN105356995B (en) * | 2015-11-24 | 2018-06-26 | 山东胜开电子科技有限公司 | A kind of two-way restoration methods of synchronous code and circuit |
| WO2018058352A1 (en) * | 2016-09-28 | 2018-04-05 | Qualcomm Incorporated | Sub-channel mapping |
| US11259280B2 (en) | 2016-09-28 | 2022-02-22 | Qualcomm Incorporated | Sub-channel mapping |
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| Publication number | Publication date |
|---|---|
| CN100393074C (en) | 2008-06-04 |
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