CN1505266A - Signal synchronization method and circuit - Google Patents
Signal synchronization method and circuit Download PDFInfo
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- CN1505266A CN1505266A CNA021538840A CN02153884A CN1505266A CN 1505266 A CN1505266 A CN 1505266A CN A021538840 A CNA021538840 A CN A021538840A CN 02153884 A CN02153884 A CN 02153884A CN 1505266 A CN1505266 A CN 1505266A
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Abstract
The invention discloses a method to synchronize two signals triggered by different frequency clock pulses. At higher frequency time sequence, both positive and negative edges of the signal sample lower frequency enabled write signal. If the sampling result of the positive or negative edge is 1, then record its sampling action state as locking state and does not sample the next reverse edge. If the sampling result is 0, then record its sampling action state as sampling state and sample the next reverse edge. Finally, collect all the sampling results to output a synchronized enabled write signal. The invention also discloses a corresponding synchronizing circuit.
Description
Technical field
The present invention relates to a kind of signal synchronizing method and circuit thereof.The invention particularly relates to a kind of synchronous two method and circuit thereof with the signal of the clock pulse triggering of different frequency.
Background technology
Along with the integrated circuit (IC) design complexity improves, more and more many people utilize electric design automation (electron design automation, EDA) aid assists the designer in design process, find the integrality of disappearance place and analysis and optimization processing test sample book ahead of time, reduce test time-histories waste unnecessary or unnecessary, to shorten the time-histories of exploitation.The circuit design of the signal that the same frequency clock pulse triggers can and analyze reliable result via this class aid emulation at an easy rate.
Yet the designer still must be in the face of the sequence problem that signal produced of different frequency clock pulse triggering.For example, (for reaching certain usefulness, its exclusive circuit adopts the clock pulse of upper frequency to the high-order Reduced Instruction Set Computing of camera use 48Mhz, as 100Mhz for Advanced RISCMachine, ARM) processor.But the input signal of transducer is with 13.5 or the 27Mhz Synchronous Processing, and its corresponding circuit then adopts the clock pulse of 27Mhz.And the result that this class sequence problem goes out with the aid simulation analysis of EDA and unreliable.
As shown in Figure 1a, first module 11 operates with the lower frequency clock pulse, and allows to write (write enable) signal WE with lower frequency clock signal LCK processing, with data transmission to the second module 12 in first buffer 111.Second module 12 allows write signal WE receiving the data that first module 11 is transmitted with the sampling of the clock pulse of upper frequency clock signal HCK, and deposits second buffer 121 in second module 12 in.When allowing write signal WE to be positioned at high potential, when being 1 state, second module 12 can receive the data that first module 11 sends and deposit in second buffer 121.Allow the sequential chart of write signal WE and upper frequency clock signal HCK among Fig. 1 b displayed map 1a, second module 12 is the permission write signal WE of sampling in 1 o'clock without Synchronous Processing in clock pulse.When Fig. 1 b position a,, therefore may miss current permission write signal WE because second module 12 needs the permission write signal WE of time enough to confirm to be sampled to.When the b of position, could successfully read the permission write signal, and the permission data writes.In the face of the sequence problem of this class different frequency clock pulse, the designer must spend many times and check one by one and export the result and finely tune, to meet its expected result.In addition, because of the influence of factors such as circuit design change or process reform, the designer must check and finely tune its circuit design once more, thereby prolongs the time-histories of development and Design.
Therefore how the circuit module that synchronous two different frequencies trigger solves above-mentioned sequence problem, and the analysis result of EDA aid can be trusted, and just becomes with the time-histories that shortens exploitation and demands the problem improved at present urgently.
Summary of the invention
At the problems referred to above, purpose of the present invention is for providing a kind of synchronous two method and circuit thereof with the signal of the clock pulse triggering of different frequency, it can solve two sequence problems that signal was produced that trigger with the clock pulse of different frequency, make time that circuit designers do not need overspending on sequence problem, to shorten the exploitation time-histories of circuit design.
Another object of the present invention is for providing a kind of synchronous two method and circuit thereof with the signal of the clock pulse triggering of different frequency, and it can make electric design automation, and (electron designautomation, EDA) the simulation analysis result of aid can be trusted.
For achieving the above object, synchronous two methods with the signal of the clock pulse triggering of different frequency of the present invention are that positive edge (positive edge) and the negative edge (negativeedge) at the upper frequency clock signal all allows write signal to take a sample to lower frequency.If sampling result is an electronegative potential when positive edge, be 0 o'clock, carry out primary sample again at next negative edge.If the sampling result at negative edge is a high potential, be 1 o'clock, then next positive edge is not promptly taken a sample.That is be 1 o'clock at the sampling result of positive edge of upper frequency clock signal or negative edge, next opposite edge is not taken a sample.If the sampling result at positive edge or negative edge is 0, next opposite edge is then taken a sample.At last, will allow write signal synchronously in the sampling result connection collection output one of positive edge and negative edge.
In addition, comprise according to above-mentioned synchronous two enforcement circuit: a writing circuit and a sample circuit with the method for the signal of the clock pulse triggering of different frequency.Writing circuit reaches the state that negative edge should carry out sampling action in order to the positive edge that is recorded in the upper frequency clock signal.Sample circuit then is the sampling action state according to the writing circuit record, makes corresponding sampling action at opposite edge, and will allow write signal synchronously in the sampling result connection collection output of positive edge and negative edge.
Writing circuit comprises one the one D type flip-flop and one the 2nd D type flip-flop, and both all are positive edge flip-over types.The one D type flip-flop is in order to write down the sampling action state after positive edge is taken a sample, and the 2nd D type flip-flop then is the sampling action state after the negative edge sampling of record.Sample circuit then comprise one first with door, one the 3rd D type flip-flop, one second with door, one the 4th D type flip-flop, one or and one the 5th D type flip-flop.The 3rd D type flip-flop, the 4th D type flip-flop and the 5th D type flip-flop are positive edge flip-over type.First imports three D type flip-flop and four D type flip-flop with door in order to control lower frequency permission write signal with door and second.The 3rd D type flip-flop and the 4th D type flip-flop then are in order at negative edge and positive edge lower frequency is allowed the write signal sampling.When a D type flip-flop and the 2nd D type flip-flop recording status were lock-out state, first was output as 0 with door and second with door, represents the 3rd D type flip-flop and the 4th D type flip-flop to take a sample, and exporting the result also is 0.When a D type flip-flop and the 2nd D type flip-flop recording status were the sampling state, first then changed along with lower frequency allows write signal with the output of door with door and second, and by the 3rd D type flip-flop and the sampling of the 4th D type flip-flop and export the result.Afterwards again with or couplet on the door collection output become one at the sampling result of positive edge and negative edge and allow write signal synchronously.The 5th D type flip-flop is then controlled and is allowed the positive edge conversion of write signal at the upper frequency clock signal synchronously.The upper frequency module can be taken a sample when the positive edge of upper frequency clock signal and be allowed write signal to handle the data that the lower frequency module is imported into synchronously.
According to synchronous two method and circuit thereof with the signal of the clock pulse triggering of different frequency of the present invention, the lower frequency that first module can be produced allows the upper frequency clock signal of the write signal and second module to produce one through Synchronous Processing and allows write signal synchronously.Subsequently, second module triggers and receives the data that first module sends to allow write signal synchronously.So, two modules of lower frequency and upper frequency can be considered synchronous module, and aid that promptly can EDA assists designer's simulation analysis to go out reliable result, to shorten the time-histories of development and Design.
Description of drawings
Fig. 1 a is that the intermodular data that the clock pulse of an existing different frequency triggers transmits schematic diagram.
Fig. 1 b is the sequential chart that the lower frequency of Fig. 1 a allows write signal and upper frequency clock signal.
The schematic diagram that Fig. 2 intermodular data that to be the method for synchronous two signals that trigger with the clock pulse of different frequency of utilization preferred embodiment of the present invention and circuit thereof trigger in the clock pulse of different frequency transmits.
Fig. 3 is a flow chart, shows synchronous two implementation steps with the method for the signal of the clock pulse triggering of different frequency according to preferred embodiment of the present invention.
Fig. 4 a shows synchronous two circuit with the signal of the clock pulse triggering of different frequency according to preferred embodiment of the present invention.
The sequential chart of the correspondence of circuit shown in Fig. 4 b displayed map 4a.
The figure number explanation:
11 first modules, 111 first buffers
12 second modules, 121 second buffers
23 synchronous circuits 24 the 3rd buffer
41 writing circuits 411 a D type flip-flop
412 the 2nd D type flip-flops, 42 sample circuits
421 first with the door 422 second with the door
423 the 3rd D type flip-flops 424 the 4th D type flip-flop
425 or the door 426 the 5th D type flip-flops
HCK upper frequency clock signal LCK lower frequency clock signal
The sampling action state of the negative edge of Lock lock-out state Nstate
The sampling action state WE of the positive edge of Pstate allows write signal
Sampling sampling state SWE allows write signal synchronously
S31～S34 synchronous two method steps of the present invention with the signal of the clock pulse triggering of different frequency
Embodiment
Hereinafter with reference to relevant drawings, synchronous two method and circuit thereof with the signal of the clock pulse triggering of different frequency according to preferred embodiment of the present invention are described, wherein components identical will be with identical being illustrated with reference to figure number.
Please refer to Fig. 2, a synchronous circuit 23 is set in first module 11 and 12 of second modules.Utilize synchronous circuit 23 with the permission write signal WE of first module 11 output with upper frequency clock signal HCK synchronization after, output allows write signal SWE synchronously.Second module 12 allows write signal SWE to receive the data that first module 11 is transmitted with upper frequency clock signal HCK sampling more synchronously, and is temporary in second buffer 121.So can solve the sequence problem of above-mentioned known techniques.Below will describe synchronous two methods in detail with the signal of the clock pulse triggering of different frequency.
According to the methods of synchronous two signals that trigger with the clock pulse of different frequency of the embodiment of the invention, the action of its spirit for all the permission write signal WE of lower frequency being taken a sample when the positive edge (positive edge) of upper frequency clock signal HCK and the negative edge (negative edge).Please refer to Fig. 3 implementation step is described.Allow the sampling action of write signal WE to divide into two kinds to lower frequency when the positive edge of upper frequency clock signal HCK and negative edge: a kind of is that permission write signal to lower frequency carries out sampling action (hereinafter referred to as the sampling state), another kind is a lock-out state, does not promptly take a sample.At first the sampling action when positive edge of upper frequency clock signal HCK and negative edge is initialized as sampling state (S31).When being initial condition, all can allow write signal WE to take a sample to lower frequency at the positive edge of upper frequency clock signal and negative edge.Then,, allow write signal WE to take a sample at positive edge and negative edge to lower frequency respectively, and be recorded in the positive edge of upper frequency clock signal HCK and the sampling action state (S32) of negative edge along with the conversion of positive edge of upper frequency clock signal HCK and negative edge.Carry out corresponding sampling action (S33) according to the positive edge of record and the sampling action state of negative edge at next opposite edge again.Its foundation that changes the sampling action state is: as if the positive edge at upper frequency clock signal HCK lower frequency being allowed the result of write signal WE sampling is high potential, is 1 state, and the sampling action state that then changes positive edge is a lock-out state.If the sampling result of the positive edge of next time cycle is an electronegative potential, be 0 state, the sampling action state that then changes positive edge is the sampling state.Same, as if the negative edge at upper frequency clock signal HCK lower frequency being allowed the result of write signal WE sampling is 1, the sampling action state that then changes negative edge is a lock-out state.If the negative edge sampling result of next time cycle is 0, the sampling action state that then changes negative edge is the sampling state.Its meaning is, if at the positive edge of upper frequency clock signal HCK, the sampling action state of its previous negative edge is the sampling state, and being illustrated in previous negative edge, lower frequency is allowed the sampling result of write signal WE is 0, must be in present positive edge sampling.If the sampling action state of previous negative edge is a lock-out state, being illustrated in previous negative edge, lower frequency is allowed the sampling result of write signal WE is 1, and the positive edge at place is taken a sample with regard to not needing again at present.In like manner, at present the result that whether takes a sample also by previous positive edge sampling of the negative edge at place decides, and no longer sets forth at this.At last, be output into one and allow write signal SWE (S34) synchronously allowing the result of write signal WE sampling to join collection to lower frequency when the positive edge of upper frequency clock signal HCK and the negative edge respectively.That is being sampled to lower frequency at the positive edge of upper frequency clock signal HCK or negative edge, to allow write signal WE be 1, promptly exports 1 signal.
Please refer to Fig. 4 a, Display Realization is according to synchronous two circuit with the method for the signal of the clock pulse triggering of different frequency of the foregoing description, and it comprises a writing circuit 41 and a sample circuit 42.The state of writing circuit 41 sampling action during in order to the positive edge that is recorded in a upper frequency clock signal and negative edge.It is made up of a D type flip-flop 411 and the 2nd D type flip-flop 412, and both all are positive edge flip-over types.The D terminal of the one D type flip-flop 411 is accepted lower frequency and is allowed write signal WE, and the CK terminal is accepted upper frequency clock signal HCK, and external and its initial condition of Q terminal is 0, represents the sampling state.Because of it is positive edge flip-over type, when at the positive edge of upper frequency clock signal HCK, trigger a D type flip-flop 411.If it is 1 o'clock that the lower frequency of input allows write signal WE, the output of Q terminal is 1, represents lock-out state, is 0 o'clock if the lower frequency of input allows write signal WE, and the output of Q terminal is 0, is the sampling state.By above-mentioned start as can be known, a D type flip-flop 411 is the state of sampling action when being recorded in the positive edge of upper frequency clock signal HCK.The D terminal of the 2nd D type flip-flop 412 is accepted lower frequency and is allowed write signal WE, and the CK terminal is accepted the anti-phase of upper frequency clock signal HCK, and external and its initial condition of Q terminal is 0, represents the sampling state.Same, because of it is positive edge flip-over type,, after anti-phase, promptly trigger the 2nd D type flip-flop 412 when when upper frequency clock signal HCK bears edge.If it is 1 o'clock that the lower frequency of input allows write signal WE, the output of Q terminal is 1, represents lock-out state.If it is 0 o'clock that the lower frequency of input allows write signal WE, the output of Q terminal is 0, is the sampling state.Therefore the 2nd D type flip-flop 412 is the state of sampling action when being recorded in the negative edge of upper frequency clock signal HCK.
Sample circuit 42 is according to the state of sampling action when positive edge of this upper frequency clock signal HCK and the negative edge of writing circuit 41 record, allow write signal WE to take a sample to a lower frequency, and the result that will take a sample when positive edge and negative edge respectively join collection and is output into a synchronization output signal SWE.Its composed component comprise one first with door 421,1 the 3rd D type flip-flop 423, one second with door 422,1 the 4th D type flip-flop 424, one or door 425 and 1 the 5th D type flip-flop 426.The 3rd D type flip-flop 423, the 4th D type flip-flop 424 and the 5th D type flip-flop 426 are positive edge flip-over type.
First accepts this lower frequency with a door input terminal of 421 allows write signal WE, and another input terminal is accepted D type flip-flop 411Q terminal output anti-phase of writing circuit 41, and lead-out terminal then is external to the D terminal of the 3rd D type flip-flop 423.The CK terminal of the 3rd D type flip-flop 423 is accepted the anti-phase of this upper frequency clock signal HCK, and the Q terminal is external to or a door input of 425, and its initial condition is 0.Second accepts this lower frequency with a door input terminal of 422 allows write signal WE, and another input terminal is accepted the 2nd D type flip-flop 412Q terminal output anti-phase of writing circuit 41, and lead-out terminal then is external to the D terminal of the 4th D type flip-flop 424.The CK terminal of the 4th D type flip-flop 424 is accepted this upper frequency clock signal HCK, and the Q terminal is external to or door another input of 425, and its initial condition is 0.
The flowing mode of doing of foregoing circuit then is described.Because the 3rd D type flip-flop 423 is positive edge flip-over type, therefore when the negative edge of upper frequency clock signal HCK, after anti-phase, triggers 423 pairs of lower frequencies of the 3rd D type flip-flop and allow write signal WE to take a sample.And the lower frequency that is input as of D terminal allows the common factor of a write signal WE and a D type flip-flop 411 to export.If lower frequency allow write signal WE be 0, the first with the output of door 421 must also be 0 for 423 pairs of lower frequencies of 0, the three D type flip-flop allow the result of write signal WE sampling, and export to or door 425.If a D type flip-flop 411 is for lock-out state and export 1, behind anti-phase input first and door 421, first with the output of door 421 also be that the result of 0, the three D type flip-flop, 423 samplings is similarly 0.Its meaning is, being sampled to lower frequency at the previous positive edge of the negative edge of this upper frequency clock signal HCK, to allow the result of write signal WE be 1, and is lock-out state through a D type flip-flop 411 its states of record.So when this negative edge, no longer lower frequency is allowed write signal WE sampling, and exports 0.Anti-, be that the state that 0, the one D type flip-flop 411 writes down is the sampling state and exports 0 at previous positive edge sampling result, when bearing edge, can take a sample.If it is 0 output 0 that the sampling lower frequency allows the result of write signal WE, the result is 1 output 1.
In like manner, the 4th D type flip-flop 424 is triggered and is taken a sample at the positive edge of upper frequency clock signal HCK.Its sampling result is subjected to the influence that lower frequency allows the sampling action state of write signal WE and the previous negative edge of the 2nd D type flip-flop 412 records.That is when previous negative edge is sampled to 1, the 2nd D type flip-flop 412 record locking states, the 4th D type flip-flop 424 promptly exports 0.When the 2nd D type flip-flop 412 recording status are the sampling state, and lower frequency to allow write signal WE be that the result of 1, the four D type flip-flop, 424 samplings just is 1 and exports 1.At last, or door 425 will allow the results of write signal WE sampling join the output of collection back to lower frequency at the positive edge of upper frequency clock signal HCK and negative edge to allow write signal SWE synchronously.
In addition can with or door 425 output be connected to the D terminal of the 5th D type flip-flop 426.The CK terminal of the 5th D type flip-flop 426 is accepted upper frequency clock signal HCK, and the external output of Q terminal allows write signal SWE synchronously, and its initial condition is 0.Allow write signal SWE only to change so, synchronously at the positive edge of upper frequency clock signal HCK.When this allowed write signal SWE to reach second module 12 synchronously, the positive edge sampling in upper frequency clock signal HCK allowed write signal SWE synchronously again, and accepts the data that first module 11 transmits according to the result of sampling.
Fig. 4 b shows the sequential chart of the foregoing description.When a of position, be in the positive edge of upper frequency clock signal HCK and allow write signal WE to take a sample lower frequency.Because need the permission write signal WE of time enough to confirm to be sampled to, therefore miss current permission write signal WE, the operate condition of positive edge still remains the sampling state.When the c of position, be in the negative edge of upper frequency clock signal HCK and take a sample, because of sampling result is 1, the operate condition of negative edge is changed into lock-out state.The connection collection should export 1 in the result of positive edge and negative edge sampling.But 426 of the 5th D type flip-flops are triggered in positive edge position, and therefore the result of connection collection is delayed to the waveform that d output in position allows write signal SWE synchronously.Simultaneously, the result who takes a sample at the positive edge of position d still is 0, therefore still keeps the sampling state.When the b of position, be sampled to 1 and just change into lock-out state, and when the g of position, be sampled to 0 and change back the sampling state.In like manner, when the e of position, be sampled to 0 at negative edge, then lock-out state originally changed into the sampling state, be sampled to 1 when the f of position, then changing operate condition is lock-out state.
By the sequential chart of Fig. 4 b as can be known, allow the wave form varies of write signal SWE to allow write signal WE to postpone a time cycle synchronously than lower frequency.Therefore can one the 3rd buffer 24 (as shown in Figure 2) be set again in first module 11 and 12 of second modules, the data that first module 11 is sent to second module 12 is temporary in the 3rd buffer 24.Be resent to second module 12 afterwards, this 3rd buffer 24 is that the positive edge via upper frequency clock signal HCK triggers and moves.
According to embodiments of the invention and since lower frequency allow write signal WE through and the Synchronous Processing of upper frequency clock signal HCK export allow write signal SWE synchronously, second module, 12 direct samples that can directly be operated on upper frequency are handled.Therefore can be considered synchronous with first module 11 that operates on lower frequency, known between the two sequence problem will not exist.Simultaneously the intermodule of two different operation frequencies is considered as synchronously, thus the result of the result who goes out with the aid simulation analysis of EDA and analysis synchronous circuit gained the same be reliable.Therefore designer's sequence problem of deriving for the different clock pulses of this class does not need the time of costing a lot of money to handle yet, and can directly trust the result that the EDA aid is analyzed, with the time-histories of effective shortening exploitation.
The above only is an illustrative, rather than restrictive.Any modification that utilizes those of ordinary skill all can carry out equivalence according to the embodiment of the invention described above, and do not break away from its spirit and category.Anyly do not break away from spirit of the present invention and category, and, all should be contained among the protection range of claim of the present invention its equivalent modifications of carrying out or change.
Claims (9)
1. signal synchronization circuit, in order to synchronous two signals that trigger with the clock pulse of different frequency, it is characterized in that: this circuit comprises
One writing circuit, the state of sampling action during in order to the positive edge that is recorded in a upper frequency clock signal and negative edge; And
One sample circuit, the state of sampling action when positive edge of this upper frequency clock signal and the negative edge according to this writing circuit record, opposite edge at this positive edge and negative edge allows write signal to carry out corresponding sampling action to a lower frequency, and the result that will take a sample when positive edge and negative edge respectively joins collection and is output into a synchronization output signal.
2. signal synchronization circuit as claimed in claim 1 is characterized in that: this writing circuit comprises
One the one D type flip-flop, be positive edge flip-over type, the state of sampling action when being recorded in the positive edge of this upper frequency clock signal, its D terminal is accepted this lower frequency and is allowed write signal, the CK terminal is accepted this upper frequency clock signal, and external and its initial condition of Q terminal is 0; And
One the 2nd D type flip-flop, be positive edge flip-over type, the state of sampling action when being recorded in the negative edge of this upper frequency clock signal, its D terminal is accepted this lower frequency and is allowed write signal, the CK terminal is accepted the anti-phase of this upper frequency clock signal, and external and its initial condition of Q terminal is 0.
3. signal synchronization circuit as claimed in claim 2, it is characterized in that: the Q terminal of a D type flip-flop is output as 0, the state of representative sampling action when the positive edge of this upper frequency clock signal is the sampling state, and being output as 1, to represent this operate condition be lock-out state.
4. signal synchronization circuit as claimed in claim 2, it is characterized in that: the Q terminal of the 2nd D type flip-flop is output as 0, the state of representative sampling action when the negative edge of this upper frequency clock signal is the sampling state, and being output as 1, to represent this operate condition be lock-out state.
5. signal synchronization circuit as claimed in claim 1 is characterized in that: this sample circuit comprises
One first with door, one input end is accepted this lower frequency and is allowed write signal, another input terminal is accepted the anti-phase of D type flip-flop Q terminal output, and a lead-out terminal is external;
One the 3rd D type flip-flop, be positive edge flip-over type, in order to allow write signal to take a sample to this lower frequency when the negative edge of this upper frequency clock signal, its D terminal accept this first with the signal of door output, the CK terminal is accepted the anti-phase of this upper frequency clock signal, and external and its initial condition of Q terminal is 0;
One second with door, one input end is accepted this lower frequency and is allowed write signal, another input terminal is accepted the anti-phase of the 2nd D type flip-flop Q terminal output, and a lead-out terminal is external;
One the 4th D type flip-flop, be positive edge flip-over type, in order to allow write signal to take a sample to this lower frequency when the positive edge of this upper frequency clock signal, its D terminal accept this second with the signal of door output, the CK terminal is accepted this upper frequency clock signal, and external and its initial condition of Q terminal is 0; And
One or door, one input end is accepted the output of the 3rd D type flip-flop Q terminal, and another input terminal is accepted the output of the 4th D type flip-flop Q terminal, and a lead-out terminal is external.
6. signal synchronization circuit as claimed in claim 5, it is characterized in that: this sample circuit also can comprise one the 5th D type flip-flop, is positive edge flip-over type, and its D terminal is accepted the signal of this or door output, the CK terminal is accepted this upper frequency clock signal, and external and its initial condition of Q terminal is 0.
7. signal synchronizing method, in order to synchronous two signals that trigger with the clock pulse of different frequency, it is characterized in that: this method comprises
(a) state of initialization sampling action when the positive edge of a upper frequency clock signal and negative edge is the sampling state;
(b) when the positive edge of this upper frequency clock signal and negative edge, allow write signal to take a sample respectively, and be recorded in the positive edge of this upper frequency clock signal and the sampling action state of negative edge a lower frequency;
(c) carry out corresponding sampling action according to the positive edge of this upper frequency clock signal and the sampling action state of negative edge at next opposite edge; And
(d) will be respectively allowing the result of write signal sampling to join collection to this lower frequency when the positive edge of this upper frequency clock signal and negative edge be output into one and allows write signal synchronously.
8. signal synchronizing method as claimed in claim 7, it is characterized in that: wherein the foundation of (b) change sampling action state is, if positive edge or negative edge at this upper frequency clock signal are 1 to the result that this lower frequency allows write signal to take a sample, the sampling action state that then changes corresponding this positive edge or negative edge is a lock-out state, if the result of sampling is 0, the sampling action state that then changes corresponding this positive edge or negative edge is the sampling state.
9. signal synchronizing method as claimed in claim 8 is characterized in that: wherein the foundation of (c) sampling is
If the last positive edge of the negative edge of this upper frequency clock signal is the sampling state, the result that then should bear the edge sampling is only effectively, and sampling result is 0, be output as 0, sampling result is 1, is output as 1, if this last positive edge is a lock-out state, the result that then should bear the edge sampling is 0; And
If the last negative edge of the positive edge of this upper frequency clock signal is the sampling state, then the result of this positive edge sampling is only effectively, and sampling result is 0, be output as 0, sampling result is 1, is output as 1, if this last negative edge is a lock-out state, then the result of this positive edge sampling is 0.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA021538840A CN1505266A (en) | 2002-12-04 | 2002-12-04 | Signal synchronization method and circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA021538840A CN1505266A (en) | 2002-12-04 | 2002-12-04 | Signal synchronization method and circuit |
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| CN1505266A true CN1505266A (en) | 2004-06-16 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104267909A (en) * | 2014-08-15 | 2015-01-07 | 珠海艾派克微电子有限公司 | Chip on imaging box and data writing response method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104267909A (en) * | 2014-08-15 | 2015-01-07 | 珠海艾派克微电子有限公司 | Chip on imaging box and data writing response method |
| CN104267909B (en) * | 2014-08-15 | 2017-09-22 | 珠海艾派克微电子有限公司 | A kind of chip on imaging cartridge and the method responded is write to data |
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