CN1485886A - Forming method of flute grid electrode profile - Google Patents
Forming method of flute grid electrode profile Download PDFInfo
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- CN1485886A CN1485886A CNA021430748A CN02143074A CN1485886A CN 1485886 A CN1485886 A CN 1485886A CN A021430748 A CNA021430748 A CN A021430748A CN 02143074 A CN02143074 A CN 02143074A CN 1485886 A CN1485886 A CN 1485886A
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Abstract
The invention provides a method to develop the outline of grooved grid. It develops a pad oxide layer and polysilicon layer, then makes thermal oxide processing course to consume partial polysilicon layer to develop a thin oxide layer and a sunken oxidized area; then etches to eliminate the thin oxide layer and partial pad oxide layer to develop a grooved grid outline structure; continues making other semiconductor components.
Description
[technical field]
The present invention relates to a kind of manufacturing method of semiconductor module, particularly relevant for a kind of method that forms the groove grids profile.
[background technology]
Science and technology is advanced few making rapid progress, especially it is especially quick to grow up in the semiconductor fabrication technology, component density on the wafer of identical size constantly is raised, this is so-called Moore's Law (Moore ' s Law), the size of assembly is more and more little, on limited area, the design surface on the assembly is just before the electric capacity that must reduce on the assembly, with the running speed of lifting subassembly.
In metal semiconductor field-effect transistor (MOSFET), when size of components is contracted to dozens of nanometer (nm), the parasitic capacitance of grid and source/drain extension area (extension) (parasitic capacitance) just becomes very remarkable, has also therefore limited running speed and the electrical quality of MOSFET; Then the someone proposes the structure of tool groove grids profile (notched gate), to reduce the generation of grid and source/drain extension area parasitic capacitance, but the method for known formation tool groove grids profile is to utilize isotropic etching (isotropic etching), because when carrying out the isotropic etching manufacture process, because of the etch-rate of either direction all identical, therefore wayward required groove structure and size, thereby limited the lifting of semiconductor subassembly qualification rate and production capacity.
Therefore in the known semiconductor manufacture method, the assembly integration is more and more higher facing, under the more and more little situation of the live width of manufacture process, desire is utilized the structure of tool groove grids profile, reduce the electric capacity between grid and source/drain extension area, will be difficult to control etched result in the manufacture process, more can further influence the stability of assembly, be difficult to make less semiconductor subassembly with making, and reduce the qualification rate and the electrical quality of assembly.Therefore, the present invention promptly at above-mentioned disappearance, proposes a kind of method that forms the groove grids profile, effectively to overcome the disappearance of traditional approach.
[summary of the invention]
Main purpose of the present invention is that a kind of method that forms the groove grids profile is being provided, it is the interface both sides in polysilicon layer and oxide layer, form a thin oxide layer that caves inward, can reduce the electric capacity between grid and source/drain extension area, to promote the characteristic and the electrical quality of assembly.
Secondary objective of the present invention is that a kind of method that forms the groove grids profile is being provided, and can reduce the resistance of metal silicide under limited grid length.
A further object of the present invention is a kind of method that forms the groove grids profile to be provided, because of under the electric capacity between lower grid and source/drain extension area, to have higher saturation current density.
In order to achieve the above object, the present invention is after a substrate surface is finished oxide layer and polysilicon layer utmost point stack architecture, carry out a thermal oxidation manufacture process, oxidation polysilicon layer partly, around this polysilicon layer, to form a thin oxide layer, and the thin oxide layer between between polysilicon layer and pad oxide caves inward, and after the thin oxide layer and pad oxide partly of etching removal polysilicon layer both sides and upper surface, forms the tool notched gate structure.
Below illustrate in detail by the specific embodiment conjunction with figs., when the effect that is easier to understand purpose of the present invention, technology contents, characteristics and is reached.
[description of drawings]
Figure 1A to Fig. 1 E forms each step profile of groove grids contour structure for the present invention.
[embodiment]
See also Figure 1A, at first in semiconductor substrate 10, form suitable isolation structure (in figure, not representing), as field oxide, shallow slot isolation structure etc., to define active region, then in this substrate 10, form a pad oxide 12, on pad oxide 12, deposit a polysilicon layer 14 then, wherein this pad oxide 12 can be made up of silicon dioxide, and polysilicon layer 14 can utilize chemical vapour deposition technique (chemical vapordeposition, CMP) dopant deposition or unadulterated polysilicon.
Then see also Figure 1B, at this substrate 10 surface coverage one patterning photoresistance (in figure, not representing), utilize photolithography techniques etching this polysilicon layer 14 and pad oxide 12, to form the stack structure of a tool polysilicon layer 14 and pad oxide 12.
Carry out a thermal oxidation manufacture process, around the polysilicon layer 14 of stack structure, to form the thin oxide layer 16 shown in Fig. 1 C, can consume the polysilicon layer 14 in the stack structure partly when forming this thin oxide layer 16, and the thin oxide layer 16 that is positioned at 12 of polysilicon layer 14 and pad oxides can cave inward, its principle is just as in local oxidation of silicon (LOCOS) manufacture process, when in substrate, making insulation system, form the structure of beak (bird ' s beak), because of the diffusion of oxygen in silicon dioxide is iso process, therefore oxygen also can be run into the polysilicon layer 14 of side, forms the oxide regions that caves at the interface of 12 of polysilicon layer 14 and pad oxides.
Then, the thin oxide layer 16 and the pad oxide 12 partly thereof of these polysilicon layer 14 both sides and upper surface removed in etching, to form as Fig. 1 polysilicon layer that D is shown in 14 and pad oxide 12 interface both sides, has the stack structure of a depression oxide regions; Be shielding with this stack structure again, carry out a shallow ion doping manufacture process, be shielding in the stack structure, carry out in a shallow ion doping manufacture process 18 stack structure substrate on two sides 10, form a shallow ion doped region (not representing in figure), wherein the ionic species of this shallow ion doped region can be phosphonium ion or boron ion.
In substrate 10 surface deposition layer of oxide layer, utilize etching technique that this oxide layer is carried out vertical unidirectional etch-back, the partial oxidation layer of polysilicon layer 14 and substrate 10 is removed in etching, so that each forms sidewall 20 structures shown in Fig. 1 E in this stack structure both sides, with this stack structure and sidewall 22 is shielding, in this substrate 10, carry out deep ion doping step 22, to form deep ion doped region (in figure, not representing), respectively as source electrode and drain electrode, wherein be the structure of source/drain extension area in the position that this shallow ion doping is not mixed by deep ion, can continue follow-up semiconductor fabrication, as form automatic aligning metal silicide (salicide), to finish follow-up semiconductor structure.
Therefore, the present invention forms the method for groove grids profile, can be widely used in the semiconductor fabrication, after forming the stack structure of polysilicon layer and pad oxide in the substrate, utilize the mode of thermal oxidation to consume between polysilicon layer partly and pad oxide interface, can form the structure of similar beak, can form the stack structure of tool groove oxide regions through etch process, can reduce the parasitic capacitance between polysilicon layer and source/drain extension area, improve the density of saturation current, and can reduce the resistance value of automatic aligning silicide, simplify the control in the manufacture process and increase stability, increase the characteristic and the electrical quality of product by this, to promote the qualification rate of product.
Above-described embodiment only is for technological thought of the present invention and characteristics are described, its purpose makes the personage who has the knack of this skill can understand content of the present invention and is implementing according to this, when can not with qualification claim of the present invention, promptly the equalization of doing according to disclosed spirit generally changes or modifies, and must be encompassed in the claim of the present invention.
Claims (10)
1. a method that forms the groove grids profile is characterized in that comprising the following steps:
One substrate is provided, has formed a pad oxide on it;
On this pad oxide, form a conductive layer;
Remove this conductive layer partly to form a stack structure, wherein this stack structure comprises and contacted first limit of this pad oxide, with second limit with respect to this first limit; And
This stack structure is carried out thermal oxidation, make the length on this first limit less than the length on this second limit.
2. the method for formation groove grids profile according to claim 1, it is characterized in that in the step of this stack structure of thermal oxidation, be to form a thin oxide layer on this stack structure, wherein this thin oxide layer inwardly recesses in the sidewall on first limit of this stack structure.
3. the method for formation groove grids profile according to claim 2 is characterized in that further comprising the following steps:
Remove this thin oxide layer and this pad oxide partly, to expose this stack structure partly;
With this stack structure is screen, is implanted into first kind of dopant ion in this substrate;
Form a sidewall in these stack structure both sides; And
With this stack structure and this sidewall is the secondary shielding layer, implants second kind of dopant ion in this substrate.
4. the method for formation groove grids profile according to claim 1 is characterized in that this conductive layer is made up of polysilicon.
5. the method for formation groove grids profile according to claim 1 is characterized in that removing this conductive layer partly and forms in the step of this stack structure, further comprises:
On this conductive layer, cover a screen;
Etching is this conductive layer of conductively-closed layer covering not; And
Remove this screen.
6. a method that forms the groove grids profile is characterized in that comprising the following steps:
One substrate is provided, has formed a pad oxide on it;
Deposition one polysilicon layer on this pad oxide;
Etching this polysilicon layer partly, to form a stack structure, wherein this stack structure has a sidewall;
Carry out a thermal oxidation processing procedure, to form a thin oxide layer on this stack structure, wherein this thin oxide layer of close this pad oxide inwardly concaves and is formed at this sidewall.
7. the method for formation groove grids profile according to claim 6, it is characterized in that inwardly concaving in the step that is formed at this sidewall near this thin oxide layer of this pad oxide, make first edge lengths of this stack structure less than second limit, and this first limit is meant the one side that contacts with this pad oxide, and with respect to second limit.
8. the method for formation groove grids profile according to claim 6 is characterized in that forming a screen earlier before etch process on this polysilicon layer, promptly removes this screen behind etching step.
9. the method for formation groove grids profile according to claim 6 is characterized in that further comprising the following steps: after the step of carrying out the thermal oxidation processing procedure
Remove this thin oxide layer and this pad oxide partly, to expose this stack structure partly;
With this stack structure is first screen, carries out the implantation process of first kind of dopant ion;
Form a clearance wall in these stack structure both sides; And
With this stack structure and this clearance wall is the secondary shielding layer, implants second kind of dopant ion in this substrate.
10, the method for formation groove grids profile according to claim 9 is characterized in that this clearance wall is made up of monoxide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02143074 CN1259697C (en) | 2002-09-27 | 2002-09-27 | Forming method of flute grid electrode profile |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02143074 CN1259697C (en) | 2002-09-27 | 2002-09-27 | Forming method of flute grid electrode profile |
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| Publication Number | Publication Date |
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| CN1485886A true CN1485886A (en) | 2004-03-31 |
| CN1259697C CN1259697C (en) | 2006-06-14 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 02143074 Expired - Fee Related CN1259697C (en) | 2002-09-27 | 2002-09-27 | Forming method of flute grid electrode profile |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100377313C (en) * | 2004-07-12 | 2008-03-26 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Method for increasing deep submicron multiple crystalline silicon grating etching uniformity |
| CN103035500A (en) * | 2012-06-04 | 2013-04-10 | 上海华虹Nec电子有限公司 | Formation method of trench gate |
| CN105304492A (en) * | 2014-07-30 | 2016-02-03 | 北大方正集团有限公司 | Semiconductor device and manufacture method thereof |
| CN106158614A (en) * | 2015-04-20 | 2016-11-23 | 北大方正集团有限公司 | The preparation method of semiconductor device |
| CN109727865A (en) * | 2017-10-30 | 2019-05-07 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic device |
-
2002
- 2002-09-27 CN CN 02143074 patent/CN1259697C/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100377313C (en) * | 2004-07-12 | 2008-03-26 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Method for increasing deep submicron multiple crystalline silicon grating etching uniformity |
| CN103035500A (en) * | 2012-06-04 | 2013-04-10 | 上海华虹Nec电子有限公司 | Formation method of trench gate |
| CN103035500B (en) * | 2012-06-04 | 2015-06-03 | 上海华虹宏力半导体制造有限公司 | Formation method of trench gate |
| CN105304492A (en) * | 2014-07-30 | 2016-02-03 | 北大方正集团有限公司 | Semiconductor device and manufacture method thereof |
| CN106158614A (en) * | 2015-04-20 | 2016-11-23 | 北大方正集团有限公司 | The preparation method of semiconductor device |
| CN106158614B (en) * | 2015-04-20 | 2019-06-14 | 北大方正集团有限公司 | The preparation method of semiconductor devices |
| CN109727865A (en) * | 2017-10-30 | 2019-05-07 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic device |
| CN109727865B (en) * | 2017-10-30 | 2022-06-28 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
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| Publication number | Publication date |
|---|---|
| CN1259697C (en) | 2006-06-14 |
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