CN1472942A - Byte transparent processing method to data flow - Google Patents
Byte transparent processing method to data flow Download PDFInfo
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Abstract
The present invention discloses a method for transparently processing bytes in a data flow. The method sets the frame data which will be inputted to all inputs of a preprocessing module, makes the identifiers for 0X7d and 0X7e according to the different high or low bytes, writes-in respectively the data with 9 bits consisting of every byte and its identifier bit into n first-in-first-out (FIFO) devices, and provides another smaller first-in-first-out (FIFO) device as a reading control, with a transparent converting module constituted of 3xn channels of registers with 9 bits. The method of the invention can realize the transparent process for the bytes in a data flow simply and easily, save resources and have a high speed. The method of the invention is suitable to the internal data bus with 16, 24, 32 bits or more.
Description
Technical fieldThe present invention relates to a kind of method that byte in the data flow is handled, especially relate to a kind of method that byte transparent in the data flow is handled.
Background technologyHigh level data controlling links (HDLC) agreement is a kind of agreement that is applied to transmit data between network node, is widely used in the transmission technology; And SDH (Synchronous Digital Hierarchy) link access processing (LAPS) agreement is an emerging agreement, it extremely is similar to the former,, adopt the SDH (Synchronous Digital Hierarchy) link to insert and handle (LAPS) agreement very succinctly efficiently in the application in SDH (Synchronous Digital Hierarchy) at Internet protocol and Ethernet protocol.But some problems below also existing.
If in transmission, payload user data is packaged into high-rise controlling links (HDLC) protocol frame or SDH (Synchronous Digital Hierarchy) link access processing (LAPS) protocol frame, because between the different frames by one or more 0X7e at interval, and receive direction is by judging that 0X7e locatees different frames, for fear of obscuring, must the 0X7e of frame in the payload data stream itself be processed, be 0X7e＞＞0X7d5e, wherein 0X7d is for shifting byte; Same reason also must process the 0X7d of itself in the payload data stream, promptly 0X7d＞＞0X7d5d.So just require 0X7d and 0X7e in the data flow of two kinds of above-mentioned frame payloads are done transparent processing, soon 0X7d is converted to 0X7d5d, 0X7e is converted to 0X7d5e.When realizing above-mentioned processing with field programmable gate array (FPGA), for 16 internal buss (i.e. the interior data that must handle 2 bytes of clock cycle), because bytes of payload is unpredictable and do not have a rule, so having 1 byte, the data that receive in each clock cycle need do transparent processing, also may 2 bytes all need to do transparent processing, may not need to do transparent processing yet, implement very loaded down with trivial details like this.
When for example payload user data is 0X7d55,0X7d7d, 0X557d, 0X5555,0X7d55, as follows to its detailed process of carrying out the transparent processing conversion: in first count clock input data is 0X7d55, owing to need do transparent processing to 0X7d, become 0X7d5d, so this clock cycle just can only be exported 0X7d5d, corresponding 0X55 just must be detained; Then next bat input data is 0X7d7d, and these two bytes all need to do transparent processing, so second count clock cycle output 0X557d, also will be detained down data 0X5d7d, 0X5d, the rest may be inferred, and the final data stream that whole payloads are done after the transparent processing will be: 0X7d5d, 0X557d, 0X5d7d, 0X5d55,0X7d5d, 0X5555,0X7d5d, 0X55 changes very complicated so as can be seen.
Specifically, the realization majority of high level data controlling links (HDLC) agreement is all based on 8 internal data buses, make the internal clocking frequency of field programmable gate array (FPGA) can not reach very high, general master clock frequency can not surpass 100M, and when the bandwidth of SDH (Synchronous Digital Hierarchy) (SDH) greater than 622M the time, 8 bit data bus can not satisfy the bandwidth needs, and internal bus is necessary for 16 when being 1.25G as the bandwidth of SDH (Synchronous Digital Hierarchy) (SDH).With respect to the transparent processing of 8 internal buss, the transparent processing of 16 internal buss is more complicated, and emerging SDH (Synchronous Digital Hierarchy) link access processing (LAPS) agreement is based on 16 internal data buses more.During as for 24,32 even wideer internal data bus, its to byte in the data flow carry out that transparent processing will be than 16 complicated more.
Therefore existing technology solves the above problems complicated loaded down with trivial detailsly, and resource is also wasted, and can take a lot of logical blocks.
Summary of the inventionThe objective of the invention is: provide a kind of method to make to carry out simple that the method for transparent processing becomes, only need a less resource just can realize transparent processing.Simultaneously, require the speed of this method fast, on general field programmable gate array (FPGA), can reach the clock frequency of 100M, and the autgmentability of this method to get well, easily graft application
In 24,32 even wideer internal bus.
The object of the present invention is achieved like this: a kind of method that byte transparent in the data flow is handled, may further comprise the steps,
A) utilize the input pretreatment module to travel through the 8Xn position frame data of importing, and respectively 0X7d and 0X7e are done sign by high low byte;
B) write individual above-mentioned input pretreatment module first-in first-out device (FIFO) buffer memory afterwards that is connected of n with n respectively by the sign position with by the data that identification byte is formed;
C) set a first-in first-out device (FIFO) that is connected with above-mentioned buffer memory first-in first-out device (FIFO) and read to control, control next bat pronunciation of current data;
D) to carrying out transparent processing from the above-mentioned n that is used for buffer memory the data that first-in first-out device (FIFO) is read, its realization is a transparent translation module of utilizing predefined 3Xn register pipeline to constitute, and controls first-in first-out device (FIFO) with the above-mentioned n that is used for buffer memory first-in first-out device (FIFO) and above-mentioned reading and be connected.
And,
Above-mentioned makes a check mark further comprising the steps of to 0X7d and 0X7e: high low byte separate processes, add a bit-identify position in highest order, and sign and corresponding byte are formed the 9bit data,
Directly will import low 4 low 4 of putting into conversion back data of data.
Above-mentioned input pretreatment module also is used to detect the full state of sky of the above-mentioned n that is used for buffer memory first-in first-out device (FIFO), and when above-mentioned n first-in first-out device (FIFO) almost make completely the time read to enable invalid.
Above-mentioned steps c) further comprising the steps of:
Above-mentioned read to control between first-in first-out device (FIFO) and above-mentioned n the buffer memory first-in first-out device (FIFO) also be connected with a logic module, the control information of reading of above-mentioned reading being controlled first-in first-out device (FIFO) is converted into the control of reading to above-mentioned n buffer memory first-in first-out device (FIFO).
Above-mentioned step c) is further comprising the steps of:
Setting above-mentioned reading, to control the value of first-in first-out device (FIFO) be 111 ... the data of n byte are read in next bat of sign current data during 111 (being total to the numerical digit that rounds of lgn/lg2), and next bat of sign current data read to reduce successively the data of a byte when value reduced successively.
Above-mentioned step c) is further comprising the steps of:
Current when reading 1 byte data, then next is clapped above-mentioned buffer memory first-in first-out device (FIFO) is read the order transposing.
Above-mentioned step d) is further comprising the steps of:
When above-mentioned transparent translation module register pipeline read in any byte data less than n, above-mentioned pipeline moved the data of this byte and also only exports the data of this byte.
Simultaneously,
The degree of depth of the above-mentioned n that is used for buffer memory first-in first-out device (FIFO) greater than in or equal 16.
The register duct length of above-mentioned transparent conversion module is more than or equal to 6.
The above-mentioned bit wide of reading to control first-in first-out device (FIFO) is the lgn/lg2 round numbers.
The above-mentioned degree of depth of reading to control first-in first-out device (FIFO) is 8Xn, and more than or equal to the length of above-mentioned register pipeline.
So, promptly realize byte in the data flow is carried out a kind of simple method of transparent processing, and only needed less resource just can realize the purpose of transparent processing.Simultaneously, the speed of this method is very fast, on general field programmable gate array (FPGA), can reach the clock frequency of 100M easily, and its favorable expandability, easily the transparent processing of graft application when 24,32 even wideer internal bus.
Describe preferred embodiment of the present invention in detail below in conjunction with accompanying drawing,, can clearerly find out and understand advantage of the present invention place by description to preferred embodiment of the present invention.
Description of drawingsFig. 1 is that the SDH (Synchronous Digital Hierarchy) link inserts the frame assumption diagram of handling (LAPS) protocol frame;
Fig. 2 is the frame assumption diagram of high level data controlling links (HDLC) protocol frame;
Fig. 3 is the schematic block diagram that whole packaged frame is carried out transparent processing;
Fig. 4 is the block diagram of method of the present invention.
EmbodimentAs Fig. 1,0X7e is that the SDH (Synchronous Digital Hierarchy) link inserts the positioning mark field of handling (LAPS) frame, pass through one or more 0X7e between the different frames at interval, and receive direction is by judging that 0X7e locatees different frames.0X04,0X03 are fixing praglit section, and 0Xfe01 identification data payload is that (MAC) frame is controlled in media interviews, and frame check field (FCS) is that address, control, protocol-identifier (SAPI) and payload user data are made cyclic redundancy check (CRC) (CRC32) result calculated.
As Fig. 2, the frame assumption diagram of high level data controlling links (HDLC) protocol frame, it is similar to the SDH (Synchronous Digital Hierarchy) link and inserts the frame assumption diagram of handling (LAPS) frame very much, repeats no more here.
As Fig. 3, this figure is an example with 16 internal buss, when reading to enable when effective, the input data that front end is 16 at first enter the input pretreatment module, enter processing (LAPS) protocol frame by the good SDH (Synchronous Digital Hierarchy) link of this module traversal package, perhaps high level data controlling links (HDLC) protocol frame, then 16 bit data are done 0X7d or 0X7e sign by high low byte respectively, sign position and corresponding height or low byte are formed 9 data together, write following first-in first-out device (FIFO) 1 or 2 buffer memorys then.Here, 0X7d and 0X7e are done identical sign, can not cause and obscure, because 0X7d＞＞0X7d5d, 0X7e＞＞0X7d5e, can see source data before low 4 and the conversion of conversion back data low 4 identical, therefore can be directly in conversion with source data low 4 put into data after the conversion hang down 4, so not only make problem reduction, and economize on resources.
Simultaneously, the input pretreatment module also detects the first-in first-out device (FIFO) 1 and 2 of following 16 above degree of depth that are used for buffer memory, detect its empty full state, be in almost when expiring when detecting first-in first-out device (FIFO) 1 or 2, this module also make front end read to enable invalid, stop to read front end data, overflow to avoid the data in first-in first-out device (FIFO) 1 or 2.
Adopt 8 dark first-in first-out devices (FIFO) of one 1 bit wide to do and read control, be connected with 2 with buffer memory first-in first-out device (FIFO) 1, read control section and determine according to the dateout of first-in first-out device (FIFO) 1 and 2 how next bat of current data reads, perhaps be the next clock cycle to read a first-in first-out device (FIFO), perhaps read two, perhaps do not need to read.The initial value of reading to control first-in first-out device (FIFO) is complete 1, reads the order initialization and can be set at first-in first-out device (FIFO) 1 earlier.Identifying next bat and read two bytes when the value of reading to control first-in first-out device (FIFO) is 1, is to identify next bat at 0 o'clock to read a byte.Read control section and also comprise a logic module, be connected and read to control between first-in first-out device (FIFO) and first-in first-out device (FIFO) 1 and 2, as shown in this figure.Read to control first-in first-out device (FIFO) inside array parameter is set in advance, the value that is used for finding according to the data of reading from first-in first-out device (FIFO) 1 and 2 next bat is 1 or is 0, again by the concrete pronunciation of logic module control to first-in first-out device (FIFO) 1 and 2.Concrete control can be different, lift one for example down:
Value such as current sense data is 0X7d7d, the two transparent translation modules that take face can only be handled the data of a byte so down, be 0X7d＞＞0X7d5d, so ensuing two clap can only read data from first-in first-out device (FIFO) 1 or 2, read to control this moment in the first-in first-out device (FIFO) and to write two 0 according to built-in array in advance and control; Be 0X5555 such as current sense data again, next bat is to read two bytes from first-in first-out device (FIFO) 1 and 2 so, and read to control in the first-in first-out device (FIFO) and write one 1 this moment.The rest may be inferred, reads control section and just can read in buffer memory first-in first-out device (FIFO) 1 and 2 one, two or do not read by logic module control.In addition the acquiescence initially read the order be that first-in first-out device (FIFO) 1 is prior to 2, but when occurring reading byte, the order that reads to first-in first-out device (FIFO) 1 and 2 is changed, so, read control section and just can control the concrete pronunciation that reads first-in first-out device (FIFO) 1 and 2.
Transparent translation module and buffer memory first-in first-out device (FIFO) 1 and 2 and read control section and be connected respectively, register pipeline by 69 constitutes, we might as well be with its difference called after byte0～byte5 at this, and wherein entrance is byte0 and byte1, exports to be byte4 and byte5.For first-in first-out device (FIFO) 1 and 2, if the current control section of reading only enables the read signal of one of them, pipeline only moves a byte so, also only export a byte, be FIFO1＞＞byte0＞＞byte1＞＞byte2＞＞byte3＞＞byte4＞＞byte5＞＞out, perhaps FIFO2＞＞byteO＞＞byte1＞＞byte2＞＞byte3＞＞byte4＞＞byte5＞＞out; And if read the read signal that control section enables two, pipeline moves 2 bytes and also exports 2 bytes so, be FIFO1＞＞byte1＞＞byte3＞＞byte5＞＞out, FIFO2＞＞byte0＞＞byte2＞＞byte4＞＞out, perhaps FIFO2＞＞byte1＞＞byte3＞＞byte5＞＞out, FIFO1＞＞byte0＞＞byte2＞＞byte4＞＞out.
Because if when being 0X7d entirely in 6 registers in the transparent translation module conduits, read to control first-in first-out device (FIFO) and just must preserve 60, all can only from first-in first-out device (FIFO) 1 or 2, read a byte to indicate back six to clap the clock cycle, so the degree of depth of reading to control first-in first-out device (FIFO) depends on the register duct length of transparent translation module, promptly its degree of depth must be greater than or equal to the length of register pipeline.Under 16 internal data buses, we are provided with it is that 8 of 1 bit wides are dark.Again because from first-in first-out device (FIFO) 1 or 2 sense datas to according to sense data change control signal, need the time of 3 clock cycle at least, so the length of the register pipeline here is greater than 6.
As Fig. 4, still be example with 16 internal data buses, method of the present invention at first is step s102,16 input data enter the input pretreatment module, then be step s104, the frame data of input pretreatment module traversal input, and respectively 0X7d and 0X7e are done like-identified by high low byte, be step s106 and step 108 thereafter, write first-in first-out device (FIFO) 1 and 2 buffer memorys with two respectively by the sign position with by 9 numeric bit datas that identification byte is formed, carry out step s110 and step s112 simultaneously, first-in first-out device (FIFO) 1 and 2 is given the input pretreatment module to the full signal of clearancen respectively, whether stop front end with decision and read to enable, thereby avoid overflowing of first-in first-out device (FIFO) 1 and 2.Thereafter being step s118 and step s120, reading to control the dateout that first-in first-out device (FIFO) reads buffer memory first-in first-out device (FIFO) 1 and 2, is step s122 then, and logic module is judged the value of reading to control first-in first-out device (FIFO).
If value is 1, then be step s124, control transparent translation module reads 2 byte datas from first-in first-out device (FIFO) 1 and 2; If value is 0, then is step s 126, to change the read order of next bat, and then carry out step s128 first-in first-out device (FIFO) 1 and 2, control transparent translation module only reads the data of 1 byte from first-in first-out device (FIFO) 1 and 2.
In the epimere step, the transparent translation module is according to the control execution in step s114 and the s116 that read control section, respectively or simultaneously from first-in first-out device (FIFO) 1 and 2 reading of data, be step s130 at last, the transparent translation module carries out being exported after the transparent translation to the data of reading in again.
With regard to simple byte in the data flow is carried out transparent processing like this, and economize on resources very much, only need 150 logical blocks; Speed is also fast simultaneously, through experimental verification, can reach the clock frequency of 100M easily on general field programmable gate array (FPGA).And method of the present invention also has very strong autgmentability, for 24,32 even wideer internal data bus, only need to change the quantity of first-in first-out device (FIFO) 1 among Fig. 3 and 2, and accordingly the input data are added after the sign that by one section of a byte buffer memory advances in each first-in first-out device (FIFO) respectively; Strengthen simultaneously and read to control the degree of depth and the width of first-in first-out device (FIFO), and it is just passable to increase the quantity of register of transparent conversion module.Other comprise reads control section to control method of reading of data etc. all substantially roughly the same.
Here it is to be noted: those of ordinary skill in the art can make various suitable distortion or replacement on basis of the present invention, but all these distortion or replacement all should belong to protection scope of the present invention.
Claims (11)
1, a kind of method that byte transparent in the data flow is handled is characterized in that: may further comprise the steps,
A) utilize the input pretreatment module to travel through the 8Xn position frame data of importing, and respectively 0X7d and 0X7e are done sign by high low byte;
B) write individual described input pretreatment module first-in first-out device (FIFO) buffer memory afterwards that is connected of n with n respectively by the sign position with by the data that identification byte is formed;
C) set a first-in first-out device (FIFO) that is connected with described buffer memory first-in first-out device (FIFO) and read control, next of control current data clapped pronunciation;
D) data of reading from described n the first-in first-out device (FIFO) that is used for buffer memory are carried out transparent processing, its realization is a transparent translation module of utilizing predefined 3Xn register pipeline to constitute, and with described n the first-in first-out device (FIFO) that is used for buffer memory and describedly read to control first-in first-out device (FIFO) and be connected.
2, method according to claim 1 is characterized in that: described 0X7d and 0X7e are made a check mark may further comprise the steps: high low byte separate processes, add a bit-identify position in highest order, and sign and corresponding byte are formed the 9bit data,
Directly will import low 4 low 4 of putting into conversion back data of data.
3, method according to claim 1 is characterized in that:
Described input pretreatment module also is used to detect the described full state of sky that is used for n the first-in first-out device (FIFO) of buffer memory, and when described n first-in first-out device (FIFO) almost make completely the time read to enable invalid.
4, method according to claim 1, wherein step c) is further comprising the steps of:
Described read to control between first-in first-out device (FIFO) and described n the buffer memory first-in first-out device (FIFO) also be connected with a logic module, the described control information of reading of reading to control first-in first-out device (FIFO) is converted into the control of reading to described n buffer memory first-in first-out device (FIFO).
5, method according to claim 1, wherein step c) is further comprising the steps of:
Setting the described value of reading to control first-in first-out device (FIFO) is 111 ... the data of n byte are read in next bat of sign current data during 111 (being total to the numerical digit that rounds of lgn/lg2), and next bat of sign current data read to reduce successively the data of a byte when value reduced successively.
6, method according to claim 1, wherein step c) is further comprising the steps of:
Current when reading 1 byte data, then next is clapped described buffer memory first-in first-out device (FIFO) is read the order transposing.
7, method according to claim 1, wherein step d) is further comprising the steps of:
When described transparent translation module register pipeline read in any byte data less than n, described pipeline moved the data of this byte and also only exports the data of this byte.
8, method according to claim 1 is characterized in that:
The degree of depth of described n the first-in first-out device (FIFO) that is used for buffer memory is more than or equal to 16.
9, method according to claim 1 is characterized in that:
The register duct length of described transparent conversion module is more than or equal to 6.
10, method according to claim 1 is characterized in that:
The described bit wide of reading to control first-in first-out device (FIFO) is the 1gn/lg2 round numbers.
11, according to claim 1 or 10 or 11 described methods, it is characterized in that:
The described degree of depth of reading to control first-in first-out device (FIFO) is 8Xn, and more than or equal to the length of described register pipeline.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101047721B (en) * | 2007-04-11 | 2010-05-26 | 重庆重邮信科通信技术有限公司 | Method for data filter process using DMA controller |
| WO2010148969A1 (en) * | 2009-12-02 | 2010-12-29 | 中兴通讯股份有限公司 | Data sending/receiving methods and devices for etc system |
| CN101635844B (en) * | 2008-07-23 | 2012-05-30 | 比亚迪股份有限公司 | Image data transmission method and device |
| CN103297184A (en) * | 2012-02-24 | 2013-09-11 | 瑞鼎科技股份有限公司 | Digital data processing method and digital data transmission system |
| CN103747253A (en) * | 2013-12-27 | 2014-04-23 | 高新兴科技集团股份有限公司 | Method for transmitting video coded data based on FIFO |
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2002
- 2002-07-29 CN CN 02134457 patent/CN1223161C/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101047721B (en) * | 2007-04-11 | 2010-05-26 | 重庆重邮信科通信技术有限公司 | Method for data filter process using DMA controller |
| CN101635844B (en) * | 2008-07-23 | 2012-05-30 | 比亚迪股份有限公司 | Image data transmission method and device |
| WO2010148969A1 (en) * | 2009-12-02 | 2010-12-29 | 中兴通讯股份有限公司 | Data sending/receiving methods and devices for etc system |
| CN102087755A (en) * | 2009-12-02 | 2011-06-08 | 中兴通讯股份有限公司 | Data transmission method and device and data receiving method and device of electronic toll collection (ETC) system |
| CN103297184A (en) * | 2012-02-24 | 2013-09-11 | 瑞鼎科技股份有限公司 | Digital data processing method and digital data transmission system |
| CN103297184B (en) * | 2012-02-24 | 2017-05-03 | 瑞鼎科技股份有限公司 | Digital data processing method and digital data transmission system |
| CN103747253A (en) * | 2013-12-27 | 2014-04-23 | 高新兴科技集团股份有限公司 | Method for transmitting video coded data based on FIFO |
| CN103747253B (en) * | 2013-12-27 | 2017-04-05 | 高新兴科技集团股份有限公司 | A kind of video data encoder transmission method based on FIFO |
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