CN1466110A - Video traffic dynamic information collecting equipment - Google Patents
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Abstract
The invention refers to a module video communication dynamic information gathering device, the device gets the picture of the observed region through vidicon, several video pictures real time processor which are connected with the vidicons correspondingly and process the video pictures outputted by the videcon and acquires the needed information; the main controller which is used to reconcile the processors and store the gathered communication information; and the bus board which connects the controller and processors, the bus board uses high speed synchronous serial data bus and provides the physical connection between the controller and the processors.
Description
Technical field
The present invention relates to utilize DSP (Digital Signal Processing, be digital signal processing) and CPLD (CPLD) technology, image processing techniques, data communication technology and video image encoding and decoding technology and a kind of video traffic dynamic information collecting equipment of designing, can be used for the transport information of roads such as traffic intersection, highway section, highway is carried out real-time data acquisition, to realize dredging and controlling to traffic flow.
Background technology
Existing video traffic information acquiring technology mainly contains following two kinds:
A kind of is to utilize desk-top industrial control computer as image processor,, adopts based on the image pick-up card of pci bus and forms a traffic information collection platform as the image digitazation front end as data storage medium with hard disk.Platform based on this technology can only be handled one tunnel picture signal in real time, and for the traffic information collection architecture of being made up of multiple cameras, this mode can not satisfy the integrated requirement of large scale system like this;
Second kind is to adopt the embedded computer structure, with the FLASH storer as storage medium, with the picture decoding chip of special use as the image digitazation front end, with this configuration information acquisition platform, this platform has still adopted the computer architecture based on universal cpu, when needs are handled multi-channel video signal in real time, for the reportedly defeated bottleneck problem of the total demand pairs of resolution system with under the universal cpu instruction set, finish the Image Information Processing function, need to adopt a large amount of field programmable gate arrays (FPGA) that digital picture is carried out pre-service, when vision signal quantity increased, this architecture can't bear the heavy load.
Summary of the invention
In order to overcome the above-mentioned defective of prior art, the invention provides a kind of video traffic dynamic information collecting equipment, set up an opening, modular hardware architecture, the quantity of image processing module can be installed according to actual needs, and the real-time of guarantee information collection.
The technical solution adopted for the present invention to solve the technical problems is: construct a kind of video traffic dynamic information collecting equipment, comprise a plurality of video cameras that are used to take the road traffic real-time status, it is characterized in that, also comprise with described video camera connecting one to one, being used for the video image that the video camera that is attached thereto is exported is handled in real time to obtain a plurality of video image real-time processors of required transport information; Be used to coordinate the duty of described each video image real-time processor and store the master controller of the transport information of being gathered; And the bus backplane that is used to connect described master controller and each video image real-time processor, described bus backplane adopts the high-speed synchronous serial data bus, for the exchanges data between master controller and the video image real-time processor provides physical connection.
In video traffic dynamic information collecting equipment of the present invention, described video image real-time processor comprises second Video Decoder that is connected with described video camera, be used for decoded original data is handled to obtain second central processing unit of required transport information, the data-carrier store that is connected with described second central processing unit, and be connected the output interface that is used to export the transport information of being gathered with described second central processing unit.Wherein, described second central processing unit adopts digital signal processor at a high speed, the digital picture memory buffer that also comprises the original data that is used to store described image decoder output in the described video image real-time processor, and adopt an address decoding of forming by CPLD, steering logic and digital video store control logic circuit are as the performer of interface and steering logic, described address decoding, steering logic and digital video store control logic circuit connect described image decoder, digital picture memory buffer and data-carrier store separate second central processing unit and described second image decoder and digital picture memory buffer of described high speed on control timing.
In video traffic dynamic information collecting equipment of the present invention, described address decoding, the inside of steering logic and digital video store control logic circuit comprises sampling controller, the address reseting logic, address generator, the sequential match circuit, address bus change-over switch and data bus change-over switch, these internal components are under the control of described second Video Decoder, can automatically the original data of catching be stored in the described digital picture memory buffer, under the control of described second central processing unit, described original data is sent in the described data-carrier store fast then.
In video traffic dynamic information collecting equipment of the present invention, described output interface is the high-speed synchronous serial bus interface, can be used for connecting transport information that described high-speed synchronous universal serial bus gathered with output or the digital video image that obtains, and realize driving and load matched described high-speed synchronous universal serial bus.
In video traffic dynamic information collecting equipment of the present invention, described master controller comprises first central processing unit that adopts high speed digital signal processor; Be connected to the high-speed synchronous serial bus interface of described video image real-time processor by described high-speed serial bus; First Video Decoder that is connected with described video camera by the gauge tap on the video image real-time processor; The transport information that be connected with the output terminal of first Video Decoder and first central processing unit, is used for the to be gathered digital video superposing control unit on the present image that is added to; And the video encoder that is connected with the output terminal of digital video superposing control unit; Wherein also adopt one to be connected with described first central processing unit, to form address decoding and inner parallel bus steering logic, described first central processing unit is opened with the cell isolation of other relative low speed by CPLD.
In video traffic dynamic information collecting equipment of the present invention, relative unit at a high speed comprises in the described master controller: the system storage that is connected with described first central processing unit; The unit of relative low speed comprises in the described master controller: system bootstrap FLASH storer, high-capacity FLASH data-carrier store, internal clocking and the house dog logic that is connected with described address decoding and inner parallel bus steering logic, internal system configuration structure detect logic, synchronous serial bus time division multiplex logic and multi-functional external interface unit.
In video traffic dynamic information collecting equipment of the present invention, be connected to system state indication logic on the described multi-functional external interface unit, also can connect in RS232 interface transceiver, RS485 interface transceiver, infrared serial line interface transceiver, the general parallel data grabbing card transceiver any one or a plurality of arbitrarily.
In video traffic dynamic information collecting equipment of the present invention, described digital video superposing control unit also adopts CPLD to realize, wherein, by the row-coordinate maker that is connected with described first Video Decoder, row coordinate maker produces the coordinate of present image point, and be fed to the regional determination circuit, thereby by it coordinate of present image point and surveyed area border are compared and to judge that this picture point is whether within surveyed area, according to result of determination the vision signal of the former digital video signal or the institute's Information Monitoring that superposeed is sent into video encoder again, finish the stack of image.
In video traffic dynamic information collecting equipment of the present invention, described high-speed synchronous serial data bus utilizes the frame synchronization host-host protocol, between described master controller and video image real-time processor, realize the transmitted in both directions of steering order and data, and utilize synchronous serial bus time division multiplex logic and synchronous serial bus to enable the time division multiplex that steering logic realizes the high-speed synchronous serial data bus.
Equipment of the present invention can detect the traffic of road in real time.When installing and use, this equipment does not destroy the road surface, and simple installation can realize that big zone detects, and maintenance cost is low, and can be according to the scale of the quantity flexible configuration system of occasion of using and video camera.Transport information such as this equipment can the inspection vehicle flow, car speed, the classification of vehicle length, lane occupancy ratio, queuing, delay, parking offense, hypervelocity, and these information are real-time transmitted to traffic control center so that in time carry out traffic dispersion, simultaneously these information can deposit database in, for traffic programme and control decision provide foundation.
Description of drawings
The invention will be further described below in conjunction with drawings and Examples, in the accompanying drawing:
Fig. 1 is the composition structural drawing of video traffic dynamic information collecting equipment of the present invention;
Fig. 2 is the basic sequential relationship synoptic diagram of high speed synchronous serial bus of the present invention;
Fig. 3 is the composition structural drawing of master controller among the present invention;
Fig. 4 is the schematic diagram of digital video stack among the present invention;
Fig. 5 is the composition structural drawing of video image real-time processor among the present invention;
Fig. 6 is the synoptic diagram of digital video store control logic of the present invention;
Fig. 7 installs four video cameras at the parting of the ways to form the synoptic diagram of traffic dynamic information collecting equipment;
Fig. 8 is the synoptic diagram of four-way video traffic dynamic information collecting equipment.
Embodiment
Based on opening, modularization, the number of channels of Video processing can flexible configuration consideration, equipment of the present invention adopts bus type topological structure, as shown in Figure 1, by the master controller 104 of equipment as Control Node, promptly as the control center of equipment, will be corresponding to the video image real-time processor 102 of each video channel basic collecting unit as whole traffic dynamic information collecting equipment, a plurality of video image real-time processors are connected with master controller by high-speed synchronous serial data bus 103, set up thus one distributed, hypotactic information acquisition equipment.A master controller can be controlled eight video image real-time processors at most, promptly can handle eight tunnel vision signals.When the practical video number of signals surpasses eight, can utilize the external serial interface RS232 of equipment or RS485 to carry out the system integration, can form large-scale, multiple spot distributed information collection system like this.
One, high speed serialization synchronous bus
The basis of video traffic dynamic information collecting equipment of the present invention is a high-speed synchronous universal serial bus 103, and this bus is made up of 6 signal wires, and its sign and definition are as table 1, and basic sequential relationship as shown in Figure 2.This bus is the internal data transfer bus of equipment, and its peak transfer rate can reach 20Mbps.It starts after the bus operation with frame mode bulk transfer data, can finish the transmission or the reception of packet automatically, does not disturb the work of CPU in the transmission course.This bus compatible 5V and 3.3V operating voltage, the driving force of its bus driver can reach 12 standard TTL (Transistor-TransistorLogic, i.e. transistor-transistor logic) load at least.Owing to adopt time division multiplexing mode, the actual scale that can constitute of this bus also depends on the transmission frequency quantity of institute's transfer data packets (p.s.) of the length and the data block of the data block of being transmitted between master controller 104 and the video image real-time processor 102.For bus, master controller is a time division multiplexing controller.Canonical system is a structure that realizes that 8 passage video images are handled in real time shown in Figure 1.Can set up distributed, a hypotactic video image real time processing system thus.Adopt a plurality of master controllers can also set up more massive multiple spot distributed video image real time processing system.
The sign and the definition of table 1-high-speed synchronous universal serial bus
| Title | Sign | Direction |
| Frame synchronization sends | ????FST | Source output |
| Send data sync clock | ????TSCK | Source output |
| Data send | ????Tx | Source output |
| Frame synchronization receives | ????FSR | The purpose input |
| Receive data sync clock | ????RSCK | The purpose input |
| Data Receiving | ????Rx | The purpose input |
Two, master controller
Among the present invention, the main task of master controller 104 is to control, coordinate duty, the mode of operation of each video image real-time processor 102 by synchronous serial bus, integrate, preserve the traffic information data that the video image real-time processor provides, finish the stack of indicators of vehicles and image, and for the data transmission of transport information detection provides external interface, its hardware configuration as shown in Figure 3.Described indicators of vehicles is a kind of like this sign: with the zone of significant color sign image detection, when not having vehicle to enter the image detection zone, indicate this zone (as yellow) with a kind of color; When vehicle enters surveyed area and is detected, indicate this zone (as green) with another kind of color, represent the result that detects intuitively with this.
In Fig. 3, first central processing unit 201 adopts speed to reach the high-performance digital signal processor of 100MIPS, for example adopt the TMS320VC54x family chip of Texas, USA instrument company (TI), it can satisfy following requirement: (1), realize the digital picture needed quick computing that superposes; (2), the order property of its high-speed cruising can be realized specific high-speed synchronous serial data bus agreement, thereby reach the real-time control to 1～8 road video image real-time processor.
The main task of the one DSP central processing unit 201 is:
(1), according to the state (having or not vehicle to enter) of surveyed area in user's setting and the video image real-time processor 102, finish the stack of indicators of vehicles and image by digital video superposing control unit 205;
(2), the analysis user order, and according to the work of order control of video image real-time processor;
(3), obtain the transport information that video image real-time processor 102 is gathered;
(4), to files such as video image real-time processor 102 download images Processing Algorithm, the configurations of video camera calculating parameter;
(5), receive user command, send result of calculation etc. by versatile interface unit 203 and external interface driver.
Among the present invention, first Video Decoder 204 adopts BT835, and the image source of BT835 is the simulating signal by the video camera 101 of the institute of the gauge tap on video image real-time processor gating.BT835 is converted into digital video signal with analog video signal, digital video signal is through the processing of digital video superposing control unit 205, directly output to video encoder 206 with the stack of former digital video signal and indicators of vehicles or with former digital video signal, by video encoder 206 digital video signal is converted into analog video signal output, shows by corresponding display equipment again.
Among the present invention, system storage 207 adopts static RAM (SRAM), and its main task is data such as needed various variablees, parameter in the storage system work.
Among the present invention, high-speed synchronous serial bus interface 218 main driving and the load matched that realize bus.Synchronous serial bus time division multiplex logic 218 is used for that bus is distributed to a plurality of video image real-time processors according to the time offshoot program of setting and uses.
Among the present invention, system bootstrap FLASH storer 207 is used to store the boot that powers on of master controller.Two kinds of contents of high-capacity FLASH data-carrier store 208 main storages: a kind of is the Flame Image Process operation program of each video image real-time processor; Another kind is the calculating parameter configuration file to each video image real-time processor, and when system powered on, master controller was given the video image real-time processor with these content delivery, starts the work of video image real-time processor then.
Among the present invention, the internal system configuration structure detects the self check that logic 216 is mainly used in each component units of system.Inner real-time clock and house dog logic 215 are used to monitor the operation of master controller, and when master controller internal processes generation gross error caused system's cisco unity malfunction, this partial logic will produce signal made system reenter the electrifying startup process.System state indication logic 210 according to self-detection result or the current task character driving LED lamp that carries out with the indication current working state.
Among the present invention, multi-functional external interface unit 203 is single chip architectures, and there are unit such as programmable serial communication controller, standard EPP, ECP parallel interface, infrared serial port controller its inside.Bus interface meets the ISA standard.This unit is mainly system and the parameter of external data interface so that system to be set is provided, obtains the detection data of system or carry out the large-scale system integration.Multiple electrical standard is selected by disposing different interface drivers in this unit, as can be seen from Figure 3, multi-functional external interface unit 203 has connected the system state indication logic 210 that is used to indicate system state, is used to connect RS232 interface transceiver 211, RS485 interface transceiver 212, infrared serial line interface transceiver 213 and the general parallel data grabbing card transceiver 214 of external interface.During practical application, can select one of them according to different application scenarios.
Among the present invention, address decoding and inner parallel bus steering logic 202 adopt CPLD (CPLD) to realize.It has determined the reference address of a DSP central processing unit 201 outside each logical blocks.It isolates the needed low speed bus operation of the relative low speed devices with other of high-speed bus of a DSP central processing unit 201, and these low speed devices comprise FLASH storer, state-detection logic, real-time clock and house dog logic, multi-functional external interface unit etc.
Among the present invention, digital video superposing control unit 205 also adopts CPLD to realize that the internal logic structure of this CPLD as shown in Figure 4.According to the surveyed area that the user sets, a DSP central processing unit 201 calculates the border in zone and gives regional determination circuit 407 as benchmark through overlap-add region control store 406 with this boundary position; Will from the row of first Video Decoder 204 synchronously, the pixel synchronous clock is fed to row-coordinate maker 409 and row coordinate maker 408 respectively, the output of these two coordinate makers is delivered to regional determination circuit 407 to determine that present image point is whether within surveyed area.If present image point is within surveyed area, then by superposing control signal control data selector switch 405, the data that desire is superposeed output to encoding video pictures device 204, otherwise the raw data of present image point is outputed to encoding video pictures device 204.The data type that is superposeed determined by the steering order of a DSP central processing unit 201, and the data of stack from the Data Generator 403 of 205 inside, digital video superposing control unit.Data Generator 403 produces two kinds of view data, the color image data when color image data when promptly vehicle does not enter surveyed area and vehicle enter surveyed area.In order to realize control and data synchronization, in the indoor design of digital video superposing control unit 205 digital synchronization signal regenerator 401, the work of the signal coordinating video encoder 206 that it produced.After a two field picture processing finishes, row, column coordinate maker 409,408 is reset to of the processing of the initial point of image coordinate system in order to the beginning next frame by reset control logic 404.
Three, video image real-time processor
Among the present invention, video image real-time processor 102 is used to finish functions such as the digitizing, Digital Image Processing, transport information extraction of video image, and its structure as shown in Figure 5.It is the digital signal processor of 10 nanoseconds that second central processing unit 301 among the figure adopts the instruction cycle, for example adopt the TMS320VC54x family chip of Texas, USA instrument company (TI), because its most of instruction is monocyclic, and have and be suitable for mass data is carried out the instruction set of computing and the addressing mode that adapts with it, so can satisfy the requirement that realtime graphic is handled.
Among the present invention, the interface of the peripheral components of the 2nd DSP central processing unit 301 and control thereof are realized by address decoding, steering logic and digital video store control logic circuit 302, it also is a CPLD (CPLD), can adopt the XC95xx family chip of U.S. Xilinx company.Its main task is each the assigns access address, unit for the video image real-time processor; And the time division multiplex of realization digital picture memory buffer, the central processing unit of high-speed cruising is cut apart with other logical gates of relative low speed, make the co-ordination of whole video processor energy, concrete principle of work will be described in detail below.
Among the present invention, data-carrier store 303 is external data storage spaces of the 2nd DSP central processing unit 301.For Flame Image Process, because handled data volume is very big, need bigger data space, but the 2nd DSP central processing unit 301 outside addressable address realms are limited, so adopted the data space addressable scope of 306 pairs the 2nd DSP central processing units of storage address expansion logic to expand in the present invention.The subprogram storage space that simultaneously also utilized this address extension logical extension.
Among the present invention, external program memory 304 and extender storer 305 are used to store and move some external treatment subroutine of the 2nd DSP central processing unit 301.The program of being moved in the external program memory 304 mainly is subroutines such as the initialization, self check, low speed I/O visit of video image real-time processor, and is lower to the requirement of real-time; Some not high special subroutine of storage frequency of utilization in the extender storer 305, as telecommunication control program etc., the travelling speed of program is lower than the travelling speed of program in the external program memory 304 in the extender storer 305, when the program of calling extension program storer 305, need to use call instruction far away.
Among the present invention, second Video Decoder 308 adopts the BT835 chip, the gray scale of each pixel is represented with 8 bit digital quantity, in a certain some digital picture of output, synchronization pulse with this point of output, utilize the reference address that this synchronizing pulse can control figure image buffer memory 307, thereby under the situation that does not have the 2nd DSP central processing unit 301 to intervene, image is stored in the digital picture memory buffer 307.
Among the present invention, state indicating member 309 is made up of several LED.When the video image real-time processor carries out initial self check, can indicate the result of self check; When operate as normal, according to the order indicating operating status and the order operation result of master controller.
Among the present invention, high-speed synchronous serial bus interface 310 is used to realize driving and the load matched to bus.Synchronous serial bus enables steering logic 319 under the control of master controller 104, opens the synchronous bus driver according to the sequential of setting, to realize the time division multiplex of bus.
Utilize multi-channel video image real time processing system that video image real-time processor of the present invention formed as shown in Figure 1, in order to make video image real-time processor of the present invention can be applicable to this system, the high-speed synchronous serial bus interface 310 of above-mentioned video image real-time processor is connected with master controller 104 by high-speed synchronous universal serial bus 103, and a plurality of video image real-time processors 102 are this bus of time division multiplex under the instruction of master controller 104.This bus is used for result's (for example transport information such as vehicle flowrate, car speed, vehicle length) of images processing and the real-time video processor control command of coming autonomous controller, and is not used in the real-time Transmission digital picture.
The key issue that system shown in Fig. 1 will solve is real-time operation and the processing that can finish when guaranteeing the realtime graphic storage image.The design's solution is based on following true and requirement:
(1), catches image to satisfy system's accuracy of detection required time resolution with the speed of 30 frame/seconds (TSC-system) or 25 frame/seconds (PAL-system);
(2), have very strong temporal correlation and spatial coherence between the strange field of same two field picture and the even field picture;
(3), alleviate image as far as possible and store the burden of bringing to the 2nd DSP central processing unit.
For this reason, the video storage steering logic that has adopted digital picture memory buffer 307 among the present invention and realized by CPLD 302, giving the special circuit that second Video Decoder 308 driven with the image store tasks finishes, when image carries out storage operation, do not influence the 2nd DSP central processing unit the image of having caught is carried out computing.Fig. 6 has provided the logic diagram of this design, and wherein sampling controller 311, address reseting logic 312, address generator 313, sequential match circuit 314, address bus change-over switch 315 and the data bus change-over switch 316 in the frame of broken lines is the different function units in address decoding, steering logic and the digital video store control logic circuit 302.
In Fig. 6, line synchronizing signal, field sync signal, the pixel synchronizing clock signals of 308 outputs of second Video Decoder are sent to sampling controller 311, sampling controller is selected effective pixel synchronous clock and it is fed to address generator 313, address generator produces the address of effective picture point in digital picture memory buffer 307, and this address is connected to the digital picture memory buffer by address bus change-over switch 315.Simultaneously, line synchronizing signal, field sync signal, pixel synchronizing clock signals pass through write signal and the chip selection signal that suitable logic produces the digital picture memory buffer, and selected effective original data is stored in the digital picture memory buffer.When an image sampling end cycle, line synchronizing signal, field sync signal produce reset signal through address reseting logic 312 address generator 313 are resetted, and produce look-at-me simultaneously and notify the 2nd DSP central processing unit 301.Have no progeny in the response of the 2nd DSP central processing unit, to switch address bus change-over switch 315 and data bus selector switch 316, take over the access right of digital picture memory buffer, the image of wherein catching is transferred in the data-carrier store 303 apace, when end of transmission (EOT), the 2nd DSP central processing unit discharges the digital picture memory buffer, and control is given back second Video Decoder 308.Second Video Decoder begins to carry out the next one sampling period.When carrying out the next image sampling cycle, the 2nd DSP central processing unit will carry out analyzing and processing to the image that the last time gathers, thereby obtain needed information.As seen, in the video image real-time processor of the present invention, the acquisition procedure of treatment of picture process and image is independently, and the burden that the acquisition procedure of image brings for the 2nd DSP central processing unit 301 is very little.Sequential match circuit 314 among the figure is used for the time delay of compensating control signal and data-signal.
This equipment can detect the traffic of road in real time.When installing and use, this equipment does not destroy the road surface, and simple installation can realize that big zone detects, and maintenance cost is low, and can be according to the scale of the quantity flexible configuration system of occasion of using and video camera.This equipment can the inspection vehicle flow, car speed, vehicle length, lane occupancy ratio, queuing, delay, parking offense, hypervelocity, transport information such as line more, and these information are real-time transmitted to traffic control center so that in time carry out traffic dispersion, simultaneously these information can deposit database in, for traffic programme and control decision provide foundation.
For a typical crossroad, 4 video cameras can be installed, the installation site is as shown in Figure 7.At this moment can be configured to by a master controller and 4 typical application systems that the video image real-time processor is formed, as shown in Figure 8.Wherein, every video camera 101 correspondences are connected on the video image real-time processor 102, the RS232 interface of equipment is connected with notebook computer 106, the video-out port of equipment also is connected on the notebook computer by video interface equipment 105, the user can be provided with by surveyed area, measuring ability, the detected parameters of notebook computer to each video camera of equipment, when all video cameras be set up finish after, can start collecting device work by the instruction that notebook computer sends.Disconnect the RS232 interface, equipment is independent operating just.The data storage that is detected perhaps is sent to traffic control center by network in the FLASH storer of master controller.
When traffic information collection is carried out in a plurality of crossings or highway section, can such checkout equipment be installed at each check point, a plurality of equipment are connected to long-range traffic control center by network, control terminal by command centre is provided with each system, each video camera, and can will store, filter, report to the police, issue to the data of command centre, set up large-scale traffic information collection and control system by Network Transmission.
Claims (9)
1, a kind of video traffic dynamic information collecting equipment, comprise a plurality of video cameras (101) that are used to take the road traffic real-time status, it is characterized in that, also comprise with described video camera connecting one to one, being used for the video image that the video camera that is attached thereto is exported is handled in real time to obtain a plurality of video image real-time processors (102) of required transport information; Be used to coordinate the duty of described each video image real-time processor and store the master controller (104) of the transport information of being gathered; And the bus backplane that is used to connect described master controller (104) and each video image real-time processor (102), described bus backplane adopts high-speed synchronous serial data bus (103), for the exchanges data between master controller and the video image real-time processor provides physical connection.
2, video traffic dynamic information collecting equipment according to claim 1, it is characterized in that, described video image real-time processor (102) comprises second Video Decoder (308) that is connected with described video camera (101), be used for decoded original data is handled to obtain second central processing unit (301) of required transport information, the data-carrier store (303) that is connected with described second central processing unit, and be connected with described second central processing unit and be used to export the transport information of being gathered and the output interface (310) of digital video image, wherein, described second central processing unit adopts digital signal processor at a high speed, the digital picture memory buffer (307) that also comprises the original data that is used to store described image decoder (308) output in the described video image real-time processor, and adopt an address decoding of forming by CPLD, steering logic and digital video store control logic circuit (302) are as the performer of interface and steering logic, described address decoding, steering logic and digital video store control logic circuit (302) connect described image decoder (308), digital picture memory buffer (307) and data-carrier store (303) separate second central processing unit (301) and described second image decoder (308) and the digital picture memory buffer (307) of described high speed on control timing.
3, video traffic dynamic information collecting equipment according to claim 2, it is characterized in that, described address decoding, the inside of steering logic and digital video store control logic circuit (302) comprises sampling controller (311), address reseting logic (312), address generator (313), sequential match circuit (314), address bus change-over switch (315) and data bus change-over switch (316), these internal components are under the control of described second Video Decoder (308), can the original data of catching be stored in the described digital picture memory buffer (307) automatically, under the control of described second central processing unit (301), described original data is sent in the described data-carrier store (303) fast then.
4, video traffic dynamic information collecting equipment according to claim 3, it is characterized in that, described output interface (310) is the high-speed synchronous serial bus interface, can be used for connecting the transport information that described high-speed synchronous universal serial bus (103) is gathered with output, and realize driving and load matched described high-speed synchronous universal serial bus.
5, video traffic dynamic information collecting equipment according to claim 1 is characterized in that, described master controller (104) comprises first central processing unit (201) that adopts high speed digital signal processor; Be connected to the high-speed synchronous serial bus interface (218) of described video image real-time processor (102) by described high-speed serial bus (103); First Video Decoder (204) that is connected with described video camera (101) by the gauge tap on the video image real-time processor; The transport information that be connected with the output terminal of first Video Decoder (204) and first central processing unit (201), is used for the to be gathered digital video superposing control unit (205) on the present image that is added to; And the video encoder (206) that is connected with the output terminal of digital video superposing control unit (205); Wherein also adopt one to be connected with described first central processing unit (201), to form address decoding and inner parallel bus steering logic (202), described first central processing unit (201) is opened with the cell isolation of other relative low speed by CPLD.
6, video traffic dynamic information collecting equipment according to claim 5 is characterized in that, relative unit at a high speed comprises in the described master controller (104): the system storage (207) that is connected with described first central processing unit; The unit of relative low speed comprises in the described master controller (104): the system bootstrap FLASH storer (208) that is connected with described address decoding and inner parallel bus steering logic (202), high-capacity FLASH data-carrier store (209), internal clocking and house dog logic (215), internal system configuration structure detect logic (216), synchronous serial bus time division multiplex logic (217) and multi-functional external interface unit (203).
7, video traffic dynamic information collecting equipment according to claim 6, it is characterized in that, be connected to system state indication logic (210) on the described multi-functional external interface unit (203), also can connect in RS232 interface transceiver (211), RS485 interface transceiver (212), infrared serial line interface transceiver (213), the general parallel data grabbing card transceiver (214) any one or a plurality of arbitrarily.
8, video traffic dynamic information collecting equipment according to claim 5, it is characterized in that, described digital video superposing control unit (205) also adopts CPLD to realize, wherein, by the row-coordinate maker (409) that is connected with described first Video Decoder (204), row coordinate maker (408) produces the coordinate of present image point, and be fed to regional determination circuit (407), thereby by it coordinate of present image point and surveyed area border are compared and to judge that this picture point is whether within surveyed area, according to result of determination the vision signal of the former digital video signal or the institute's Information Monitoring that superposeed is sent into video encoder (206) again, finish the stack of image.
9, video traffic dynamic information collecting equipment according to claim 1, it is characterized in that, described high-speed synchronous serial data bus (103) utilizes the frame synchronization host-host protocol, between described master controller (104) and video image real-time processor (102), realize the transmitted in both directions of steering order and data, and utilize synchronous serial bus time division multiplex logic (217) and synchronous serial bus to enable the time division multiplex that steering logic (319) realizes high-speed synchronous serial data bus (103).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02134324 CN1187724C (en) | 2002-07-04 | 2002-07-04 | Video traffic dynamic information collecting equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02134324 CN1187724C (en) | 2002-07-04 | 2002-07-04 | Video traffic dynamic information collecting equipment |
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| Publication Number | Publication Date |
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| CN1466110A true CN1466110A (en) | 2004-01-07 |
| CN1187724C CN1187724C (en) | 2005-02-02 |
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| CN 02134324 Expired - Fee Related CN1187724C (en) | 2002-07-04 | 2002-07-04 | Video traffic dynamic information collecting equipment |
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| CN101729872B (en) * | 2009-12-11 | 2011-03-23 | 南京城际在线信息技术有限公司 | Video monitoring image based method for automatically distinguishing traffic states of roads |
| CN102801211A (en) * | 2012-06-13 | 2012-11-28 | 南京南瑞继保电气有限公司 | Data concentrator with blade-type framework |
| CN102982783A (en) * | 2012-12-10 | 2013-03-20 | 广东威创视讯科技股份有限公司 | Video processor and video request processing method thereof |
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| CN101729872B (en) * | 2009-12-11 | 2011-03-23 | 南京城际在线信息技术有限公司 | Video monitoring image based method for automatically distinguishing traffic states of roads |
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| CN103730000A (en) * | 2012-10-12 | 2014-04-16 | 姜廷顺 | Method and system for automatically recording response speed for emergency |
| CN103730000B (en) * | 2012-10-12 | 2016-01-20 | 姜廷顺 | The method and system of automatic record accident reaction velocity |
| CN103794043B (en) * | 2012-11-02 | 2016-03-02 | 姜廷顺 | Public security traffic accident is received a crime report auto-allocation method and system |
| CN103794043A (en) * | 2012-11-02 | 2014-05-14 | 姜廷顺 | Police traffic emergency alarm receiving automatic distribution method and system |
| CN102982783B (en) * | 2012-12-10 | 2015-02-04 | 广东威创视讯科技股份有限公司 | Video processor and video request processing method thereof |
| CN102982783A (en) * | 2012-12-10 | 2013-03-20 | 广东威创视讯科技股份有限公司 | Video processor and video request processing method thereof |
| CN103916641A (en) * | 2014-04-22 | 2014-07-09 | 浙江宇视科技有限公司 | Queue length calculating method and device |
| CN107516064A (en) * | 2016-04-19 | 2017-12-26 | 通用汽车环球科技运作有限责任公司 | Use the parallel scene unit detection around camera chain |
| CN110576867A (en) * | 2018-06-08 | 2019-12-17 | 铃木株式会社 | Vehicle driving support device |
| CN110576867B (en) * | 2018-06-08 | 2022-11-25 | 铃木株式会社 | Vehicle driving support device |
| CN113610883A (en) * | 2021-04-30 | 2021-11-05 | 新驱动重庆智能汽车有限公司 | Point cloud processing system and method, computer device, and storage medium |
| CN113610883B (en) * | 2021-04-30 | 2022-04-08 | 新驱动重庆智能汽车有限公司 | Point cloud processing system and method, computer device, and storage medium |
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