CN1450621A - Method for eliminating stress and damage while forming isolation component - Google Patents
Method for eliminating stress and damage while forming isolation component Download PDFInfo
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- CN1450621A CN1450621A CN 02105884 CN02105884A CN1450621A CN 1450621 A CN1450621 A CN 1450621A CN 02105884 CN02105884 CN 02105884 CN 02105884 A CN02105884 A CN 02105884A CN 1450621 A CN1450621 A CN 1450621A
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Abstract
This invention provides a method for eliminating stress and damage when forming a channeled isolation element including: providing a semi-conductor basic material to be etched to form a channeled structure, processing the channeled structure with high temperature annealing or quick heat annealing to eliminate stress of the channeled structure to reach the aim of avoiding the reduction of the reliability, semiconductive elements or annealing processing to a sidewall oxidation layer to eliminate the stress generated by the oxidation layer of the channeled structure.
Description
(1) technical field
The present invention is about a kind of method that eliminates stress and damage when forming isolated component, particularly about a kind of method that eliminates stress and damage when forming the shallow trench isolated component.
(2) background technology
Using shallow trench isolation to come isolated component from (shallow-trench isolation) technology in integrated circuit manufacture process is the way of using always.Generally speaking, on the semiconductor ground, use silicon nitride, use the anisotropic etching processing procedure to form precipitous groove as shade.Then, fill up groove forming the shallow trench isolated component with oxide, its surface is that the surface with ground has same level height.
Figure 1A to Fig. 1 D be conventional method form shallow trench isolation from generalized section.Shown in Figure 1A, on silicon base material 110, form a pad oxide 122 (pad oxide layer) with protection silicon base material 110, this pad oxide 122 can remove before forming sacrificial oxide layer.Then, on pad oxide 122, form a silicon nitride layer 124 with chemical vapour deposition technique.Then, with a photoresist layer 128 with pattern as shade carrying out etching program on the silicon base material 110 on silicon base material 110, to form some groove structures 130, after etching, remove photoresist layer 128.
With reference to Figure 1B, on the sidewall of groove structure 130, form sidewall oxide 131 with the method for thermal oxidation, then, in the surface of silicon base material 110 and groove structure 130, fill out one silica layer 132.
With reference to Fig. 1 C, at compact substance process (densification process), AN or reoxidize with after forming shallow trench isolated component 134 with dried oxygen, wet oxygen sidewall for example removes silicon oxide layer 132 on silicon nitride layer 124 with chemical and mechanical grinding method.
With reference to Fig. 1 D, utilize hot phosphoric acid to divest silicon nitride layer 124.
Yet, described conventional method is applied to than the high density integrated circuit having manufacturing, for example during 0.25 micron system, stress is a factor that need take in.For instance, when the ditch trench etch, may cause stress and infringement, and then cause the reduction of the reliability of semiconductor element the active area of semiconductor element.
(3) summary of the invention
The purpose of this invention is to provide a kind of method that eliminates stress when forming the shallow trench isolated component with damage, eliminate by the stress effect that is produced in the etching in the shallow trench isolated component forming process so that high annealing is applied to.
Another object of the present invention is to provide a kind of method that eliminates stress when forming the shallow trench isolated component with damage, to prevent the decline of the reliability that the trench isolations element is produced when forming.。
Another purpose of the present invention is to provide a kind of method that eliminates stress when forming the shallow trench isolated component with damage, forms the decline of the reliability that is caused with the sidewall oxide that prevents the trench isolations element.
According to above-described purpose, trench isolations element of the present invention eliminates stress when forming and the method for damaging, and it comprises at least: the semiconductor ground is provided; The etching semiconductor ground is to form a groove structure; And annealing in process, for example handle groove structure, so as to eliminating the stress of this groove structure, reach the purpose of avoiding the semiconductor element reliability to reduce with high annealing or rapid thermal annealing mode.Also can be in forming a sidewall oxide after on the sidewall of groove structure, the annealing in process sidewall oxide is so as to eliminating the stress that oxide layer produced of groove structure.
For further specifying purpose of the present invention, design feature and effect, the present invention is described in detail below with reference to accompanying drawing.
(4) description of drawings
Figure 1A to Fig. 1 D is a succession of generalized section that forms the shallow trench isolated component with conventional method; And
Fig. 2 A to Fig. 2 D is for carrying out a succession of generalized section that groove structure is handled with the inventive method.
(5) embodiment
Method of the present invention can be widely applied in many semiconductor design, and can utilize many different semi-conducting materials to make, when the present invention illustrates the inventive method with a preferred embodiment, the personage in known this field will be appreciated that many steps can change, material and impurity are also replaceable, and these general replacements also do not break away from spirit of the present invention and category far and away.
Secondly, the present invention is described in detail as follows with schematic diagram, and when the embodiment of the invention was described in detail in detail, the profile of expression semiconductor structure can be disobeyed general ratio and be done local the amplification in order to explanation in manufacture of semiconductor, so should be with this as qualification.In addition, in the making of reality, should comprise the three dimensions size of length, width and the degree of depth.
In this embodiment, a kind of method that eliminates stress when forming the shallow trench isolated component with damage to avoid the reliability reduction of semiconductor element when a trench isolations element forms, is characterized in comprising at least: the semiconductor ground is provided; Form a pad oxide on semiconductor substrate; Form a dielectric layer, for example silicon nitride layer is on pad oxide; Form a photoresist layer on dielectric layer, the some of photoresist layer exposed dielectric layer is in order to form the groove structure part; The part that removes pad oxide and dielectric layer is to expose the part of semiconductor substrate; The semiconductor substrate that etch exposed goes out is to form groove structure; And annealing in process, for example handle groove structure with high annealing or rapid thermal annealing mode, reduce so as to the reliability of avoiding semiconductor element.Then can form a sidewall oxide again on a sidewall of groove structure; And the annealing in process sidewall oxide, so as to eliminating the stress that oxide layer produced of groove structure.
One embodiment of the invention are with reference to Fig. 2 A to Fig. 2 C.At first according to Fig. 2 A, provide semiconductor ground 10, for example silicon base material forms a pad oxide 22 thereon with protection semiconductor substrate 10.Utilize the method for chemical vapour deposition (CVD) on pad oxide 22, to form a silicon nitride layer 24.On silicon nitride layer 24, form a photoresist layer 28 with pattern with as shade.
Then, with reference to Fig. 2 B, silicon nitride layer 24, pad oxide 22 and semiconductor substrate 10 are carried out etching step to form a groove structure 30 on semiconductor substrate.Photoresist layer 28 removes after etching step is finished.
With reference to Fig. 2 C, a committed step of the present invention shown in the figure: before a sidewall oxide 31 forms, with groove structure 30 with high annealing or quick thermal annealing process.The sidewall of groove structure 30 may cause structural damage in the groove etching process, this structural damage can cause the reliability of semiconductor element to reduce.And the processing of high annealing or rapid thermal annealing can be repaired the structural damage of the sidewall of groove structure 30, and then avoids the reliability of semiconductor element to reduce.And the processing of this high annealing or rapid thermal annealing can comprise in the environment of nitrogen in one and carries out.Then, on the sidewall of groove structure 30, form sidewall oxide 31 with suitable method.
Also one of committed step of the present invention shown in Fig. 2 D.The deposition one oxide layer 32 before, with sidewall oxide 31 with high annealing or quick thermal annealing process.The processing of high annealing or rapid thermal annealing can reduce the stress that oxide layer produces, and avoids the reliability of semiconductor element to reduce.And the processing of this high annealing or rapid thermal annealing can comprise in one and carries out in the environment of nitrogen, and operating temperature is approximately between 800 ℃ to 1200 ℃, and the operation time-histories is approximately between 1 minute to 1 hour.Then, in groove structure 30 with on the silicon nitride layer 24, insert oxide layer 32.
Certainly, those of ordinary skill in the art will be appreciated that, above embodiment is used for illustrating the present invention, and be not to be used as limitation of the invention, as long as in connotation scope of the present invention, all will drop in the scope of claims of the present invention variation, the modification of the above embodiment.
Claims (10)
1. one kind is applied to eliminate stress and the method for damaging when a trench isolations element forms, and it is characterized in that, comprising:
The semiconductor ground is provided;
This semiconductor substrate of etching is to form a groove structure; And
This groove structure of annealing in process is so as to eliminating the stress of this groove structure.
2. the method that eliminates stress and damage as claimed in claim 1 is characterized in that described annealing is included in the environment that comprises nitrogen at least carries out high annealing.
3. the method that eliminates stress and damage as claimed in claim 1 is characterized in that described annealing is included in the environment that comprises nitrogen at least carries out rapid thermal annealing.
4. the method that eliminates stress and damage as claimed in claim 1 is characterized in that described etching step comprises at least:
Form a pad oxide on this semiconductor substrate;
Form a dielectric layer on this pad oxide;
Form a photoresist layer on this dielectric layer, this photoresist layer exposes the some of this dielectric layer in order to form this groove structure part;
This part that removes this pad oxide and this dielectric layer is to expose this part of this semiconductor substrate; And
This semiconductor substrate that etch exposed goes out is to form this groove structure.
5. the method that eliminates stress and damage as claimed in claim 4 is characterized in that described dielectric layer comprises a silicon nitride layer at least.
6. the method that eliminates stress and damage as claimed in claim 1 is characterized in that also comprise with an insulating material and fill up this groove structure to form this trench isolations element, wherein, this insulating material comprises silica at least.
7. one kind is applied to eliminate stress and the method for damaging when a trench isolations element forms, and it is characterized in that, comprising:
The semiconductor ground is provided;
This semiconductor substrate of etching is to form a groove structure;
This groove structure of annealing in process is so as to eliminating the stress of this groove structure;
Form a sidewall oxide on a sidewall of this groove structure; And
This sidewall oxide of annealing in process is so as to eliminating the stress that oxide layer produced of this groove structure.
8. as claimed in claim 7 being applied to eliminates stress and the method for damaging when a trench isolations element forms, and it is characterized in that, also comprises with an insulating material and fills up this groove structure to form this trench isolations element.
9. as claimed in claim 7 being applied to eliminates stress and the method for damaging when a trench isolations element forms, and it is characterized in that described annealing is included in the environment that comprises nitrogen at least carries out high annealing.
10. as claimed in claim 7 being applied to eliminates stress and the method for damaging when a trench isolations element forms, and it is characterized in that described annealing is included in the environment that comprises nitrogen at least carries out rapid thermal annealing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02105884 CN1450621A (en) | 2002-04-09 | 2002-04-09 | Method for eliminating stress and damage while forming isolation component |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02105884 CN1450621A (en) | 2002-04-09 | 2002-04-09 | Method for eliminating stress and damage while forming isolation component |
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| CN1450621A true CN1450621A (en) | 2003-10-22 |
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| CN 02105884 Pending CN1450621A (en) | 2002-04-09 | 2002-04-09 | Method for eliminating stress and damage while forming isolation component |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1323422C (en) * | 2003-11-04 | 2007-06-27 | 国际商业机器公司 | Oxidation method for altering a film structure and CMOS transistor structure formed therewith |
| CN102412157A (en) * | 2011-04-29 | 2012-04-11 | 上海华力微电子有限公司 | ACT dummy insert method used for raising semiconductor device performance |
| CN102931055A (en) * | 2012-10-10 | 2013-02-13 | 中国科学院微电子研究所 | Multi-layer graphene thinning method |
| WO2013143033A1 (en) * | 2012-03-29 | 2013-10-03 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| US8829642B2 (en) | 2012-03-29 | 2014-09-09 | The Institute of Microelectronics, Chinese Academy of Science | Semiconductor device and method for manufacturing the same |
| CN104733375A (en) * | 2013-12-20 | 2015-06-24 | 中芯国际集成电路制造(上海)有限公司 | Damascene structure manufacturing method |
| CN116525456A (en) * | 2023-07-03 | 2023-08-01 | 粤芯半导体技术股份有限公司 | MOSFET device manufacturing method based on TDDB optimization |
-
2002
- 2002-04-09 CN CN 02105884 patent/CN1450621A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1323422C (en) * | 2003-11-04 | 2007-06-27 | 国际商业机器公司 | Oxidation method for altering a film structure and CMOS transistor structure formed therewith |
| CN102412157A (en) * | 2011-04-29 | 2012-04-11 | 上海华力微电子有限公司 | ACT dummy insert method used for raising semiconductor device performance |
| CN102412157B (en) * | 2011-04-29 | 2014-04-30 | 上海华力微电子有限公司 | ACT dummy insert method used for raising semiconductor device performance |
| WO2013143033A1 (en) * | 2012-03-29 | 2013-10-03 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| US8829642B2 (en) | 2012-03-29 | 2014-09-09 | The Institute of Microelectronics, Chinese Academy of Science | Semiconductor device and method for manufacturing the same |
| CN102931055A (en) * | 2012-10-10 | 2013-02-13 | 中国科学院微电子研究所 | Multi-layer graphene thinning method |
| CN102931055B (en) * | 2012-10-10 | 2015-07-29 | 中国科学院微电子研究所 | A kind of thining method of multi-layer graphene |
| CN104733375A (en) * | 2013-12-20 | 2015-06-24 | 中芯国际集成电路制造(上海)有限公司 | Damascene structure manufacturing method |
| CN104733375B (en) * | 2013-12-20 | 2018-08-10 | 中芯国际集成电路制造(上海)有限公司 | The production method of damascene structure |
| CN116525456A (en) * | 2023-07-03 | 2023-08-01 | 粤芯半导体技术股份有限公司 | MOSFET device manufacturing method based on TDDB optimization |
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