CN1435872A - Wafer grade testing and salient point process and chip struture with testing pad - Google Patents
Wafer grade testing and salient point process and chip struture with testing pad Download PDFInfo
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- CN1435872A CN1435872A CN 03120575 CN03120575A CN1435872A CN 1435872 A CN1435872 A CN 1435872A CN 03120575 CN03120575 CN 03120575 CN 03120575 A CN03120575 A CN 03120575A CN 1435872 A CN1435872 A CN 1435872A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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Abstract
A wafer-class test and salient point technology and the chip structure with test pads are disclosed. The multiple test pads as the test points for analyzing and debugging the circuits are arranged on the active surface of wafer, and electrically connected with relative flip-chip welding pads of chip. The probe can directly contact the surface of test pads for testing the wafer. Based on the test result, it is determined that if the repair lines are cut off via repair window. Finally the protecting layer and salient points are sequentially generated on the active surface of wafer, which is the cut to form more chips.
Description
Technical field
The present invention relates to a kind of test and packaging technology, and be particularly related to test and the bump process of a kind of wafer scale (wafer level).
Background technology
Along with the fast development of semiconductor technology, and improve constantly down in the market demand at the product of semi-conductor packaging, more accurate and advanced semi-conductor electricity sub-element constantly develops out.With regard to (encapsulation and test) surveyed in present semi-conductive manufacturing and envelope, at integrated circuit (Integral Circuit, IC) after design is finished, then carry out semi-conductive FEOL, it mainly comprises the manufacturing of integrated circuit of wafer and test etc., then by wafer cutting back formed chip (die), again for example in the mode of lead-in wire bonding (wire bond) or flip-chip (flip chip bond), make the flip-chip weld pad (bonding pad) on active surface (active surface) of chip be electrically connected to the contact of carrier (carrier), wherein carrier for example is substrate (substrate) or lead frame (lead-frame) etc.Chip-packaging structure with the flip-chip kenel is an example, can form a plurality of flip-chip weld pads earlier on the active surface of chip, then forms a salient point (bump) again on each flip-chip weld pad respectively.Therefore, the flip-chip weld pad on the active surface of chip can be via salient point, and electricity and be mechanically attached to the contact of substrate respectively, makes the signal of telecommunication of integrated circuit of chip can be connected to exterior electrical components by the transmission of carrier.
Please refer to Figure 1A～1C, wherein Figure 1A illustrates the partial top view on the active surface of existing wafer, and Figure 1B illustrates the generalized section along the I-I line of Figure 1A, and Fig. 1 C illustrates the generalized section along the II-II line of Figure 1A.Shown in Figure 1A and 1B, wafer 100 has one active surperficial 102, the one side of a plurality of active elements of configuration (active device) 104 of wherein active surperficial 102 general reference wafers 100, these active elements 104 are then respectively by metal interconnecting (metalinterconnection) 106, and be electrically connected to each other, and be electrically connected to the flip-chip weld pad 108 on the active surface of wafer 100, and according to the difference on the electric work energy, flip-chip weld pad 108 can be used as signal contact, power supply contact or ground contact etc.Wafer 100 with flip-chip (flip chip bonding) is an example; before carrying out salient point (bump) technology; active surperficial 102 of wafer 100 can cover a protective layer (passivation) 110 earlier usually; and protective layer 110 can cover repairing circuit (fuse line) 112 and repair window (fuse window) 114; and expose flip-chip weld pad 108; and a plurality of salient points 120 are disposed at respectively on each flip-chip weld pad 108, in order to contact as electrical connection exterior electrical components (not shown).
Shown in Figure 1B, electricity condition for the internal integrated circuit of testing wafer 100, behind the metal interconnecting 106 that forms wafer 100 inside, prior art is normally utilized active surperficial 102 flip-chip weld pad 108 of wafer 100 or the contact that salient point 120 is used as testing.It should be noted that, existing test mode is utilized the tops of a plurality of probes (probe tip) 12 corresponding these salient points 120 of contact that the array-like of vertical probe carb (vertical probe card) 10 arranges, in order to the circuit analysis of carrying out chip 100 and the test of debug isoelectric state.
Shown in Fig. 1 C, after the electrical testing of the internal integrated circuit of wafer 100, lost efficacy if detect partial circuit, the mode of circuit mending (repair) is to utilize laser to block the repairing circuit (fuse line) 112 of the correspondence of wafer 100, and replaces the inefficacy circuit with another group stand-by circuit.Therefore, existing wafer 100 all can design many group stand-by circuits, and design the inside of many repairing circuits 112 in wafer 100, and utilize the structure of the top of a repairing window 114 relative thinning repairing circuits 112, so that laser blocks the repairing circuit of desiring to block 112, make stand-by circuit can replace the inefficacy circuit.It should be noted that when repairing the inefficacy circuit, the structure of the top of necessary first thinning repairing circuit 112 is passed the structure of the top of repairing circuit 112 to help laser, and then blocked repairing circuit 112.Therefore, before repairing the inefficacy circuit, can remove local protective layer 110 in advance, repair window 114, use the structural thickness of the top of reducing repairing circuit 112 in order to expose.Afterwards, block the repairing circuit of desiring to block 112 with laser again, and after finishing circuit mending, form another protective layer 110a (or protective layer) again and cover above-mentioned repairing window 114.Yet, in the middle of the process of repairing the inefficacy circuit, protective layer 110 perforate again, in order to exposing the repairing window, and the partial structurtes of the top of thinning repairing circuit relatively so will prolong the process cycle of the test and the encapsulation of wafer 100 relatively.
Please also refer to Figure 1B, 1C, 2, wherein Fig. 2 illustrates the flow chart of the test and the encapsulation of existing wafer scale.The test of existing wafer and bump process are roughly as follows: at first shown in step S11, form a plurality of flip-chip weld pads 108 in active surperficial 102 of wafer 100, then shown in step S12, form at least one repairing window 114 in active surperficial 110 of wafer 100.Then shown in step S13, form protective layer 110 active surperficial 102 in wafer 100, wherein protective layer 110 exposes flip-chip weld pad 108.Then shown in step S14, carry out bump process, to form salient point 120 on the flip-chip weld pad 108 of wafer 100.Then shown in step S15, as test contacts, carry out the test of the electricity condition of wafer 100 with these salient points.Then shown in step S16, remove local protective layer 110, repair the window 114 thereby the partial structurtes of the top of relative thinning repairing circuit 112 in order to expose.Then shown in step S17, the repairing circuit 112 that utilizes laser to block to desire to block.Then shown in step S18, fill up repairing window 114 with dielectric material.It should be noted that the repairing window 114 that after removing local protective layer 110, is exposed, must once more this be repaired window 114 and be filled up, so will increase processing step, thereby increase process cycle and technology cost relatively.
On the other hand, please refer to Figure 1B, because salient point 110 is in reflow (reflow) when being shaped to orbicule, the error amount of the coplane degree at its top (co-planarity) is about 50 microns, and the coplane degree error amount on the top of these probes 12 also can reach 50 microns.Therefore, when the top of these probes 12 contacts with the salient point 120 of sphere, fail the top of contact salient point 120 for fear of part probe 12, thereby the accuracy of influence test, so the probe of increase vertical probe carb 10 is pressed on the strength of salient point 120 for 12 times relatively.Yet the probe 12 of probe 10 excessively presses down the result of (over-travel), will cause the damage of the internal integrated circuit of wafer 100, thereby has a strong impact on the normal operation of the internal integrated circuit of wafer 100.
Summary of the invention
Therefore, purpose of the present invention just provides a kind of test and bump process of wafer scale, in order to reducing its processing step, and then reduces technology cost and process cycle.
In addition, another order of the present invention is to provide a kind of chip structure with testing cushion, it mainly is to utilize a plurality of testing cushion that are disposed at the active surface of wafer to be used as test contacts, so that the top of probe can be come the electricity condition of the internal integrated circuit of testing wafer by the engaged test pad, thereby the exert pressure degree of the internal integrated circuit that destroys wafer of the top that reduces probe.
For realizing above-mentioned purpose of the present invention, the present invention proposes a kind of test and bump process of wafer scale, be applicable to a wafer, wherein wafer has at least one repairing circuit, it is embedded in the inside of wafer, and wafer has more an active surface, and the test and the bump process of this wafer scale comprises the following steps: that at least (a) at least one flip-chip weld pad of configuration and at least one testing cushion are on active surface, and testing cushion is positioned at the periphery on active surface, and is electrically connected to the flip-chip weld pad; (b) form at least one repairing window on active surface, and repair the active surface that window is depressed in wafer relatively, in order to the partial structurtes between thinning repairing circuit and the active surface; (c) come the electricity condition of testing wafer via testing cushion, and obtain a test result; (d) according to test result, whether decision blocks repairing circuit via repairing window; (e) protective layer that forms patterning is on the active surface of wafer, and wherein protective layer is filled up and repaired window and coverage test pad, but exposes the flip-chip weld pad; And (f) form a salient point on the flip-chip weld pad.
According to the preferred embodiments of the present invention, on when being set forth in step (c), more comprise via the tip of at least one probe of a cantalever type probe card and come the engaged test pad, in order to be electrically connected to the internal circuit of wafer.In addition, wafer has more at least one trace, and it is disposed on the active surface, and testing cushion is electrically connected to the flip-chip weld pad via trace, and when step (e), protective layer more covers trace.
For realizing above-mentioned purpose of the present invention, the present invention more proposes a kind of chip structure with testing cushion, mainly comprises a chip and a protective layer.Wherein, chip has an active surface, at least one flip-chip weld pad and at least one testing cushion, and wherein flip-chip weld pad and testing cushion all are disposed on the active surface, and testing cushion is positioned at the periphery on active surface, and is electrically connected to the flip-chip weld pad.In addition, protective layer is disposed at active surface, and protective layer exposes the flip-chip weld pad.
According to the preferred embodiments of the present invention; above-mentioned chip has more at least one repairing circuit; it is embedded in the inside of chip; and chip has more at least one repairing window; it is depressed in the active surface of chip relatively; in order to the partial structurtes between thinning repairing circuit and the active surface, and protective layer is more filled up the repairing window.In addition, chip has more at least one trace, and it is disposed on the active surface, and testing cushion is electrically connected to the flip-chip weld pad via trace, and protective layer more covers trace.
Based on above-mentioned, the present invention is the active surface that flip-chip weld pad and testing cushion is formed at simultaneously chip, make the top of probe can come the electricity condition of test chip, so can reduce the exert pressure degree of the internal integrated circuit that destroys wafer of the top of probe by the engaged test pad.In addition; the present invention more can determine whether blocking repairing circuit via repairing window according to test result; form protective layer and salient point at last more in regular turn on chip, thus the test of wafer scale and the processing step of salient point can be reduced, and then reduce technology cost and process cycle.
Description of drawings
For above and other objects of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below, among the figure:
Figure 1A illustrates the partial top view on the active surface of existing wafer;
Figure 1B illustrates the generalized section of existing wafer along the I-I line;
Fig. 1 C illustrates the generalized section of the repairing window of existing wafer along the II-II line;
Fig. 2 illustrates the flow chart of existing wafer level test and encapsulation;
Fig. 3 A illustrates a kind of schematic top plan view of utilizing testing cushion as the test contacts of wafer (or the chip after the cutting) of the preferred embodiments of the present invention;
Fig. 3 B illustrates the generalized section of wafer along the I-I line;
Fig. 4 A～4C illustrates the wafer level test of the preferred embodiments of the present invention and the flow chart of bump process; And
Fig. 5 illustrates the wafer level test of the preferred embodiments of the present invention and the flow chart of bump process.
Description of reference numerals in the accompanying drawing is as follows:
10: vertical probe carb 12: probe
20: cantalever type probe card 22: probe
30: laser beam 100: wafer
102: active surperficial 104: active element
106: integrated circuit 108: the flip-chip weld pad
110,110a: protective layer 112: repairing circuit
114: repair window 120: salient point
200: wafer 202: active surface
204: active element 206: metal interconnecting
208: flip-chip weld pad 208a: testing cushion
209: trace 210: protective layer
212: repairing circuit 214: repair window
230: salient point
Embodiment
Please also refer to Fig. 3 A, 3B, wherein Fig. 3 A illustrates a kind of local schematic top plan view with wafer of testing cushion of the preferred embodiments of the present invention, and Fig. 3 B illustrates the generalized section along the I-I line of Fig. 3 A.At first as shown in Figure 3A, active surperficial 202 of wafer 200 disposes a plurality of flip-chip weld pads 208 and a plurality of testing cushion 208a, and each flip-chip weld pad 208 is for example respectively via a trace 209, and be electrically connected to testing cushion 208a, and 208 of these flip-chip weld pads are via metal interconnecting 206, and are electrically connected to active element 204.It should be noted that, testing cushion 208a is positioned at active surperficial 202 periphery, and testing cushion 208a finishes when making flip-chip weld pad 208 in the lump, and in order to the test contacts as the electricity condition of wafer 200, and the area of testing cushion 208a can be less than the area of flip-chip weld pad 208.In addition, when active surperficial 202 the integrated circuit of making wafer 200 when (comprising active element 104 and metal interconnecting 106), owing to may being subjected to technologic influence, the internal circuit of wafer 200 lost efficacy, so the inside of wafer 200 all is embedded with a plurality of repairing circuits (fuse line) 212 and stand-by circuit (not shown), wherein repair window 214 and be depressed in the active surperficial 202 of wafer 200 relatively, in order to the partial structurtes between thinning repairing circuit 212 and active surperficial 202.Therefore, when finding the circuit of inefficacy is arranged, can utilize laser to pass and repair window 214, and block the repairing circuit of desiring to block 212, thereby make stand-by circuit can replace the circuit of inefficacy through the wafer after the test 200.
Fig. 4 A～4C illustrates the wafer level test of the preferred embodiments of the present invention and the flow chart of bump process.Please refer to Fig. 4 A, with regard to the preferred embodiments of the present invention, the test of its electricity condition of integrated circuit of the inside of wafer 200 is not form salient point (bump) to carry out before on the flip-chip weld pad 208 of wafer 200, and can come active surperficial 202 testing cushion 208a of contact wafer 200 via the probe 22 (only illustrating wherein two) of a cantalever type probe card (cantilever probe card) 20, and testing cushion 208a is via the trace 209 shown in Fig. 3 A, and is electrically connected to the flip-chip weld pad 208 on wafer 200 surfaces.Therefore, the electricity condition of wafer 200 can be via the test contacts of testing cushion 208a as its circuit analysis and debug, and according to the test result that is obtained, determine whether utilizing laser to block repairing circuit 212 via repairing window 214.It should be noted that, because testing cushion 208a is positioned at active surperficial 202 periphery of chip (i.e. cutting after part wafer 200), and the probe 22 of cantalever type probe card 20 flexibly contacts to these testing cushion 208a, makes that the probe 22 desired coplane precisions of cantalever type probe card 20 can be lower.On the other hand, if allow equal all testing cushion 208a on active surperficial 202 of contact wafers 200 simultaneously of all probes 22 of cantalever type probe card 20, in order to improve the accuracy of test, it applies pressure to the strength of testing cushion 208a can moderately to increase cantalever type probe card 20, makes the tip of probe 22 can excessively press down (over-travel) in testing cushion 208.It should be noted that because testing cushion 208a only as the test contacts of circuit analysis and debug, so testing cushion 208a damages (or scratch) to some extent, can not influence the zygosity between salient point 230 shown in Fig. 4 C and the flip-chip weld pad 208 yet.
Then please refer to Fig. 4 B, repairing circuit 212 is embedded in the inside of wafer 200, and is arranged in active surperficial 202 repairing window 214 of wafer 200.Therefore, after the test of the internal integrated circuit of finishing wafer 200, if detect the partly integrated circuit malfunction of the inside of wafer 200, can utilize laser to block the repairing circuit of desiring to block 212, make the stand-by circuit of wafer 200 can replace the partly integrated circuit of inefficacy via repairing window 214.
Then please refer to Fig. 4 C; after the partly integrated circuit mending of wafer 200 is finished; a protective layer 210 that forms patterning afterwards again in wafer 200 active surperficial 202 on; it should be noted that; protective layer 210 is filled up in repairing window 214; and be covered in testing cushion 208a and trace 209 simultaneously, but expose flip-chip weld pad 208.Then carry out bump process, in order to form salient point 230 on each flip-chip weld pad 208, when the material of salient point 230 was scolder, the profile of salient point 230 can slightly be a spherical outward appearance via reflow.In addition, salient point 230 more can carry out the technology of wafer 200 cuttings, in order to form a plurality of chip (not shown), so that carry out the packaging technology of the back segment of chip before forming or after forming.
Please in regular turn with reference to figure 4A～4C, and simultaneously with reference to figure 5, it illustrates the test of wafer scale of the preferred embodiments of the present invention and the flow chart of encapsulation.The test of wafer of the present invention and the technology of encapsulation are roughly as follows: at first shown in step S21, form active surperficial 202 in wafer 200 of flip-chip weld pad 208 and testing cushion 208a simultaneously, and each flip-chip weld pad 208 is electrically connected on one of these testing cushion 208a.Then shown in step S22, form at least one repairing window 214 in active surperficial 202 of wafer 200.Then shown in step S23, as test contacts,, and obtain a test result with the electricity condition of testing wafer 200 (uncut chip) with these testing cushion 208a.Then shown in step S24, according to this test result, whether decision utilizes laser and blocks the repairing circuit of desiring to block 212 via repairing window 214.Then shown in step S25, a protective layer 210 that forms patterning in wafer 200 active surperficial 202 on, wherein protective layer 210 is filled up and is repaired window 214, and coverage test pad 208a, but exposes flip-chip weld pad 208.At last shown in step S26, form salient point 230 on active surperficial 202 flip-chip weld pad 208 of wafer 200.
Wafer level test disclosed in this invention and bump process begin to form the flip-chip weld pad of salient point in the active surface of wafer at last; so the active surface of wafer need not cover a protective layer in advance in technology; and in follow-up with laser when repairing window and block repairing circuit, the present invention need not carry out the action of perforate again to protective layer.In addition, but the present invention the more a plurality of testing cushion of design configurations in the active surface of wafer, in order to test contacts as circuit analysis and debug, and these testing cushion are electrically connected on its pairing flip-chip weld pad respectively, and testing cushion is positioned at the periphery on the active surface of chip, and utilizes the direct surface of engaged test pad, tip of the probe of cantalever type probe card, with the electricity condition of testing wafer, and, determine whether blocking repairing circuit via repairing window according to the test result that is obtained.
In sum, the test of wafer scale of the present invention and bump process have following advantage at least:
(1) test of wafer scale of the present invention and bump process be the integrated circuit of the inside of wafer repair finish after; just form protective layer and salient point in regular turn on the active surface of wafer; compare with the test and the envelope survey technology of existing wafer scale; the present invention need not carry out the work of perforate again to protective layer; get final product the partial structurtes of the top of thinning repairing circuit; so can effectively reduce the test of wafer scale and the processing step of bump process, thereby effectively reduce the technology cost and the cycle of the test and the encapsulation of wafer scale.
(2) test of wafer scale of the present invention and bump process are in the periphery on the active surface of chip with a plurality of testing cushion design configurations of configuration, be used as the test contacts of circuit analysis and debug, therefore, come engaged test pad respectively at probe via cantalever type probe card, during with the electricity condition of the internal integrated circuit of testing wafer, damage (or scratch) to some extent so can not influence the zygosity between salient point and the flip-chip weld pad yet even testing cushion is subjected to the direct contact of probe.
(3) hold (2) point described, because testing cushion is disposed at the periphery on the active surface of chip, so can utilize lower-cost cantalever type probe card, the electricity condition of the internal integrated circuit of testing wafer, and this tests cheaply before salient point forms and just finishes, carries out the bump process of follow-up Flip-Chip Using afterwards again.
Though the present invention with a preferred embodiment openly as above; but it is not in order to limit the present invention; under the situation that does not break away from the spirit and scope of the present invention; those skilled in the art can do a little change and retouching, so protection scope of the present invention should be with being as the criterion that claims were defined.
Claims (8)
1. the test of a wafer scale and bump process are applicable to a wafer, and wherein this wafer has at least one repairing circuit, and it is embedded in the inside of this wafer, and this wafer has more an active surface, and the test and the bump process of this wafer scale comprise the following steps: at least
(a) configuration at least one flip-chip weld pad and at least one testing cushion be on this active surface, and this testing cushion is positioned at the periphery on this active surface, and be electrically connected to this flip-chip weld pad;
(b) form at least one repairing window on this active surface, and this repairing window is depressed in this active surface of this wafer relatively, in order to the partial structurtes between this repairing circuit of thinning and this active surface;
(c) test the electricity condition of this wafer via this testing cushion, and obtain a test result;
(d) according to this test result, whether decision blocks this repairing circuit via this repairing window;
(e) protective layer that forms patterning is on this active surface of this wafer, and wherein this protective layer is filled up this repairing window and covered this testing cushion, but exposes this flip-chip weld pad; And
(f) form a salient point on this flip-chip weld pad.
2. the test of wafer scale as claimed in claim 1 and bump process when step (c), comprise that also the tip via at least one probe of a cantalever type probe card contacts this testing cushion, in order to be electrically connected to the internal circuit of this wafer.
3. the test of wafer scale as claimed in claim 1 and bump process; wherein this wafer also has at least one trace, and it is disposed on this active surface, and this testing cushion is electrically connected to this flip-chip weld pad via this trace; and when step (e), this protective layer also covers this trace.
4. the test of wafer scale as claimed in claim 1 and bump process also comprise a step (g): cut this wafer, in order to form a plurality of chips.
5. chip structure with testing cushion comprises at least:
One chip, have an active surface, at least one flip-chip weld pad and at least one testing cushion, wherein this flip-chip weld pad and this testing cushion all are disposed on this active surface, and this testing cushion is positioned at the periphery on this active surface, and are electrically connected to this flip-chip weld pad; And
One protective layer is disposed at this active surface, and this protective layer exposes this flip-chip weld pad.
6. the chip structure with testing cushion as claimed in claim 5; wherein this chip has more at least one repairing circuit; it is embedded in the inside of this chip; and this chip has more at least one repairing window; it is depressed in this active surface of this chip relatively; in order to the partial structurtes between this repairing circuit of thinning and this active surface, and this protective layer is more filled up this repairing window.
7. the chip structure with testing cushion as claimed in claim 5, wherein this chip also has at least one trace, and it is disposed on this active surface, and this testing cushion is electrically connected to this flip-chip weld pad via this trace, and this protective layer more covers this trace.
8. the chip structure with testing cushion as claimed in claim 5 also comprises at least one salient point, and it is disposed on this flip-chip weld pad.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 03120575 CN1208822C (en) | 2003-03-14 | 2003-03-14 | Wafer grade testing and salient point process and chip struture with testing pad |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 03120575 CN1208822C (en) | 2003-03-14 | 2003-03-14 | Wafer grade testing and salient point process and chip struture with testing pad |
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| CN1435872A true CN1435872A (en) | 2003-08-13 |
| CN1208822C CN1208822C (en) | 2005-06-29 |
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| CN100371726C (en) * | 2004-06-29 | 2008-02-27 | 联华电子股份有限公司 | Chip needle detector |
| CN100466243C (en) * | 2005-09-29 | 2009-03-04 | 三洋电机株式会社 | Semiconductor device and manufacturing method of the same |
| CN102184904A (en) * | 2011-04-12 | 2011-09-14 | 中颖电子股份有限公司 | Bonding disc structure aiming at BOAC frame and integrated circuit device structure |
| CN101488465B (en) * | 2009-02-18 | 2012-01-11 | 北京天碁科技有限公司 | Chip feature configuring method and chip |
| CN103197227A (en) * | 2013-03-25 | 2013-07-10 | 西安华芯半导体有限公司 | Wafer testing method used for design analysis purpose |
| CN103700598A (en) * | 2013-12-10 | 2014-04-02 | 北京中电华大电子设计有限责任公司 | Method for supporting multiple chip packaging modes |
| CN104810242A (en) * | 2014-01-24 | 2015-07-29 | 中芯国际集成电路制造(上海)有限公司 | Test structure and manufacturing method thereof |
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| CN100371726C (en) * | 2004-06-29 | 2008-02-27 | 联华电子股份有限公司 | Chip needle detector |
| CN100466243C (en) * | 2005-09-29 | 2009-03-04 | 三洋电机株式会社 | Semiconductor device and manufacturing method of the same |
| US7508072B2 (en) | 2005-09-29 | 2009-03-24 | Sanyo Electric Co., Ltd. | Semiconductor device with pad electrode for testing and manufacturing method of the same |
| CN101488465B (en) * | 2009-02-18 | 2012-01-11 | 北京天碁科技有限公司 | Chip feature configuring method and chip |
| CN102184904A (en) * | 2011-04-12 | 2011-09-14 | 中颖电子股份有限公司 | Bonding disc structure aiming at BOAC frame and integrated circuit device structure |
| CN103197227A (en) * | 2013-03-25 | 2013-07-10 | 西安华芯半导体有限公司 | Wafer testing method used for design analysis purpose |
| CN103700598A (en) * | 2013-12-10 | 2014-04-02 | 北京中电华大电子设计有限责任公司 | Method for supporting multiple chip packaging modes |
| CN104810242B (en) * | 2014-01-24 | 2017-12-19 | 中芯国际集成电路制造(上海)有限公司 | A kind of test structure and preparation method thereof |
| CN104810242A (en) * | 2014-01-24 | 2015-07-29 | 中芯国际集成电路制造(上海)有限公司 | Test structure and manufacturing method thereof |
| WO2019069192A1 (en) * | 2017-10-02 | 2019-04-11 | International Business Machines Corporation | Wafer scale testing and initialization of small die chips |
| US10388578B2 (en) | 2017-10-02 | 2019-08-20 | International Business Machines Corporation | Wafer scale testing and initialization of small die chips |
| CN111095511A (en) * | 2017-10-02 | 2020-05-01 | 国际商业机器公司 | Wafer level testing and initialization of small die chips |
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| GB2581684A (en) * | 2017-10-02 | 2020-08-26 | Ibm | Wafer scale testing and initialization of small die chips |
| GB2581684B (en) * | 2017-10-02 | 2022-05-11 | Elpis Tech Inc | Wafer scale testing and initialization of small die chips |
| CN110246813A (en) * | 2018-03-08 | 2019-09-17 | 台湾积体电路制造股份有限公司 | Chip architecture and packaging method |
| CN110246813B (en) * | 2018-03-08 | 2022-11-11 | 台湾积体电路制造股份有限公司 | Chip structure and packaging method |
| CN110911301A (en) * | 2019-12-26 | 2020-03-24 | 苏州科阳光电科技有限公司 | Wafer level packaging detection structure and method |
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