CN1430769B - Tiled graphics architecture - Google Patents
Tiled graphics architecture Download PDFInfo
- Publication number
- CN1430769B CN1430769B CN018098916A CN01809891A CN1430769B CN 1430769 B CN1430769 B CN 1430769B CN 018098916 A CN018098916 A CN 018098916A CN 01809891 A CN01809891 A CN 01809891A CN 1430769 B CN1430769 B CN 1430769B
- Authority
- CN
- China
- Prior art keywords
- frames images
- storage area
- primitive
- vertex
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T15/00—3D [Three Dimensional] image rendering
- G06T15/005—General purpose rendering architectures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/60—Memory management
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Graphics (AREA)
- Image Generation (AREA)
Abstract
A method and apparatus for reducing memory bandwidth utilization in a tiled graphics architecture is disclosed. In one embodiment, a microprocessor reads vertex data for a graphics primitive from graphics memory. The processor determines with which bins the graphics primitive intersects. Assuming that the processor determines that the graphics primitive intersects a first and a second bin, the processor writes the vertex data for the graphics primitve to a first bin storage area in graphics memory. The processor then writes a pointer to a second bin storage area. The pointer indicates the location in memory of the actual vertex data.
Description
Invention field
The present invention relates to field of computer.More particularly, this invention relates in tiled graphics architecture (tiled graphics archtecture) field that reduces the primitive memory requirement and improve the bandwidth of memory utilization factor.
Background technology
In typical computer graphics system, the three-dimensional that is represented on the display screen (3D) object is by forming such as triangle bar (triangle lists), triangular plate (triangle strips) and fan-shaped (triangle fans) the figures primitive of triangle (primitive).Usually, the primitive that presents the 3D object is confirmed by main frame according to the primitive data.For example, for each triangle in the primitive, main frame can be according to confirming leg-of-mutton three summits by the locus of X, Y, the decision of Z coordinate, and with the data and the texture structure coordinate of three kinds of color numerical value of the red, green, blue that decides each summit.Can use some additional primitive data in the certain applications field.The hardware that is used to appear that is positioned at graphics controller comes computing to represent R, G and the B color numerical value of pixel and each pixel of each primitive through slotting primitive data.
In order more effectively to utilize bandwidth of memory, graphic primitive is assigned in the frames images (bin), these frames images also can be called " piece ".This technology that is widely known by the people is commonly called " piece method ".
Accompanying drawing 1 is depicted as with accompanying drawing 2 graphic primitive is assigned to the example in frames images or the piece.In this example, microprocessor is got the data of primitive 110,120 and 130 from the primitive storage area.This primitive storage area can be used as the part of main system memory or is used as the local graphics memory that is directly connected in graphics controller.Primitive 110,120 and 130 is finally appeared, and on display screen, shows then, and square frame 100 is represented display screen.Four frames images of square frame 100 discrete one-tenth in this example.Especially, the often discrete one-tenth of video data structure is more than four frames images in this example, and the size of the frames images in this example is 128 * 64 pixels of standard.Why using four frames images purposes in this example is in order to simplify discussion.
Read after the graphic primitive data, processor will confirm that primitive and that frames images or " piece " intersect.For example, processor can confirm that primitive 110 and frames images 210 and 220 intersect.Next processor is written as the zone of the graphic memory that frames images 210 storage primitive data are kept with three vertex datas of primitive 110 and the zone of the graphic memory that kept for frames images 220 storage primitive data.Similarly, storer is written to the storage area of frames images 220 and 240 with the vertex data of primitive 120, simultaneously the vertex data of primitive 130 is written to the storage area of frames images 210,230 and 240.In case primitive is assigned in the frames images, graphics controller will read the primitive data from graphic memory, and presents the primitive of a frames images at every turn.
It is how primitive 110,120 and 130 to be divided into a plurality of primitives that are fitted to frames images 210,220,230 and 240 that accompanying drawing 2 provides graphics controller.Intersect the different of mode according to primitive with the frames images border, all kinds of primitives are divided in the frames images.For example, when the primitive data of frames images 210 when graphic memory reads, thereby graphic memory comes primitive 110 separations and produces primitive 211, the primitive 130 discrete primitives 212 that produce.Then, graphics controller presents primitive 211 and 212.Graphic memory then through discrete primitive 110 and 120 to produce primitive 221 and 222 and present primitive 221 and 222 and come frames images 220 is handled.The processing mode that graphics controller continues frames images 230 and 240 is similar.
Accompanying drawing 3 is depicted as the existing block diagram that uses the computer system of tiled graphics architecture.Provided processor 310 in the accompanying drawing 3, comprised the system storage 330 of graphic primitive storage area 332, graphics controller 340 and picture monitor 350.
Existing like the employed tiled graphics architecture of system in the accompanying drawing 3, its drawback is need use a large amount of bandwidth of memories when between equipment, moving the primitive data.For example, when processor 310 is handled primitive, processor 310 will read the vertex data value of this primitive from graphic primitive storage area 332.Processor 310 confirms that thereupon primitive and that frames images intersect.Processor 310 must write back to graphic primitive storage area 332 to a plurality of copies of vertex data then, and the copy amount of writing is decided by the quantity of primitive intersection frames images therewith in this zone.
Can show the influence that the bandwidth of memory utilization factor is suffered through investigating the typical graphics primitive, this primitive can be represented and it possibly intersect with a plurality of frames images by the vertex data that size is approximately 100 bytes.To suppose in this example that typical primitive and 3 frames images intersect.In such cases, for each primitive of handling, processor 310 must write the vertex data of average 300 bytes in graphic primitive storage area 332.For the simple relatively display structure that comprises the 2k graphic primitive, processor 310 must provide the data of 600k byte to every kind of structure.If frame shows that speed is per second 60 frames, processor must provide data to graphic primitive storage area 332 with the speed of per second 360M byte so.For the more complicated demonstration that comprises the 100k primitive, bandwidth requirement is brought up to per second 1.8G byte.The bandwidth requirement that between graphic primitive storage area 332 and graphics controller 340, needs to satisfy is the same.This with the graphic primitive data from processor 310 transfer to graphic primitive storage area 332 and from graphic primitive storage area 332 to graphics controller 340 the height utilization meeting of memory bandwidth is brought great negative effect for the total system operation.
Accompanying drawing is briefly described
Through following detailed description and the accompanying drawing relevant, will fully understand the present invention with content of the present invention.Yet these contents should not be regarded as and only be confined to specific embodiment described in the invention, and only be for explain and understand on convenience.
Fig. 1 is according to existing system, the structural drawing of several 3D objects of on display screen, being arranged.
Fig. 2 is according to existing system, describes the several 3D objects among Fig. 1 are assigned to the process structure diagram in the frames images.
Fig. 3 is the current block diagram that comprises the tiled graphics architecture system.
Fig. 4 is in tiled graphics architecture, uses the process flow diagram of the specific embodiment of the method that reduces the bandwidth of memory utilization factor.
Fig. 5 uses the process flow diagram of the specific embodiment of the method that reduces the bandwidth of memory utilization factor for be arranged in the tiled graphics architecture of system storage at the graphic primitive storage area.
Fig. 6 uses the process flow diagram of the specific embodiment of the method that reduces the bandwidth of memory utilization factor for be arranged in the tiled graphics architecture of local graphics memory at the graphic primitive storage area.
Fig. 7 is the block diagram that comprises the system of a concrete graphics controller embodiment, and this controller contains vertex cache.
Describe in detail
To describe the specific embodiment that is used for reducing bandwidth of memory utilization factor method and apparatus in the tiled graphics architecture below.In this example, microprocessor reads vertex data for graphic primitive from graphic memory.Storer will confirm that graphic primitive and that frames images intersect.All summits of this primitive are write in the vertex buffer in order to reference in the future.This vertex buffer is arranged in main system memory or local graphics memory.Vertex buffer can be used as the part of frames images storage area or in the separate memory zone, uses.
Suppose that processor confirms that this graphic primitive and first and second frames images intersect, processor will write pointer to the first and second frames images storage areas.This pointer has been indicated the position in actual vertex data storer.Like this, only there is a vertex data copy to transfer to graphic memory from processor.Because this pointer size is littler than vertex data,, improved the use of bandwidth of memory simultaneously so less data move to graphic memory from processor.
Microprocessor in previous example and the ensuing specific embodiment is replaceable to be the 3D graphic process unit, and its primitive that carries out operation is identical with microprocessor.For example, extention can comprise the 3D graphic process unit of accomplishing hardware conversion and the inner indication calculating of hardware.
The part that graphic memory in previous example and the ensuing specific embodiment can be used as main system memory includes, or is able to use as the local graphics memory that is directly connected in graphics controller.
Here employed " pointer " means and comprises any means of indicating the vertex data position at least in part, comprises that storage address also comprises index.For example, pointer can be physical storage or the virtual memory address of indicating the vertex data position.This pointer is replaceable to be index, utilizes this index can calculate the address of vertex data.For example, can calculate the address from index value according to equation " base address+index * vertex data size ".
Though top example and ensuing numerous example have been discussed the frames images of the specified quantity that intersects with graphic primitive, and can use the frames images of any amount in other the example.Further, though the graphic primitive of being discussed here comprises the triangle on three summits, and the primitive of other type also is feasible.
Moreover in the described here specific embodiment, address date is assumed to 32 bit wides, and index is assumed to 16 bit wides, and the vertex data of triangle primitive is assumed to about 100 byte longs.Other uses on a large scale, and the embodiment of address, index and data size and length also is feasible.
Accompanying drawing 4 is for using the process flow diagram of the concrete grammar that improves the bandwidth of memory utilization factor in tiled graphics architecture.Square frame 410 will confirm whether graphic primitive intersects with first and second frames images.If graphic primitive comes to light and first and second frames images intersect, a plurality of vertex datas of conforming to of graphic primitive are written into the first frames images storage area that is arranged in memory device in square frame 420 so therewith.This memory device can comprise main system memory, or comprises the local graphics memory that is directly connected in graphics controller.
At square frame 430, a plurality of pointers are written into the second frames images storage area that is positioned at graphic memory.These pointers have been indicated the memory location of a plurality of vertex datas.Through pointer being write the second frames images storage area rather than writing vertex data, less data are transferred to graphic memory from processor, have improved the bandwidth of memory utilization factor simultaneously.Graphics controller will use pointer to extract vertex data from the first frames images storage area.
Accompanying drawing 5 is for using the process flow diagram of the concrete grammar that improves the bandwidth of memory utilization factor in the computer system tiled graphics architecture.Wherein, in this system, graphic memory is used as a zone in the main system memory, and graphics controller comprises vertex cache.This vertex cache is that vertex data provides the scratchpad area (SPA); Simultaneously through reduce graphic memory and graphics controller between the vertex data quantity that shifted, thereby in graphics controller bandwidth of memory utilization factor, realize the improvement that system storage is inner.
With reference to accompanying drawing 5, read the graphic primitive vertex data at square frame 505 processors from system storage, accomplish computing at square frame 510 processors to vertex data.In this example, the vertex data of graphic primitive comprises the data on three summits, though the vertex data of graphic primitive possibly comprise the data on any amount summit in other embodiment.Be meant the numerous technology that are widely known by the people of processing graphics primitive data of being used for as the computing of an embodiment part.
In square frame 515, processor confirms that whether graphic primitive intersects with first frames images, supposes there is the situation that intersects that storer is with the first frames images storage area of the vertex data writing system storer of graphic primitive so.
In square frame 520, processor confirms whether graphic primitive intersects with second frames images.If graphic primitive comes to light and second frames images intersects, then at the second frames images storage area of square frame 525 processors with three pointer writing system storeies.These pointers are indicated the memory location on three summits that before are written to system storage.
In square frame 530, processor will confirm whether graphic primitive intersects with the 3rd frames images.If graphic primitive comes to light and the 3rd frames images intersects, then at three the frames images storage area of square frame 535 processors with three pointer writing system storeies.These pointers have been indicated the memory location on three summits that before are written to system storage.
At square frame 540, processor will confirm whether graphic primitive intersects with the 4th frames images.If graphic primitive comes to light and the 4th frames images intersects, then at four the frames images storage area of square frame 545 processors with three pointer writing system storeies.Before having indicated, these pointers are written to the memory location on three summits of system storage.
Though the graphic primitive described in this embodiment possibly intersect with four frames images, other graphic primitive possibly also be feasible with the embodiment that two or more frames images intersect.Further, in one embodiment, the size of frames images possibly be 128 pixels * 64 pixels, even other frames images size also is feasible.In addition, replacing above-mentioned in-order mode to confirm whether frames images intersects in a parallel manner also is fine.For example, can utilize the bounding box of primitive to come to find fast all images frame with primitive intersection.
Shown in square frame 547,, be assigned in the frames images up to all primitives with repeating the operation of square frame 505 to square frame 545.
In square frame 550, graphics controller is from the first frames images storage area reading of data.The data that from the first frames images storage area and vertex buffer, read are included in the vertex data that is written to the graphic primitive of system storage before the square frame 515.
In square frame 555, graphics controller is by reading vertex data in the vertex cache.In one embodiment, vertex cache comprises 16 inlets, and these inlets are 4 the tunnel and mutual weave in, can store the vertex data of 32 bytes.Other has the inlet and the way of varying number, but and further the embodiment of the vertex data of each inlet storing different numbers also be feasible.
Graphics controller reads the first frames images data and simultaneously vertex data is stored into after the vertex cache, and graphics controller presents the first frames images primitive at square frame 560.As a part that presents operation, graphics controller will confirm to be included in that each graphic primitive is that part drops in first frames images actually in the first frames images data, only present that part of primitive then.
Follow appearing of first frames images closely, graphics controller will be handled second frames images.As the first step of handling second frames images, reading of data in the second frames images storage area of graphics controller from square frame 565.The data that from the second frames images storage area, read comprise the pointer of the vertex data of order directional pattern primitive, suppose at square frame 520 and find to intersect with second frames images.In square frame 570, graphics controller uses pointer to be stored in the data in the vertex cache in the square frame 555 in the past.In case graphics processor accesses is data to the limit, graphic process unit presents the second frames images primitive at square frame 575.
In square frame 580, will determine whether to present remaining frames images.If there is remaining frames images, in square frame 565, proceed operation.Repeat the operation of square frame 565, up to presenting all frames images and running abort at square frame 585 to square frame 580.Noticing that the order that frames images appears can be serial, can not be serial also.Based on certain heuristic method, the foregoing description can be summed up as and at first present second frames images, is respectively the 3rd, first and the 4th frames images then.This can provide best practice for the total system operation.For example, download capable of using is balanced carries out standardization to the download in the most preceding and rearmost end operation in the graphic process unit.
Accompanying drawing 6 is for using the process flow diagram of the embodiment of the method for improving the bandwidth of memory utilization factor in the computer system tiled graphics architecture, graphic memory is used as the local graphics memory that is directly connected in graphics controller in this system.Local graphics memory is that vertex data provides storage space; Simultaneously through reducing the quantity of the vertex data that graphic memory and graphics controller in the main system memory shift between the two, thereby realize the improvement of system storage to the use of graphics controller memory bandwidth.
With reference to accompanying drawing 6, from local graphics memory or system storage, read the vertex data of graphic primitive at square frame 605 processors, at square frame 610 storeies vertex data is handled simultaneously.In this example, the vertex data of graphic primitive comprises three vertex datas, also is feasible though other graphic primitive vertex data comprises the embodiment of the vertex data of any amount.Above described computing as an embodiment part be meant the technology that is widely known by the people on a large scale of processing graphics primitive data of being used for.In square frame 615, processor confirms whether graphic primitive intersects with first frames images.Suppose crossingly, storer writes the first frames images storage area in the local graphics memory with the vertex data of graphic primitive.
In square frame 620, processor confirms whether graphic primitive intersects with second frames images.Intersect if find the graphic primitive and second frames images, processor then writes the second frames images storage area in the local graphics memory at square frame 625 with three pointers.These pointers are indicated the memory location on three summits that before write local graphics memory.
In square frame 630, processor confirms whether graphic primitive intersects with the 3rd frames images.Intersect if find graphic primitive and the 3rd frames images, processor then writes the 3rd frames images storage area in the local graphics memory at square frame 635 with three pointers.These pointers are indicated the memory location on three summits that before write local graphics memory.
In square frame 640, processor confirms whether graphic primitive intersects with the 4th frames images.Intersect if find graphic primitive and the 4th frames images, processor then writes the 4th frames images storage area in the local graphics memory at square frame 645 with three pointers.These pointers are indicated the memory location on three summits that before write local graphics memory.
Though the graphic primitive described in this embodiment possibly intersect with four frames images, other graphic primitive possibly also be feasible with the embodiment that two or more frames images intersect.Further, the size of frames images possibly be 128 pixels * 64 pixels in specific embodiment, even other frames images size also is feasible.In addition, replacing above-mentioned in-order mode to confirm whether frames images intersects in a parallel manner also is fine.For example, can utilize the bounding box of primitive to come to find fast all images frame with primitive intersection.
Shown in square frame 647,, be assigned in the frames images up to all primitives with repeating the operation of square frame 605 to square frame 645.
In square frame 650, graphics controller is from the first frames images storage area reading of data.The data that read from the first frames images storage area are included in the vertex data that is written to the graphic primitive of system storage before the square frame 615.
Graphics controller reads after the first frames images data, and graphics controller presents the first frames images primitive at square frame 660.As a part that presents operation, graphics controller will confirm to be included in that each graphic primitive is that part drops in first frames images actually in the first frames images data, only present that part of primitive then.
Follow appearing of first frames images closely, graphics controller will be handled second frames images.As the first step of handling second frames images, reading of data in the second frames images storage area of graphics controller from square frame 665.The data that from the second frames images storage area, read comprise the pointer of the vertex data of order directional pattern primitive, suppose at square frame 620 and find to intersect with second frames images.In square frame 670, graphics controller uses pointer to be stored in the data in the vertex cache in the square frame 615 in the past.In case graphics processor accesses is data to the limit, graphic process unit presents the second frames images primitive at square frame 675.
In square frame 680, need present in additional frames images determine whether.If there is additional frames images, in square frame 665, proceed operation.Repeat the operation of square frame 665, up to presenting all frames images and running abort at square frame 685 to square frame 680.Noticing that the order that frames images appears can be serial, can not be serial also.Based on certain heuristic method, the foregoing description can be summed up as and at first present second frames images, is respectively the 3rd, first and the 4th frames images then.This can provide best practice for the total system operation.For example, download capable of using is balanced carries out standardization to the download in the most preceding and rearmost end operation in the graphic process unit.
Accompanying drawing 7 is for comprising the computer system block diagram of graphics controller 740, and this controller contains vertex cache 742.Computer system in the accompanying drawing 7 also contains the processor 710 that is connected in system logic device 720 through processor bus 715.This system logic device 720 provides the dialogue between processor 710 and the system storage 730.System storage 730 comprises graphic primitive storage area 732.This graphic primitive storage area 732 can become a plurality of storage areas for a plurality of frames images are discrete.
System logic device 720 is also as graphics controller 740 being connected to processor 710 and system storage 730.System in the accompanying drawing 7 also comprises the picture monitor 750 that is connected on the graphics controller 740.
System in the accompanying drawing 7 can with as the use that attaches in the Figure 4 and 5 the to be discussed method embodiment that improves the bandwidth of memory utilization factor use simultaneously.For example, processor 710 can read the vertex data of graphic primitive from graphic primitive storage area 732.Processor 710 can confirm that then graphic primitive and that frames images intersect.Processor 710 writes the frames images storage area first time in the graphic primitive storage area 732 with vertex data then.Intersect if find graphic primitive and other frames images, processor 710 then writes other frames images storage area in the graphic primitive storage area 732 with pointer.These pointers indicated be used for storing vertex data the first time frames images storage area the position.Pointer in this example comprises 16 bit index value, utilizes this index value can calculate the memory location of vertex data.Other embodiment that comprises the 32 bit address pointers that are used for confirming the vertex data memory location also is feasible.Other uses different length index values and/or other embodiment of address also to be fine.
When graphics controller 740 desires were handled first frames images, graphics controller 740 can read the first frames images data from graphic primitive storage area 732.Graphics controller 740 is graphic primitive storage vertex data in vertex cache 742.Graphics controller 740 presents first frames images of a part that comprises the graphic primitive that falls into first frames images then.
In this example, frames images is of a size of 128 * 64 pixels.Vertex cache 742 in the example comprises 16 inlets, and these inlets are 4 road set associative structures and can store the vertex data of 32 bytes.Graphic primitive in this example is represented by three summits, and wherein each summit is confirmed by 32 byte datas.Other uses the embodiment of different images frame size and/or cache memory also is feasible.
When graphics controller 740 was ready to handle second frames images, graphics controller 740 can read the data of second frames images from graphic primitive storage area 732.The data of second frames images will comprise the pointer of order directional pattern primitive vertex data, suppose that the processor 710 before definite graphic primitives and second frames images intersect.Graphics controller 740 utilizes pointer to get into the vertex data that is stored in the vertex cache 742 then.When the copy of vertex data is stored in the vertex cache 742; Through eliminating the demand that from graphic primitive storage area 732, reads vertex data; Vertex cache 742 can be used to improve the bandwidth of memory utilization factor, and this example just belongs to this situation.
In case vertex data is return from vertex cache 742, graphics controller 740 can present second frames images.Follow-up frames images is handled in a similar fashion, till presenting all frames images.
Invention has been described with reference in the concrete embodiment detailed description in front.Yet significantly, can carry out various changes and conversion, and these can not be deviated from wider thought of the present invention and category as what mention in the accompanying claims to this.Instructions and accompanying drawing correspondingly are counted as a kind of giving an example rather than restriction.
Be associated with these embodiment described specific characteristic, structure or characteristic of " a kind of embodiment " that is mentioned in the instructions, " a certain embodiment ", " some embodiment " or " other embodiment " expression is contained among some embodiment at least, but not necessarily is contained among all embodiment.The appearance indication of " a kind of embodiment ", " a certain embodiment " or " some embodiment " needn't just be meant identical embodiment.
Claims (10)
1. method that is used to improve the bandwidth of memory utilization factor, said method comprises:
Intersect if find the graphic primitive and first frames images, then the vertex data of graphic primitive is write the position of the first frames images storage area that is arranged in system storage;
If find that graphic primitive is crossing with the frames images except that first frames images; Then only a plurality of pointers are write and be arranged in frames images storage area system storage, except that the first frames images storage area; The memory location of the vertex data of writing system storer before said a plurality of pointer is used for indicating
Only the copy of the vertex data of graphic primitive is moved to the vertex cache of graphics controller from the first frames images storage area of system storage.
2. method according to claim 1; The vertex cache that wherein only the copy of the vertex data of graphic primitive is moved to graphics controller from the first frames images storage area of system storage only comprises a copy of vertex data moved to the vertex cache of graphics controller from the first frames images storage area of system storage, and wherein only said a plurality of pointers write and be arranged in frames images storage area system storage, except that the first frames images storage area and comprise if find that graphic primitive and second frames images are crossing then with the second frames images storage area of pointer writing system storer.
3. method according to claim 2; The position that wherein vertex data of graphic primitive is write the first frames images storage area that is arranged in system storage comprises that the vertex data with graphic primitive writes the first frames images storage area that is arranged in main system memory, and wherein said system storage comprises main system memory.
4. method according to claim 3; Wherein a plurality of pointers are write the second frames images storage area that is arranged in system storage and comprise a plurality of pointers are write the second frames images storage area that is arranged in main system memory that wherein said system storage comprises main system memory.
5. equipment that is used to improve the bandwidth of memory utilization factor, said equipment comprises:
Processor intersects if be used for finding the graphic primitive and first frames images, then with the position in the first frames images storage area in the vertex data writing system storer of graphic primitive, related with first frames images,
If said processor is used for also finding that graphic primitive is crossing with the frames images except that first frames images; Then only a plurality of pointers are write in the storage area related with the frames images except that first frames images memory location of the vertex data of writing system storer before said a plurality of pointers are used for indicating; And
Graphics controller is used for only the copy of vertex data being moved to from the first frames images storage area of system storage the vertex cache of graphics controller.
6. equipment according to claim 5 further comprises:
Vertex cache; And
The frames images reading unit is used for reading the corresponding data in the summit of indicating with pointer from said vertex cache.
7. equipment according to claim 6, wherein said vertex cache comprises a plurality of inlets, each inlet is used for storing the vertex data of 32 bytes.
8. system that is used to improve the bandwidth of memory utilization factor, said system comprises:
Processor; If being used for finding the graphic primitive and first frames images intersects; Then with the position in the first frames images storage area in the vertex data writing system storer of graphic primitive, related with first frames images; If said processor is used for also finding that graphic primitive is crossing with the frames images except that first frames images; Then only a plurality of pointers are write in the storage area related with the frames images except that first frames images, the memory location of the vertex data of writing system storer before said a plurality of pointers are used for indicating, wherein storage area is in system storage;
The Memory Controller that is connected with processor;
The system storage that is connected with Memory Controller; And
Graphics controller; Said graphics controller comprises from being arranged in the frames images reading unit that storage area system storage, related with first frames images reads the graphic primitive data, and said graphics controller only moves to the copy of vertex data the vertex cache of graphics controller from the first frames images storage area of system storage.
9. system according to claim 8, graphics controller further comprises vertex cache, the frames images reading unit reads the corresponding data in the summit of indicating with pointer from said vertex cache.
10. system according to claim 9, wherein said vertex cache comprises a plurality of inlets, each inlet is used for storing the vertex data of 32 bytes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210080502.0A CN102842145B (en) | 2000-03-31 | 2001-03-06 | Tiled graphics architecture |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US54061600A | 2000-03-31 | 2000-03-31 | |
| US09/540,616 | 2000-03-31 | ||
| PCT/US2001/007225 WO2001075804A1 (en) | 2000-03-31 | 2001-03-06 | Tiled graphics architecture |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210080502.0A Division CN102842145B (en) | 2000-03-31 | 2001-03-06 | Tiled graphics architecture |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1430769A CN1430769A (en) | 2003-07-16 |
| CN1430769B true CN1430769B (en) | 2012-05-30 |
Family
ID=24156227
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210080502.0A Expired - Fee Related CN102842145B (en) | 2000-03-31 | 2001-03-06 | Tiled graphics architecture |
| CN018098916A Expired - Fee Related CN1430769B (en) | 2000-03-31 | 2001-03-06 | Tiled graphics architecture |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210080502.0A Expired - Fee Related CN102842145B (en) | 2000-03-31 | 2001-03-06 | Tiled graphics architecture |
Country Status (8)
| Country | Link |
|---|---|
| EP (1) | EP1269418A1 (en) |
| JP (1) | JP2003529860A (en) |
| KR (1) | KR100550240B1 (en) |
| CN (2) | CN102842145B (en) |
| AU (1) | AU2001256955A1 (en) |
| HK (1) | HK1049537A1 (en) |
| TW (1) | TWI233573B (en) |
| WO (1) | WO2001075804A1 (en) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6738069B2 (en) * | 2001-12-31 | 2004-05-18 | Intel Corporation | Efficient graphics state management for zone rendering |
| US7765366B2 (en) * | 2005-06-23 | 2010-07-27 | Intel Corporation | Memory micro-tiling |
| GB2449399B (en) * | 2006-09-29 | 2009-05-06 | Imagination Tech Ltd | Improvements in memory management for systems for generating 3-dimensional computer images |
| JP4913823B2 (en) * | 2006-11-01 | 2012-04-11 | 株式会社ディジタルメディアプロフェッショナル | A device to accelerate the processing of the extended primitive vertex cache |
| US8139058B2 (en) * | 2006-11-03 | 2012-03-20 | Vivante Corporation | Hierarchical tile-based rasterization algorithm |
| GB2458488C (en) | 2008-03-19 | 2018-09-12 | Imagination Tech Ltd | Untransformed display lists in a tile based rendering system |
| US20110043518A1 (en) * | 2009-08-21 | 2011-02-24 | Nicolas Galoppo Von Borries | Techniques to store and retrieve image data |
| KR101609266B1 (en) | 2009-10-20 | 2016-04-21 | 삼성전자주식회사 | Apparatus and method for rendering tile based |
| KR101683556B1 (en) | 2010-01-06 | 2016-12-08 | 삼성전자주식회사 | Apparatus and method for tile-based rendering |
| JP5362915B2 (en) * | 2010-06-24 | 2013-12-11 | 富士通株式会社 | Drawing apparatus and drawing method |
| KR102018699B1 (en) | 2011-11-09 | 2019-09-06 | 삼성전자주식회사 | Apparatus and Method for Tile Binning |
| CN110415161B (en) * | 2019-07-19 | 2023-06-27 | 龙芯中科(合肥)技术有限公司 | Graphics processing method, device, equipment and storage medium |
| WO2022150347A1 (en) * | 2021-01-05 | 2022-07-14 | Google Llc | Subsurface display interfaces and associated systems and methods |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5886701A (en) * | 1995-08-04 | 1999-03-23 | Microsoft Corporation | Graphics rendering device and method for operating same |
| AU5686299A (en) * | 1998-08-20 | 2000-03-14 | Raycer, Inc. | Method and apparatus for generating texture |
| US6771264B1 (en) * | 1998-08-20 | 2004-08-03 | Apple Computer, Inc. | Method and apparatus for performing tangent space lighting and bump mapping in a deferred shading graphics processor |
-
2001
- 2001-03-06 CN CN201210080502.0A patent/CN102842145B/en not_active Expired - Fee Related
- 2001-03-06 KR KR1020027013055A patent/KR100550240B1/en active IP Right Grant
- 2001-03-06 WO PCT/US2001/007225 patent/WO2001075804A1/en active IP Right Grant
- 2001-03-06 AU AU2001256955A patent/AU2001256955A1/en not_active Abandoned
- 2001-03-06 EP EP01930417A patent/EP1269418A1/en not_active Withdrawn
- 2001-03-06 JP JP2001573406A patent/JP2003529860A/en active Pending
- 2001-03-06 CN CN018098916A patent/CN1430769B/en not_active Expired - Fee Related
- 2001-04-17 TW TW090107594A patent/TWI233573B/en not_active IP Right Cessation
-
2003
- 2003-03-07 HK HK03101674.8A patent/HK1049537A1/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| WO2001075804A1 (en) | 2001-10-11 |
| EP1269418A1 (en) | 2003-01-02 |
| CN102842145B (en) | 2016-08-24 |
| KR20030005253A (en) | 2003-01-17 |
| TWI233573B (en) | 2005-06-01 |
| JP2003529860A (en) | 2003-10-07 |
| CN102842145A (en) | 2012-12-26 |
| HK1049537A1 (en) | 2003-05-16 |
| AU2001256955A1 (en) | 2001-10-15 |
| CN1430769A (en) | 2003-07-16 |
| KR100550240B1 (en) | 2006-02-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5729672A (en) | Ray tracing method and apparatus for projecting rays through an object represented by a set of infinite surfaces | |
| US7119809B1 (en) | Parallel architecture for graphics primitive decomposition | |
| CN101124613B (en) | Graphic processing sub system and method with increased scalability in the fragment shading pipeline | |
| US5805868A (en) | Graphics subsystem with fast clear capability | |
| US6348919B1 (en) | Graphics system with optimized use of unified local and frame buffers | |
| KR100301223B1 (en) | Draw processor for high performance 3D graphic accelerators | |
| US5815166A (en) | Graphics subsystem with slaveable rasterizer | |
| CN1430769B (en) | Tiled graphics architecture | |
| US20040008200A1 (en) | Method for context switching a graphics accelerator comprising multiple rendering pipelines | |
| EP0783154A2 (en) | Split-level graphics library | |
| WO1997005576A1 (en) | Method and apparatus for span and subspan sorting rendering system | |
| WO1997005576A9 (en) | Method and apparatus for span and subspan sorting rendering system | |
| JP2002526842A (en) | Graphics processor with deferred shading | |
| EP0725367A1 (en) | Improvements relating to computer 3D rendering systems | |
| JP4154336B2 (en) | Method and apparatus for drawing a frame of a raster image | |
| JP2882465B2 (en) | Image generation method and apparatus | |
| US6778179B2 (en) | External dirty tag bits for 3D-RAM SRAM | |
| US6982719B2 (en) | Switching sample buffer context in response to sample requests for real-time sample filtering and video generation | |
| WO1992000570A1 (en) | Graphics rendering systems | |
| US7528839B1 (en) | Faster clears for three-dimensional modeling applications | |
| US7710425B1 (en) | Graphic memory management with invisible hardware-managed page faulting | |
| US6816162B2 (en) | Data management to enable video rate anti-aliasing convolution | |
| US6515661B1 (en) | Anti-aliasing buffer | |
| JPS63137378A (en) | Graphics processing system | |
| US20050052459A1 (en) | Method and system for rendering macropixels in a graphical image |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120530 Termination date: 20180306 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |