CN1417682A

CN1417682A - Dynamic memory function test method

Info

Publication number: CN1417682A
Application number: CN 01140560
Authority: CN
Inventors: 胡勇; 朱星海
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2001-11-06
Filing date: 2001-11-06
Publication date: 2003-05-14
Anticipated expiration: 2021-11-06
Also published as: CN1194299C

Abstract

The dynamic memory function test method features the sectional test .The program in the EEROM is transferred to the dynamic memory, and the dynamic memory is then tested through test-removal-test-recovery-removal-test-recovery process until completing the test of all sections. During the test, if some error is found, the test will be paused while the error information is reported. Owing to the save and restore of the content in each section, the program may run normally. The present invention has high test speed, and this makes it possible to use only higher order language rather than assembly language and facilitates the program debugging.

Description

Dynamic memory function test method

Technical field:

The present invention relates to a kind of dynamic memory function test method.

Background technology:

At present, CPU minimum system on the veneer generally all comprises devices such as central processing unit CPU, electrically-erasable storer FLASH (BOOTROM) and dynamic storage SDRAM, as shown in Figure 1, wherein CPU is the core of veneer, is used for carrying out the operations of board software appointment.FLASH is a kind of storer of electric erasable, even the veneer power down, the program or the data that are kept at wherein can not lost yet.CPU can read the content among the FLASH easily, but only just can wipe and write operation it under specific situation.SDRAM is a kind of dynamic storer, and after the veneer power down, the program or the data that are kept at wherein will be lost, and CPU can carry out read-write operation to SDRAM easily.The characteristics of these two kinds of storeies itself have determined that CPU is slower to the reading and writing data among the FLASH, and very fast to the reading and writing data among the SDRAM.So generally all be that board software is kept among the FLASH, Board Power up carries out just program among the FLASH and data-moving being moved in SDRAM after the necessary initialization, can guarantee that like this travelling speed of veneer is very fast.The effect of SDRAM on veneer is considerable, therefore is necessary it is comprehensively tested.

The method of carrying out the SDRAM test at present is as follows:

One, single board starting finishes after some necessary initialization and self check, and directly operation test procedure in FLASH (or other ROM) is comprehensively tested data line, address wire and the unit of SDRAM all on the veneer.If test is not passed through, then by lighting a lamp or alternate manner reports error message.If test is passed through, then the program among the FLASH (or other ROM) is moved among the SDRAM, carry out other operation then.

Two, single board starting finishes after some necessary initialization and self check, and directly operation test procedure in FLASH (or other ROM) is comprehensively tested data line, address wire and the unit of sub-fraction SDRAM on the veneer.If test is not passed through, then by lighting a lamp or alternate manner reports error message.If test is passed through, then the program among the FLASH (or other ROM) is moved among the SDRAM that had tested, and then determined whether and need other SDRAM be tested according to the demand (may be test command) of reality.

Because directly operation in FLASH (or other ROM) of test procedure is so speed is slower.In order to improve the efficient of test speed and test code, above-mentioned test procedure generally will be write with assembly language, and is higher relatively to developer's requirement.

In addition, veneer generally all be after program is moved among the SDRAM just serial ports or the network interface to veneer carry out initialization, serial ports and network interface all also do not have initialization when using the test procedure of present method debugging SDRAM, be inconvenient to export detailed Debugging message, can only be by lighting a lamp or other simple mode is exported Debugging message, therefore debugging difficulty relatively.

Summary of the invention:

Purpose of the present invention is exactly in order to overcome the above problems, and a kind of dynamic memory function test method is provided, and improves test speed.

For achieving the above object, the present invention proposes a kind of dynamic memory function test method, it is characterized in that its segmentation is tested, and its step is as follows: 1) will be stored in the program in the electricity erasable memorizer, and wherein comprise test procedure, and move in the dynamic storage; 2) move finish after, first one section dynamic storage all not using of all programs of test is if find that this section has problem, then reports error message after test is finished; 3) if this section is no problem, test procedure is moved certain ad-hoc location in the dynamic storage that this section tested, and will use but content in one section dynamic storage to be tested is moved in the dynamic storage that this section tested and preserved, calling test procedure then tests this section storer to be tested, after test is finished, with the content recovery of just preserving before the test; 4) repeat the 3rd) step, another section used but dynamic storage to be tested is tested, up to having surveyed all each sections; If in test process, pinpoint the problems, then report error message, interrupt test.

Owing to adopted above scheme, test procedure is moved dynamic storage just operation later on, utilize the fast advantage of dynamic storage travelling speed, improved test speed greatly.Owing to before the internal memory that each section of test used, all content is wherein preserved, after test is finished, recovers again, so program can normally be moved always.After test speed improves, require nature just to reduce, so also just needn't adopt assembly language again the efficient of test program code, also just passable with common higher level lanquage (as the C language), greatly facilitate programming.

Description of drawings:

Fig. 1 is a CPU minimum system synoptic diagram on the veneer.

Fig. 2 is the schematic flow sheet of one embodiment of the invention.

Fig. 3 is the testing process synoptic diagram of each section.

Embodiment:

Also the present invention is described in further detail in conjunction with the accompanying drawings below by specific embodiment.

Circuit shown in Figure 1 is common in all kinds of veneers of various products, and it is the part of CPU minimum system, and this is a kind of very general method for designing.For different veneers, the CPU kind, the model of SDRAM and capacity may be different.The importance of this part circuit on veneer is conspicuous, therefore must comprehensively test this partial circuit before veneer dispatches from the factory.

In general, board software all is kept among the FLASH (or other ROM), if program is not moved among the SDRAM, and the test procedure that directly moves (or other ROM) among the FLASH comprehensively tests SDRAM, and the test duration may be long.For example, we find in the process of test that directly working procedure test 32M SDRAM needs clock more than a minute from FLASH, and use same method of testing, and code is moved the test procedure test 32M SDRAM that reruns among the SDRAM then only needs more than ten second.Under the identical situation of hardware environment, test duration mainly is to be decided by the number of times that each unit is read and write, but when using same method of testing, with code move rerun among the SDRAM with directly in FLASH operation compare and have very remarkable advantages aspect the testing efficiency.After moving veneer initialize routine and test procedure among the SDRAM,, let us comprehensively be tested at inconvenience to all unit of SDRAM because test procedure has taken some unit of SDRAM.Here it is why prior art have the reason of above-mentioned shortcoming.

Here testing the method for SDRAM unit in fact tests its segmentation exactly.Program is moved after the SDRAM, the high-end SDRAM unit that elder generation's testing single-board initialize routine and other program (comprising test procedure) all do not use, if find that high-end SDRAM has problem after test is finished, then report the information of makeing mistakes, comprise the element address of makeing mistakes, the data that write, the data of reading, be easy to find out the data line, address wire or the chip that have fault like this, be convenient to produce maintenance.If high-end SDRAM is no problem, then to the SDRAM segmentation of low side, every section is carried out " preserving data (program) (moves), and--test low memory (test)--returns to the preceding state (recovery) of test with data (program) " successively in high-end internal memory, in this process, note abnormalities as long as test, just report error message, withdraw from the test procedure of SDRAM.The basic test flow process of SDRAM circuit is (process flow diagram is that example is drawn with 32M SDRAM test, only as an example) as shown in Figure 2.

Shown in Figure 3 is testing process in every section.Wherein used algorithm is divided into (WALK-0) two kinds of algorithms of walking " 1 " algorithm (WALK-1) and walking " 0 ", and two kinds of algorithms preferably adopt simultaneously, can certainly adopt wherein a kind of separately.The method of this test data line and address wire also can be used for testing mailbox and FLASH circuit.

The initial testing vector of walking " 1 " algorithm is 1,0,0 ..., 0.Allow 1 order be shifted then, so be called walking " 1 " algorithm.The test vector number of this algorithm is n.For example n=7 the time, then test vector is:

1000000

0100000

0010000

0001000

0000100

0000010

0000001

For the peripheral interconnecting test of storer is exactly to carry out read-write operation 7 times.Walking " 1 " algorithm can carry out accurate localization to fault.

Walking " 0 " algorithm and walking " 1 " algorithm complementation, its initial testing vector is 0,1,1 ..., 1.Allow 0 order be shifted then, so be called walking " 0 " algorithm.The test vector number of this algorithm also is n.For example n=7 the time, then test vector is:

0111111

1011111

1101111

1110111

1111011

1111101

1111110

Test is exactly to carry out read-write operation 7 times for the memory interconnect line.Walking " 0 " algorithm also can carry out accurate localization to fault.

Walking in theory " 1 ", walking " 0 " should be as broad as long, so the two can be chosen any one kind of them.As: for the normal low and normal high fault of the sort of data line, address wire, be easy to find out with the method for walking " 1 ".But exception is also arranged sometimes, for example,, may use the method for walking " 1 " to survey failsafe, and can measure fault with walking " 0 " at the soft fault (when for example the resistance to earth of the data line of fault is about more than 30 ohm) of critical conditions; Otherwise it is also possible.Owing to carry out walking test one time more, only carry out writing for tens times, read operation more, how long waste yet, therefore suggestion is carried out the method for walking " 1 " and walking " 0 " when testing simultaneously, with the test mass of assurance data line, address wire.

This method of testing to each unit of tested SDRAM all carried out writing, read-around ratio operation, should be more complete and reliable for general application.Because this method of testing is fairly simple, for the general SDRAM cell failure of test, obtained effect preferably through this method on probation, the time of for example testing 32M SDRAM is approximately more than 10 second, and this method helps us to find many SDRAM cell failures in production test.

Some data in will the attention program when using this method should decide according to the size of the SDRAM that is tested, and the method that provides above should flexible Application, such as: during sectionalization test each " section " get much, or the like.Following Example can help choosing of reader understanding " section ": on a kind of veneer of certain product 16M SDRAM is arranged, after program is moved, may be the 9th, Useful Information is arranged in the memory headroom of 10M, the high 8M of test earlier when if we adopt method of the present invention, 8M is hanged down in (4M, 4M) test more at twice, program just might be run in when debugging fly (make mistakes, overflow) because will be wherein when the high 8M of test the 9th, the useful information in the memory headroom of 10M destroyed.If but adopted the high 6M of test earlier, would divide the method for the low 10M of three times (3M, 3M, 4M) test just problem to be solved again; Perhaps adjust a little, (5M, 5M) also can solve problem at twice.

Certainly, the not necessarily strictness of choosing in proper order also of " section " is chosen to low side successively from high-end, as long as have routine data and test can not travel through all SDRAM unit in selecteed at first " section ".

In a word, because test procedure reruns in moving SDRAM, speed is very fast.The feasible requirement to program efficiency of the quickening of speed reduces, thereby can utilize higher level lanquage to carry out programming, directly uses the C language compilation as test procedure, requires lower to the developer.In addition, it is to test later at serial ports or network interface initialization again, is easy to export various Debugging message, and debugging is got up very convenient.The present invention successfully has been applied in the Board Functional Test, Board Function Test of several products, has passed through the checking of long period and veneer in enormous quantities, and effect is very good.

Claims

1, a kind of dynamic memory function test method is characterized in that: its segmentation is tested, and its step is as follows: 1) will be stored in the program in the electricity erasable memorizer, and wherein comprise test procedure, and move in the dynamic storage; 2) move finish after, first one section dynamic storage all not using of all programs of test is if find that this section has problem, then reports error message, interrupt test after test is finished; 3) if this section is no problem, test procedure is moved certain ad-hoc location in the dynamic storage that this section tested, and will use but content in one section dynamic storage to be tested is moved in the dynamic storage that this section tested and preserved, calling test procedure then tests this section storer to be tested, after test is finished, with the content recovery of just preserving before the test; 4) repeat the 3rd) step, another section used but dynamic storage to be tested is tested, up to having surveyed all each sections; If in test process, pinpoint the problems, then report error message, interrupt test.

2, dynamic memory function test method as claimed in claim 1 is characterized in that: when moving program, all programs in the electrically-erasable storer are together moved with test procedure, moved the low side that all routine datas of back are stored in dynamic storage; During sectionalization test be according to test-move-test-recover-move-test from high-end order to low side-recover, up to the test of finishing all sections.

3, dynamic memory function test method as claimed in claim 1 or 2 is characterized in that: every period when test, with in walking " 1 " algorithm and walking " 0 " algorithm one or both carry out data line, address wire is tested.

4, dynamic memory function test method as claimed in claim 1 or 2 is characterized in that: test later at serial ports or network interface initialization, so that carry out program debug and report test result again.