CN1414718A - Receiving filter of CDMA system - Google Patents

Abstract

A receiving filter of CDMA system can be formed by connecting seveal low-order FIR filters and several IIR filters in series and the its mathematical presentation should be equivalent to a single high-order FIR filter in accordance with the requirement of specific CDMA system. The said low-order FIR filter can obtain the filtering output by utilizing the input data and the shifting addition of filter parameters, the said IIR filter can obtain the filtering output through the data addition of the last one code slice and the present code slice according to the bit. The present invention has relatively smaller operation volume camparing with the original one, so the requirement for the hardware and the occupation to hardware resources can be lowered as well as comparatively faster speed rate of input signal can be achieved.

Description

A kind of receiving filter of cdma system

Technical field

The present invention relates to wireless communication technology field, particularly relate to a kind of receiving filter of cdma system.

Background technology

Stipulate that in the IS95 of cdma wireless communication system standard behind the transmitting terminal four phase spread spectrums, the signal of I, Q two-way will be input to two forming filter filtering respectively.The main effect of forming filter is limiting bandwidth and anti-intersymbol interference.The shaping filter of corresponding transmitting terminal will have matched filtering after the receiving terminal A/D conversion, makes input signal obtain maximum signal to noise ratio.Usually, forming filter adopts single FIR (finite impulse response) filter, and its exponent number increases with data sampling speed and forming filter exponent number during realization; And in the IS95B standard, after molding filtration, also stipulated a phase equalization filter, and this phase equalization filter provides Phase synchronization to signal, and purpose is in order to simplify the design of travelling carriage part receiving filter; Corresponding therewith, in the IS97 standard, defined a benefit filter as receiving filter, this filter is realized being complementary with transmission filtering (being made up of jointly molding filtration and phase equalization), purpose will realize not having intersymbol interference, and amplitude-frequency is corresponding similar with transmission filtering, because recipient's sampling rate is very high, mend filter and adopt single FIR filter to realize routinely if receive, but relative forming filter further increases again during its exponent number.Though the FIR filter order is high more, also just mean better filtering performance, but since the FIR filter be utilize its parameter and input data mutually multiply accumulating realize, therefore also along with the increase of exponent number is the geometric progression multiplication, this also means the hardware requirement of more hardware resource of needs and Geng Gao to its operand.On the other hand, IIR (endless unit impact response) filter is under constructed index, owing to exist the feedback of output to input, thereby the available exponent number more less than FIR filter satisfy the requirement of index, and promptly used memory cell is few, and operand is little.

Summary of the invention

Technical problem to be solved by this invention be exactly how to provide a kind of few to the hardware resource requirement, operand is little and performance and high order FIR receive and mend the suitable reception of filter and mend filter.

The present invention solves the problems of the technologies described above the technical scheme that is adopted: several low orders FIR filter and several IIR (infinitely impacting corresponding) filter are connected into a new filter, and its mathematical expression are equivalent to meet the single high order FIR filter of specific CDMA system requirements.

Described low order FIR filter can utilize the data of input and filter parameter shifter-adder to obtain filtering output; Described iir filter can obtain filtering output by going up a chip and current chip data step-by-step addition.

Compared with prior art, the present invention satisfies the high order FIR filter of mending the filter standard in the IS97 standard with one and converts several low orders FIR filter and several iir filters dexterously to, because the operand of low order FIR filter and iir filter is relative much smaller, therefore the total operand of benefit filter that should synthesize will be much smaller than original single high order FIR filter, thereby reduce to the requirement of hardware with to the taking of hardware resource, and input signal speed faster can be arranged.

Description of drawings

Fig. 1 is the amplitude-frequency corresponding figures that filter is mended in the acceptance of a needs realization.

Fig. 2 is the pulse corresponding figures that transmitting filter links to each other with benefit filter shown in Figure 1.

Fig. 3 is the anti-intersymbol interference figure of benefit filter shown in Figure 1.

Fig. 4 is the realization block diagram at benefit filter shown in Figure 1.

Embodiment

Below in conjunction with accompanying drawing embodiment invention is described in further detail.

Benefit filter in the CDMA-IS97 standard comes down to a high order FIR filter, as the filter with following system function is exactly an example wherein: $H\left(z\right)=\underset{k=1}{\overset{\[n/2\]}{\mathrm{\Π}}}\[a_k+{{(b_k-{2a}_k)}_Z}^{-1}+{{(a_k+c_k-2b_k)}_Z}^{-2}+{{(b_k-{2c}_k)}_Z}^{-3}+{c_{k_Z}}^{-4}\]$

Following formula is carried out conversion, $H\left(z\right)=\underset{k=1}{\overset{\[n/2\]}{\mathrm{\Π}}}\[a_k+{{(b_k-{2a}_k)}_Z}^{-1}+{{(a_k+c_k-2b_k)}_Z}^{-2}+{{(b_k-{2c}_k)}_Z}^{-3}+{c_{k_Z}}^{-4}\]$ $=\underset{k=1}{\overset{\[n/2\]}{\mathrm{\Π}}}\{\[a_k+{{(b_k-a_k)}_Z}^{-1}+{{(c_k-b_k)}_Z}^{-2}+{c_{k_Z}}^{-3}\]\frac{1}{1-z^{-1}}\}$ $=\underset{k=1}{\overset{\[n/2\]}{\mathrm{\Π}}}\[(a_k+{b_{k_Z}}^{-1}+{c_{k_Z}}^{-2})\frac{1}{(1-z^{-1})}\frac{1}{(1-z^{-1})}\]$

And $\underset{k=1}{\overset{\[n/2\]}{\mathrm{\Π}}}\[(a_k+{b_{k_Z}}^{-1}+{c_{k_Z}}^{-2})\frac{1}{(1-z^{-1})}\frac{1}{(1-z^{-1})}\]$ Represent that promptly this filter can be converted to [n/2] individual FIR filter and add [n/2] individual iir filter, perhaps be converted to [n/2] individual FIR filter and add 2 * [n/2] individual iir filters.

With our a needed receiving filter is example, and it has amplitude-frequency response as shown in Figure 1, and its bandwidth is 580K, cut-off frequency is 760K, with transmission filtering essentially identical amplitude-frequency response is arranged, it also satisfies the requirement with outer rejection ratio in addition, and minimum is 21dB;

The impulse response that transmitting filter links to each other with this benefit filter (8 times of spreading rates samplings) as shown in Figure 2;

Regularly on time, impulse response in the value (its maximum intersymbol interference value is 0.0561, satisfies the requirement of system to intersymbol interference) of sampled point (1 times of spreading rate sampling) as shown in Figure 3;

In design, following 3 difficult points are arranged:

(1) will realize on an APEX20K100 that 6 (3 sectors, I/Q two-way) accept filter, the unit of the multipotency utilization of each filter is no more than 600 logical blocks;

(2) Shu Ru signal rate very fast (8 times spreading rate is for sending 8 times of filtering) can not realize with the same method of timesharing that adopts of transmission filtering, also promptly can not make full use of the effect of memory cell;

(3) the exponent number height (31 rank delay line FIR filtering, and send filtering be essentially realize 4 13 rank filtering), as directly by filter factor and input mutually multiply accumulating realize need be a large amount of logical block (1400 logical blocks of minimum need).

In order to overcome the above problems, according to design of the present invention, utilize the correlation between the filter factor, we provide the conversion regime to this high order FIR filter: $C_0\left(z^{-1}\right)=C_1\left(z^{-1}\right)\frac{1}{{(1-z^{-1})}^2}$

Receiving and mending filter is C ₀(z ^-1), be the FIR filter of a high-order, C ₁(z ^-1) be the FIR filter of a low order, Can be by two

Filter (IIR) series connection realizes;

After like this FIR filter being converted to the series connection of FIR filter and two iir filters, in the coefficient of FIR filter, major part is zero, and other coefficient is 1 ,-1,2 ,-2,4, the parameter multiplying of FIR filter very simple (simple displacement), the resource that takies seldom can utilize the data of input and filter parameter shifter-adder to obtain filtering output, also promptly can utilize direct phase multiply accumulating to realize; The computing of two iir filters is also simple relatively, can obtain filtering output by going up a chip and current chip data step-by-step addition.The receiving filter that adopts this structure to realize forms behind the hardware description language that comprehensive required logical block is roughly 550 under Quatus.

The specific implementation block diagram that this accepts filter as shown in Figure 4; Wherein, the input figure place is relevant with the precision of A/D conversion, the precision height, and figure place is just many; Quantification is in order to adapt to the needs of modules such as receiving terminal search tracking.

Claims (3)

1, a kind of receiving filter of cdma system, it is characterized in that it is connected into and is formed by several low orders FIR filter and several IIR (infinitely impacting corresponding) filter, and its mathematical expression is equivalent to meet the single high order FIR filter of specific CDMA system requirements.

2, the receiving filter of cdma system according to claim 1 is characterized in that the data of described low order FIR filter utilization input and filter parameter shifter-adder obtain filtering output.

3, the receiving filter of cdma system according to claim 1 and 2 is characterized in that described iir filter obtains filtering output by going up a chip and current chip data step-by-step addition.

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