CN1409322A - Circuit structure for simulating polarizing relaxation in ferroelectric memory - Google Patents
Circuit structure for simulating polarizing relaxation in ferroelectric memory Download PDFInfo
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- CN1409322A CN1409322A CN 01142273 CN01142273A CN1409322A CN 1409322 A CN1409322 A CN 1409322A CN 01142273 CN01142273 CN 01142273 CN 01142273 A CN01142273 A CN 01142273A CN 1409322 A CN1409322 A CN 1409322A
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Abstract
A circuit structure for the emulational ferroelectric memory polarized realxation phenomenon, which comprises: a MOS transistor whose grid is coupled to the word line and the source is coupled to the bit line; a ferroelectric capacitor whose one terminal is coupled to the drain of the MOS transistor and another terminal is coupled to the electrode line; a capacitor whose one terminal is coupled to the drain of the MOS transistor; a realxation voltage source whose one terminal is coupled to the another terminal of the capacitor, and another terminal is coupled to the ground. The capacitance of the capacitor is much smaller than that of the bit line ,the output voltage of the realxation voltage source has the logarithmic and time correlation.
Description
Technical field
The invention relates to a kind of artificial circuit of memory behavior, particularly relevant for the artificial circuit of a kind of ferroelectric internal memory (FeRAM) characteristic, especially specifically about a kind of circuit structure of relaxation that can the emulation ferroelectric internal memory.
Background technology
The storage unit of ferroelectric internal memory and general dynamic RAM (dynamicalrandom access memory, storage unit DRAM) has similar structure; That is to say to have a MOS transistor and an electric capacity.Two kinds of storage unit all utilize word line and bit line to come the work of control store unit.Difference between the two is that the electrode in the electric capacity in the FeRAM storage unit need be connected to a drive wire, and this drive wire is non-existent in the DRAM storage unit.Word line, bit line and drive wire in the FeRAM storage unit apply suitable bias voltage respectively, operations such as just can reading, write and wipe the FeRAM storage unit.
Fig. 1 illustrates the retardant curve (hysteresis loop) of ferroelectric internal memory.When a ferroelectric material was applied voltage (extra electric field), amount of polarization can begin to increase.Afterwards, after voltage was applied to a certain amount of (for example about 5V), amount of polarization can begin to diminish.But when voltage was got back to 0V, the polarization quantitative change can't get back to 0, but arrived P
R+Yet when voltage was got back to 0V, amount of polarization can't arrive P in fact,
R+, but slightly little P
Rel+At this moment, just there is P
Rel+-P
R+Difference.After voltage (negative voltage) was continuously applied a certain amount of (for example-about 5V), it is big that amount of polarization can begin to become.But when voltage was got back to 0V, the polarization quantitative change can't get back to 0, but arrived P
R-Yet when voltage was got back to 0V, amount of polarization can't arrive P in fact,
R-, but slightly little P
Rel-At this moment, just there is P
R--P
Rel-Difference.Here it is because the phenomenon that dipole alignment relaxation (polarization relaxation) is caused.
The dipole alignment relaxation phenomenon causes when voltage is 0V, and retardant curve presents discontinuous characteristic and occurs, and that is to say that having a space (gap) produces (P
Rel+-P
R+Or P
R--P
Rel-).Yet the circuit model of at present general ferroelectric internal memory is all set up according to desirable retardant curve, does not consider the dipole alignment relaxation phenomenon.
Fig. 2 illustrates the artificial circuit of known ferroelectric internal memory.The circuit structure of this ferroelectric storage cell comprises MOS transistor 10 and ferroelectric capacitor 12, except ferroelectric capacitor 12 and electrode wires (plateline, PL) outside, all the other are identical with general DRAM.The grid of MOS transistor 10 is couple to word line WL, and source electrode is couple to bit line BL, and drain electrode is couple to an end of ferroelectric capacitor 12.The other end of ferroelectric capacitor 12 is couple to a strip electrode line (plate line) PL.In operation, in the time will writing " 0 " to storage unit, just with electrode wires PL ground connection, and with power supply V
DDBe applied on the bit line; Otherwise, in the time will writing " 1 ", just with power supply V to storage unit
DDBe applied to electrode wires PL, and with bit line ground connection.So just can carry out the write operation of ferroelectric internal memory.In the time will reading ferroelectric storage, with power supply V
DDBe applied to electrode wires PL, and bit line is floated.
Yet, when the inherent characteristic of the retardant curve of considering ferroelectric material, the description retardant curve that the artificial circuit of known ferroelectric internal memory just can't be correct.Fig. 3 illustrates the retardant curve comparison diagram, with relatively actual to measured retardant curve of ferroelectric internal memory and retardant curve so that known artificial circuit was simulated.As shown in Figure 3, ordinate is amount of polarization (μ C/cm
2), horizontal ordinate is voltage (V).The mark that indicates square is represented the result of actual measurement, and the result that solid line partly represents to utilize the emulation of known artificial circuit institute to come out.When the amount of polarization of actual measurement ferroelectric material when voltage is 0V, have the phenomenon that increases suddenly or die-off; That is to say, can have a space, Here it is a kind of non-continuous event.But, when coming emulation with known artificial circuit, from figure circle part 20 as can be seen, when voltage was 0V, the retardant curve I that known artificial circuit simulated was for changing continuously.That is to say that known artificial circuit can only present desirable retardant curve, and can't accurately represent this characteristic that has of ferroelectric material.
Above-mentioned circuit model has the phenomenon appearance that makes sensing voltage too exaggerative when carrying out the emulation of ferroelectric internal memory, and can't verily reflect the sensing voltage characteristic of ferroelectric internal memory.The dipole alignment relaxation phenomenon of one of most important effect can cause quick decay (fast-decaying) in the ferroelectric internal memory, makes in sensing border (sense margin) variation of switching between the accurate position of (switching) and non-switching (non-switching).
As mentioned above, general known artificial circuit all lacks the ability that can simulate the dipole alignment relaxation phenomenon, seriously influences so all cause at the design and research of ferroelectric internal memory, can't simulate the physical characteristics of ferroelectric internal memory effectively.
Summary of the invention
Therefore, the objective of the invention is to propose a kind of circuit structure of emulation ferroelectric internal memory dipole alignment relaxation phenomenon, the discontinuous characteristic that it can correctly simulate the retardant curve of ferroelectric material also can present the dipole alignment relaxation phenomenon in addition.
Another object of the present invention is the circuit structure that proposes a kind of emulation ferroelectric internal memory dipole alignment relaxation phenomenon, it can correctly simulate the discontinuous characteristic of the retardant curve of ferroelectric material, make it when carrying out the ferroelectric internal memory design and research, can correctly simulate the physical characteristics of ferroelectric internal memory.
For reaching above-mentioned purpose, the present invention proposes a kind of circuit structure of emulation ferroelectric internal memory dipole alignment relaxation phenomenon, is made of following device.The grid of one MOS transistor is couple to word line, and source electrode is couple to bit line; One end of one ferroelectric capacitor is couple to the drain electrode of MOS transistor, and the other end is couple to electrode wires; One electric capacity and an end are connected to the drain electrode of MOS transistor; One end of one lax voltage source is coupled to the other end of electric capacity, and the other end ground connection of lax voltage source.The capacitance of above-mentioned electric capacity is selected the capacitance much smaller than bit line, and the output voltage of lax voltage source is logarithmic time relevant (logarithmic time dependence).
The present invention also proposes a kind of circuit structure of emulation ferroelectric internal memory dipole alignment relaxation phenomenon, is made of following device.One MOS transistor; One end of one ferroelectric capacitor is couple to the drain electrode of MOS transistor, and the other end receives control voltage, so that ferroelectric capacitor work; One end of one electric capacity is connected to the drain electrode of MOS transistor; One lax voltage source is coupled to electric capacity.The output voltage of above-mentioned lax voltage source is that logarithmic time is relevant.
Thus, utilization of the present invention connects a lax voltage source in the artificial circuit of ferroelectric storage cell, and making its output voltage is that logarithmic time is relevant.Whereby, can positively simulate the discontinuous characteristic of the retardant curve of ferroelectric material.In addition, when prediction or design, can more can grasp the physical characteristics of ferroelectric internal memory.
Description of drawings
Fig. 1 illustrates the retardant curve of general ferroelectric internal memory;
Fig. 2 illustrates the artificial circuit of known ferroelectric internal memory;
Fig. 3 illustrates the retardant curve comparison diagram, with relatively actual to measured retardant curve of ferroelectric internal memory and retardant curve so that known artificial circuit was simulated;
Fig. 4 illustrates the circuit simulation framework of ferroelectric internal memory of the present invention;
Fig. 5 illustrates an embodiment of the lax voltage source among Fig. 4;
Fig. 6 illustrates the relation curve of slack time and voltage, and it shows the attenuation rate in the lax composition (relaxedcomponent);
Fig. 7 illustrates retardant curve figure, the simulation result that it indicates the result of actual measurement ferroelectric internal memory and utilizes artificial circuit of the present invention;
Fig. 8 illustrates the electric current and the time relation figure of resistive load, and it is respectively and switches accurate position (first) and non-actual measurement and the simulation result that switches between the accurate position (second);
Fig. 9 illustrates the graph of a relation between slack time and the sensing voltage, is respectively the simulation result that utilizes well known model and model of the present invention.
Description of reference numerals:
10 MOS transistor
12 ferroelectric capacitors
14 lax voltage sources
Embodiment
The present invention is the circuit that adds the relaxation that can simulate ferroelectric material in the artificial circuit of ferroelectric internal memory.When coming the behavior of emulation ferroelectric internal memory, just can fully show the actual physics behavior of ferroelectric internal memory, make the behavior that when carrying out emulation, can predict ferroelectric internal memory more accurately by lax voltage source provided by the present invention.
Fig. 4 illustrates the circuit simulation structure of ferroelectric internal memory of the present invention.The circuit structure of this ferroelectric storage cell comprises a MOS transistor 10, a ferroelectric capacitor 12, a linear capacitance Cr and a lax voltage source 14.The grid of MOS transistor is couple to word line WL, and source electrode is couple to bit line BL, and drain electrode is couple to an end of ferroelectric capacitor 12.The other end of ferroelectric capacitor 12 is couple to a strip electrode line (plate line) PL.The end of linear capacitance Cr is connected to the drain electrode of MOS transistor 10, and the other end then is connected to an end of lax voltage source 14.The other end of lax voltage source 14 is ground connection then.The capacitance of above-mentioned linear capacitance Cr is selected the capacitance much smaller than bit line, and it is logarithmic time relevant (logarithmictime dependence) that lax 14 of voltage sources have output voltage.The present invention utilizes lax voltage source 14 positively to simulate the operating characteristic of ferroelectric storage cell.
Fig. 5 illustrates an embodiment of the lax voltage source among Fig. 4.The circuit diagram that is noted that Fig. 5 only is an example, and the output voltage of any circuit is that logarithmic time is relevant, all can be used as lax voltage source of the present invention.
As shown in Figure 5, lax voltage source 14 is made of first resistance R 1, the first operational amplifier OP1, capacitor C 1, second resistance R 2, the second operational amplifier OP2 and diode D.One end of first resistance R 1 is couple to the wherein input end of the first operational amplifier OP1, and the other end then is connected to input voltage vin.Capacitor C 1 is coupled between the output terminal and input end of the first operational amplifier OP1.Second resistance R 2 is coupled to output terminal and wherein between the input end of the second operational amplifier OP2 of the first operational amplifier OP1.Diode D is coupled between the output terminal and input end of the second operational amplifier OP2.
According to circuit knowledge, be familiar with the satisfied following equation of output voltage V out that this operator can calculate above-mentioned lax voltage source 14:
V wherein
0, I
0Characterisitic parameter for this diode D.Generally speaking, can know that the electric current that flows through this diode can be tried to achieve by following equation by the circuit characteristic of diode.
The output voltage V out that can clearly find out lax voltage source 14 from above-mentioned equation is directly proportional with the logarithm of time; That is to say that output voltage is that logarithmic time is relevant.
Above-mentioned lax voltage source 14 can be exported has drawing high/draw and falling voltage (pull-up/down voltage) signal of logarithm dependence relation, and the differentiation that is used for simulating the polarization characteristic of ferroelectric material whereby changes.
Below just come the result of comparison actual measurement ferroelectric internal memory, and the simulation result that utilizes artificial circuit of the present invention at several physical characteristicss.Through following explanation, just can understand artificial circuit proposed by the invention really can be very accurately near the behavioral trait of actual ferroelectric internal memory.
Fig. 6 illustrates the relation curve of slack time and voltage, and it shows the attenuation rate in the lax composition (relaxedcomponent).In Fig. 6, the mark that indicates square is represented the result of actual measurement, and solid line partly represents to utilize the measured result who comes out of the circuit of Fig. 4.
As shown in Figure 6, after it illustrates and connects a capacity load, measured impulse response (pulse response).Ordinate is voltage V (t), and horizontal ordinate is slack time (μ s).In the ferroelectric storage cell of reality, the voltage of lax composition can reduce along with the increase of slack time, that is to say decay fast.As shown in Figure 6, the result of actual measurement (square mark) demonstrates this characteristic.Clearly coincide according to the result that circuit model of the present invention simulated, demonstrate this phenomenon of decay fast with actual measured results.Therefore, ferroelectric internal memory artificial circuit of the present invention can positively be predicted the behavioral trait of ferroelectric storage cell.
Fig. 7 illustrates the retardant curve figure of ferroelectric internal memory, in order to the result of simulation result more of the present invention and actual measurement.As shown in Figure 7, ordinate is amount of polarization (μ C/cm
2), horizontal ordinate is voltage (V).The mark that indicates square is represented the result of actual measurement, and the result that solid line partly represents to utilize the circuit institute emulation of Fig. 4 to come out.Be noted that the circle part of amplifying among the figure especially.As previously mentioned, the retardant curve of ferroelectric material has uncontinuity, that is to say that when voltage was 0V, amount of polarization can increase or die-off suddenly, and produces a space (gap).Can find out significantly by Fig. 7, utilize the lax voltage source 14 of artificial circuit of the present invention can accurately simulate discontinuous (space) characteristic in the retardant curve.Therefore, under known artificial circuit was compared, known circuits shown in Figure 2 can only simulate continuous retardant curve, and can't simulate the air gap characteristics in the retardant curve.The result can understand thus, and the present invention can do accurate and the most certain prediction and emulation to ferroelectric material.
Fig. 8 illustrates electric current and time relation figure, and it is connected to a resistive load with ferroelectric capacitor, and the electric current of measuring by this resistive load concerns over time.Fig. 8 is respectively to switching the actual measurement and the simulation result of the accurate position of (switching) accurate position (Fig. 8 first half) and non-switching (non-switching) (Fig. 8 Lower Half).Solid line among the figure partly presents the electric current and the time chart of actual measurement, and dotted line is then represented the simulation result according to artificial circuit of the present invention.Can clearly be seen that by Fig. 8 the simulation result of artificial circuit of the present invention is consistent with the measurement result of reality.That is to say that artificial circuit of the present invention can very accurately simulate the physical characteristics of ferroelectric storage cell really.
Fig. 9 illustrates the graph of a relation between slack time and the sensing voltage (sense voltage), is respectively and utilizes known and of the present invention simulation result.It is that storage unit to a 2T/2C (two-transistor/two electric capacity) is estimated the influence of relaxation effect to sensing voltage that Fig. 9 illustrates.Part i among the figure is presented at electrode wires PL and applies during the voltage, the influence of the sensing voltage when increase slack time on the pairs of bit line; Part ii is presented at electrode wires PL and applies after the voltage, the influence of the sensing voltage when increase slack time on the pairs of bit line.Square mark among the figure is the simulation result that known artificial circuit is used in expression, and round mark then represents to use the simulation result of artificial circuit of the present invention.In circuit model of the present invention, sensing voltage can greatly reduce as can be seen from Figure.On the contrary, the sensing voltage that known artificial circuit simulated almost remains unchanged.
In sum, feature of the present invention connects a lax voltage source in ferroelectric storage cell, and making its output voltage is that logarithmic time is relevant.Whereby, can positively simulate the discontinuous characteristic of the retardant curve of ferroelectric material.
Another feature of the present invention makes it can more can grasp the physical characteristics of ferroelectric internal memory by adding the characteristic that lax voltage source comes the emulation ferroelectric internal memory when prediction or design.
In sum, though the present invention with preferred embodiment openly as above, so is not in order to limit the present invention; anyly be familiar with this operator; without departing from the spirit and scope of the present invention, when can doing various changes, so protection scope of the present invention is as the criterion with claims.
Claims (12)
1. the circuit structure of an emulation ferroelectric internal memory dipole alignment relaxation phenomenon is characterized in that: comprising:
One MOS transistor, its grid is couple to a word line, and its source electrode is couple to a bit line;
One ferroelectric capacitor, an end is couple to the drain electrode of MOS transistor, and the other end is couple to an electrode wires;
One electric capacity, an end is connected to the drain electrode of MOS transistor;
One lax voltage source, the one end is coupled to the other end of this electric capacity, and the other end ground connection of voltage source that should relax.
2. the circuit structure of emulation ferroelectric internal memory dipole alignment relaxation phenomenon as claimed in claim 1 is characterized in that: the capacitance of this electric capacity is selected the capacitance much smaller than this bit line.
3. the circuit structure of emulation ferroelectric internal memory dipole alignment relaxation phenomenon as claimed in claim 1 is characterized in that: this electric capacity is a linear capacitance.
4. the circuit structure of emulation ferroelectric internal memory dipole alignment relaxation phenomenon as claimed in claim 1 is characterized in that: the output voltage of this lax voltage source is logarithmic time relevant (logarithmictime dependence).
5. the circuit structure of emulation ferroelectric internal memory dipole alignment relaxation phenomenon as claimed in claim 1 is characterized in that: wherein should also comprise by lax voltage source:
One first resistance has first end and one second end that is couple to an input voltage;
One first operational amplifier has an input end that is couple to second end of first resistance, with an output terminal;
One electric capacity is coupled between the input end and output terminal of first operational amplifier;
One second operational amplifier has an input end and an output terminal;
One second resistance is coupled between the input end of the output terminal of first operational amplifier and second operational amplifier;
One diode is coupled between the input end and output terminal of this second operational amplifier.
6. the circuit structure of an emulation ferroelectric internal memory dipole alignment relaxation phenomenon is characterized in that: comprising:
One MOS transistor, its grid is couple to a word line, and its source electrode is couple to a bit line;
One ferroelectric capacitor, an end is couple to the drain electrode of MOS transistor, and the other end is couple to an electrode wires;
One lax voltage source, the one end is coupled to the drain electrode of this MOS transistor, and the other end ground connection of lax voltage source.
7. the circuit structure of emulation ferroelectric internal memory dipole alignment relaxation phenomenon as claimed in claim 6 is characterized in that: the output voltage of the voltage source that wherein should relax is logarithmic time relevant (logarithmic time dependence).
8. the circuit structure of emulation ferroelectric internal memory dipole alignment relaxation phenomenon as claimed in claim 6 is characterized in that: wherein should also comprise by lax voltage source:
One first resistance has first end and one second end that is couple to an input voltage;
One first operational amplifier has an input end and an output terminal that is couple to second end of this first resistance;
One electric capacity is coupled between the input end and output terminal of first operational amplifier;
One second operational amplifier has an input end and an output terminal;
One second resistance is coupled between the input end of the output terminal of first operational amplifier and second operational amplifier;
One diode is coupled between the input end and output terminal of second operational amplifier.
9. the circuit structure of an emulation ferroelectric internal memory dipole alignment relaxation phenomenon is characterized in that: comprising:
One MOS transistor;
One ferroelectric capacitor, an end is couple to the drain electrode of this MOS transistor, and the other end receives a control voltage, so that ferroelectric capacitor work;
One electric capacity, an end is connected to the drain electrode of this MOS transistor;
One lax voltage source is coupled to this electric capacity.
10. the circuit structure of emulation ferroelectric internal memory dipole alignment relaxation phenomenon as claimed in claim 9 is characterized in that: wherein this electric capacity is a linear capacitance.
11. the circuit structure of emulation ferroelectric internal memory dipole alignment relaxation phenomenon as claimed in claim 9 is characterized in that: the output voltage of lax voltage source is logarithmic time relevant (logarithmic timedependence).
12. the circuit structure of emulation ferroelectric internal memory dipole alignment relaxation phenomenon as claimed in claim 9 is characterized in that: wherein should also comprise by lax voltage source:
One first resistance has first end and one second end that is couple to an input voltage;
One first operational amplifier has second an end input end that is couple to first resistance, with an output terminal;
One electric capacity is coupled between the input end and output terminal of first operational amplifier;
One second operational amplifier has an input end and an output terminal;
One second resistance is coupled between the input end of the output terminal of first operational amplifier and second operational amplifier;
One diode is coupled between the input end and output terminal of second operational amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011422734A CN1324611C (en) | 2001-09-25 | 2001-09-25 | Circuit structure for simulating polarizing relaxation in ferroelectric memory |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011422734A CN1324611C (en) | 2001-09-25 | 2001-09-25 | Circuit structure for simulating polarizing relaxation in ferroelectric memory |
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| Publication Number | Publication Date |
|---|---|
| CN1409322A true CN1409322A (en) | 2003-04-09 |
| CN1324611C CN1324611C (en) | 2007-07-04 |
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|---|---|---|---|
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022160292A1 (en) * | 2021-01-29 | 2022-08-04 | 华为技术有限公司 | Ferroelectric memory and storage device |
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| US5867405A (en) * | 1996-03-01 | 1999-02-02 | Motorola, Inc. | Ferroelectric simulator, ferroelectric method of manufacture, and method of simulation |
| JPH11163280A (en) * | 1997-12-02 | 1999-06-18 | Matsushita Electron Corp | Method for simulating ferroelectric |
| JP2001148469A (en) * | 1999-11-19 | 2001-05-29 | Rohm Co Ltd | Extracting device for ferroelectric fet characteristic constant |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2022160292A1 (en) * | 2021-01-29 | 2022-08-04 | 华为技术有限公司 | Ferroelectric memory and storage device |
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