CN1391164A - On-off test method for motherboard of computer - Google Patents
On-off test method for motherboard of computer Download PDFInfo
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- CN1391164A CN1391164A CN 02122499 CN02122499A CN1391164A CN 1391164 A CN1391164 A CN 1391164A CN 02122499 CN02122499 CN 02122499 CN 02122499 A CN02122499 A CN 02122499A CN 1391164 A CN1391164 A CN 1391164A
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Abstract
A test for the on-off status of computer motherboard features that the circuit hardware with minimal command explanation units and test program control units is inserted to the standard interface of motherboard, and connected to the power switch and reset swith of motherobard. The turn-on, turn-off and reset of motherboard are automatically controlled by test program. The error detecting code output by motherboard is read by command explanation unit to judge on/off status, reset and sleep/wake-up are normal and record the result.
Description
Technical field
The present invention relates to a kind of computer main frame panel, and particularly relate to a kind of on-off test method for motherboard of computer.
Background technology
Along with the prosperity of electronics technology, necessity that computing machine has become information processing is equipped with, so number of computers is to shoot up, the stability of computer main frame panel is the phase fractal key also.In order to ensure the stability of computer main frame panel, when the motherboard manufacturing is finished, must to confirm its quality, wherein, repeat machine open/close test, replacement test and the test of power management sleep-awake and be an important test event by various testing standards.Yet, past relies on artificial practical operation power switch and reset switch mostly and carries out test, this kind mode is limited except testing time, so that for the repeatedly or continuous switching on and shutting down problem that just can occur of need, outside being difficult to detect, because of manually-operated efficient is very low, and do not have unified testing standard yet, and cause test accuracy not good.
In addition; other has, and CMOS sets the method that timed power on/off is realized the repeat switch machine in a kind of similar motherboard; though can avoid manually-operated shortcoming; but need after entering operating system; just can write down testing time, and if computing machine before entering operating system, shut down or stagnate, then can't continue test and not have a test result; the action and the hardware of software start are not quite similar still more, cause being difficult for the error on the detection hardware.
Summary of the invention
In view of this; the invention provides a kind of on-off test method for motherboard of computer; can automatically perform the repetition machine open/close test of motherboard, reset test and the test of power management sleep-awake; and note down automatically and show test results; need not manually-operated; can consequently there be test result because of the system-down in the test yet.
For reaching above-mentioned and other purpose, the invention provides a kind of on-off test method for motherboard of computer, comprise the following steps: at first foundation one presumptive test program, send a test control command in regular turn, with control ON/OFF and replacement computer main frame panel; Again as calculated a standard interface decipher one particular port address of machine host plate write data, whether normal to judge computer main frame panel, and record or show its test result in the lump.
Test control command wherein comprises the electric power on/off order and the order of resetting, and its presumptive test program comprises the machine open/close test, reset test and the test of power management sleep-awake.And the standard interface that computer main frame panel provides is a pci interface, and use input/output end port address 80H is the particular port address of its error detection.In addition, the displayable test result of this method of testing comprises testing time and the number of times that makes a mistake, and the time interval of each test control command wherein is for setting.
The present invention provides a kind of computer main frame panel on-off test device in addition, comprising: order interpretation unit and test procedure control module.Wherein, the order interpretation unit couples computer main frame panel via a standard interface, in order to the data that write of reception and decipher one particular port address, and will write the data latching preservation.The test procedure control module couples order interpretation unit and computer main frame panel, in order to according to a presumptive test program, send the test control command in regular turn, reading order interpretation unit breech lock writes data again, judging whether computer main frame panel is normal, and write down its test result.
In the preferred embodiment of the present invention, this computer main frame panel on-off test device is applied to the test of computer main frame panel, at this moment, this computer main frame panel on-off test device comprises that also test result display unit and test procedure select setup unit.The test result display unit couples the test procedure control module, in order to show its test result.Test procedure selects setup unit to be coupled to the test procedure control module, in order to set the above-mentioned presumptive test program of selecting.These presumptive test programs comprise the machine open/close test, reset test and the test of power management sleep-awake.
In the preferred embodiment of the present invention, this computer main frame panel on-off test device also also comprises and writes data display unit, in order to the data that write of display command interpretation unit breech lock.And above-mentioned test control command comprises the electric power on/off order and the order of resetting.In addition, the standard interface that this computer main frame panel on-off test device connects motherboard is PCI (PeripheralComponent Interconnect) interface, and the error detection particular port address that it uses is input/output end port address 80H.In test process and test when finishing, and can show and comprise testing time and the test result of the number of times that makes a mistake, and the time interval of each the test control command in the test procedure is for setting.
By in the above-mentioned explanation as can be known; use a kind of computer main frame panel on-off test device provided by the invention, method and system thereof; then need not come the Test Host plate with complicated manually-operated again; automatic control program is carried out its repetition machine open/close test, reset test and the test of power management sleep-awake and replace; and can adjust testing time and test interval according to need; and when test is finished; automatically note down and show test results; and can consequently not have test result because of the system-down in the test again.
Summary of the invention
For above and other objects of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:
Fig. 1 is a kind of computer main frame panel on-off testing system synoptic diagram that shows the preferred embodiment according to the present invention;
Fig. 2 is the machine open/close test procedure process flow diagram that shows the preferred embodiment according to the present invention;
Fig. 3 A is the replacement test procedure first part process flow diagram that shows the preferred embodiment according to the present invention;
Fig. 3 B is the replacement test procedure second part process flow diagram that shows the preferred embodiment according to the present invention;
Fig. 4 A is the power management sleep-awake test procedure first part process flow diagram that shows the preferred embodiment according to the present invention;
Fig. 4 B is the power management sleep-awake test procedure second part process flow diagram that shows the preferred embodiment according to the present invention; And
Fig. 5 is the test procedure control module calcspar that shows the preferred embodiment according to the present invention.
The explanation of symbol among the figure:
100 computer main frame panel on-off test devices
110 computer main frame panels
120 order interpretation units
130 test procedure control modules
140 test result display units
150 test procedures are selected setup unit
160 write data display unit
S200～S490 program step
510 single-chip microprocessor
520 latch units
530?EEPROM
Embodiment
As shown in Figure 1, it is a kind of computer main frame panel on-off testing system synoptic diagram according to a preferred embodiment of the present invention, by among the figure as can be known, this system comprises computer main frame panel to be tested 110 and computer main frame panel on-off test device 100.Wherein, computer main frame panel 110 comprises it for example being standard interface, power source ON/OFF switch, replacement (Reset) switch, CPU (central processing unit), ACPI (the Advanced Configuration ﹠amp of PCI (Peripheral Component Interconnect is called for short PCI) interface; Power Interface) electric power controller and for example be the basic input/output (Basic Input/Output System is called for short BIOS) of Award.Computer main frame panel on-off test device 100 then comprises order interpretation unit 120 and test procedure control module 130 at least.As then can also comprising test result display unit 140 for showing test results, for providing the user to select the elasticity of different test procedures, then can also comprise test procedure selection setup unit 150, and be the elasticity of generator error detection, then can also comprise writing data display unit 160.
Refer again to Fig. 1, wherein, order interpretation unit 120 couples computer main frame panel 110 via the PCI interface, because the computer main frame panel 110 of present embodiment is when start or reopening machine execution Award BIOS, can be the data that write that a non-FF is exported in the error detection particular port address of 80H via input/output end port (I/O Port) address, so this writes data to order interpretation unit 120 to receive also decipher with this, and this is write data latching preserves, normally whether use for judgement computer main frame panel 110 start situations, but present embodiment is to finish with program logic device GAL16V8.Test procedure control module 130 couples order interpretation unit 120 and reaches power switch and the reset switch that connects computer main frame panel 110 via connecting line in addition, in order to foundation one presumptive test program, send in regular turn for example is electric power on/off (ON/OFF) order or the test control command of (Reset) order of resetting, switching on and shutting down and replacement with control computer motherboard 110, reading order interpretation unit 120 breech locks writes data again, to judge whether computer main frame panel is normal, and the record for example be the test result of the testing time and the number of times that makes a mistake etc., present embodiment is then with single-chip microprocessor 8031, latch unit 74LS373 and EEPROM 2864 realize.Test result display unit 140 then couples test procedure control module 130, in order to show this test result.
As shown in Figure 5, after computer power supply was opened, the single-chip microprocessor 510 in the test procedure control module 130 promptly began effect, will give EEPROM520 to take out this instruction by execution instruction address.Wherein this execution instruction address comprises high address and low order address, wherein EEPROM520 is directly given by single-chip microprocessor 510 in the high address, low order address then has 8, is to export latch unit 530 to and latch in wherein by data/address bus, transfers to EEPROM520 again.When EEPROM520 be provided for comprise high address and both full address of bit address after, then the data in this address are offered single-chip microprocessor 510 by data (instruction)/address bus and carry out, to carry out the control of various test procedures.
In addition, test procedure selects setup unit 150 to couple test procedure control module 130, in order to set the above-mentioned presumptive test program of selecting.These presumptive test programs comprise the machine open/close test procedure of Fig. 2, the replacement test procedure of Fig. 3 and the power management sleep-awake test procedure of Fig. 4, and its program code by 8031 single-chip microprocessor is formed.Start wherein to shutdown, shutdown to start and time interval of resetting etc. be and can set, and the cycle index of test also can be set at specific times, as 10 times, 100 times or 200 inferior, or is set at and continues and do not limit number of times.Write data display unit 160 then in order to the data that write of display command interpretation unit 120 breech locks, so that the error detection reference to be provided.
Please refer to Fig. 2, it is the machine open/close test procedure process flow diagram of the preferred embodiment according to the present invention, show among the figure, program is by Initiation and read setting value S200 and begin, this step is except that the initial value of setting this computer main frame panel on-off test device 100, and the selection setting value of read test procedure Selection setup unit 150, for down-stream with reference to use, then in order to confirm the initial situation of tested computer main frame panel 110, avoiding some motherboard to have preparation (Standby) power supply one opens and promptly starts shooting and cause the situation of unexpected start, so no matter power switch is the state that is in connection (ON) or cuts off (OFF), all cut off mainboard power supply S205 by issuing orders with the power switch that continues more than 4 seconds in advance, just begin test then.
Test procedure at the beginning, at first connect order and open mainboard power supply S210 with power switch, follow the data that write of reading order interpretation unit 120 breech locks, and judge whether its value is that FF is shown in the S215 step, this moment is because of in the start BIOS execution, so if the value that reads is FF, represent not successful execution of BIOS, program enters S265 errors number is added 1, cut off mainboard power supply in the mode of delaying time 4 seconds then, whether enter next loop test with decision, otherwise non-as if the value that reads is FF, then enter S220 and delay time 30 seconds to allow BIOS finish execution if having time, certainly, those skilled in the art are when knowing that these times for the treatment of need to revise change with motherboard, at this moment, enter S225 again and read the value that writes data, if still be non-FF, it is complete then to represent the BIOS of motherboard to fail, and tests as then can enter shutdown for FF.
Before entering the shutdown test, judge at first whether the shutdown mode of selecting wants delay operation shown in the S230 step, then enter S240 in this way and cut off mainboard power supply in the mode of delaying time 4 seconds, otherwise cut off mainboard power supply S235 in instantaneous mode, read then and write data and judge whether its value is that FF is shown in the S245 step.This moment, the circuit design because of order interpretation unit 120 was when motherboard shuts down, its value is non-FF, so if read the FF value, the representative shutdown that fails can enter the S265 step errors number is added 1 and cut off behind the mainboard power supply to the S260 step in the mode of delaying time 4 seconds, otherwise enter the S250 step, to judge whether the test interval of selecting will add long delay, in the time will adding long delay, enter the S255 step and added long delay in addition 15 seconds, enter S260 then.Whether the testing time of judge setting at S260 arrives, as otherwise get back to S210 and continue next loop test, finish test as arriving then representative, and show and comprise testing time and the test result S270 of the number of times that makes a mistake.
Please refer to Fig. 3, it is the replacement test procedure process flow diagram of the preferred embodiment according to the present invention, show among the figure, program is by Initiation and read setting value S300 and begin, this step is except that the initial value of setting this computer main frame panel on-off test device 100, and the selection setting value of read test procedure Selection setup unit 150, for down-stream with reference to use, then in order to confirm the initial situation of tested computer main frame panel 110, a dozen are opened and promptly start shooting and cause the situation of unexpected start to avoid some motherboard to have pre-stand-by power source, so no matter power switch is the state that is in connection (ON) or cuts off (OFF), all cut off mainboard power supply S305 by issuing orders with the power switch that continues more than 4 seconds in advance, just begin test then.
Test procedure at the beginning, at first connect order and open mainboard power supply S310 with power switch, follow the data that write of reading order interpretation unit 120 breech locks, and judge whether its value is that FF is shown in the S315 step, this moment is because of in the start BIOS execution, so if the value that reads is FF, represent the start that fails, can't proceed the test of resetting, the relative program so the program A of entering starts shooting again, otherwise enter BIOS was finished in the S320 time-delay in 30 seconds with wait execution, at this moment, enter S325 again and read the value that writes data, if be non-FF still, then represent the BIOS of motherboard to fail and finish execution, program enters S360 errors number is added 1, cut off mainboard power supply in the mode of delaying time 4 seconds then, and time-delay a period of time S365, return S310 and reenter test loop, if FF then enters S330, to judge whether testing time arrives, as otherwise show present test result S345, and send the order of resetting, with the replacement motherboard shown in the S350 step, get back to the S315 step then and continue this loop test, arrive as testing time when the S330 step, then the representative test is finished, at this moment, enter S335 with the cut-out mainboard power supply, and show its final testing result S340.
The correlation step system of starting shooting again of program A is included in the S380 step errors number of will starting shooting and adds 1 and cut off mainboard power supply in the mode of delaying time 4 seconds, whether reach to S382 step look at the to reset set point number of test then, then show test results and finish S390 to the S384 step in this way in entering thereafter, otherwise will get back to S310 and reopen power supply, until enter the S320 test of resetting by S315 just now till starting shooting successfully with start.Because the purpose of this test procedure is in the test of resetting, so also can replace step to stop to test in program A, this is start and unsuccessful therefore the time, and real in some sense can't the replacement tested event.
Please refer to Fig. 4, it is power management sleep-awake (suspend/wake up) the test procedure process flow diagram of the preferred embodiment according to the present invention.ACPI S3 state is a kind of battery saving mode of power management, i.e. STR (Suspend To Ram), and it is to utilize hardware to realize with cooperating of operating system.When computing machine is idle, consider from the angle of energy savings, can enter the S3 power down mode according to the setting of operating system, promptly the content of carrying out at present is kept in the internal memory, this moment, power supply was only powered to internal memory, other partly then keeps preparation (standby) power supply, so promptly enters the S3 sleep state.When computing machine is waken up, can be immediately from internal memory sense data enter normal condition.During test, can in operating system, set and when pressing power switch, enter the S3 state, wake computing machine when pressing once more up; Therefore, in test process, send and press the power switch order and cooperate corresponding time-delay, can reach this purpose.Show among the figure, program is by Initiation and read setting value S400 and begin, this step is except that the initial value of setting this computer main frame panel on-off test device 100, and the selection setting value of read test procedure Selection setup unit 150, for down-stream with reference to use, then in order to confirm the initial situation of tested computer main frame panel 110, a dozen are opened and promptly start shooting and cause the situation of unexpected start to avoid some motherboard to have pre-stand-by power source, so no matter power switch is the state that is in connection (ON) or cuts off (OFF), all cut off mainboard power supply S405 by issuing orders with the power switch that continues more than 4 seconds in advance, just begin test then.
Test procedure at the beginning, at first connect order and open mainboard power supply S410 with power switch, follow the data that write of reading order interpretation unit 120 breech locks, and judge whether its value is that FF is shown in the S415 step, this moment is because of in the start BIOS execution, so if the value that reads is FF, represent the start that fails, can't proceed the test of S3 sleep-awake, so program enters the program B relative program of starting shooting again, otherwise enter S420 time-delay 120 seconds and finish the execution of BIOS and operating system, and the time of test man's activation S3 sleep-awake function is provided, at this moment with wait, enter S425 again and read the value that writes data, if still be non-FF, then to represent the BIOS of motherboard to fail and finish execution, program enters S470 errors number is added 1, cut off mainboard power supply in the mode of delaying time 4 seconds then, and time-delay a period of time S475, return S410 and reenter test loop, otherwise formally enter the test of S3 sleep-awake.
After entering the test of S3 sleep-awake, at first send power switch and connect order, make it enter sleep state shown in the S430 step, read then and write data and judge whether its value is that FF is shown in the S435 step, this moment, the circuit design because of order interpretation unit 120 was when motherboard loses power supply, its value is non-FF, so if read the FF value, representative fails and enters sleep state, need to S470 step record errors number 1 time, otherwise enter the S440 step, with arbitrary delay time of delaying time 30 seconds or desire is waited for, and then send power switch and connect order, wake it up S445, then enter the S450 step, read again and write data and judge whether its value is FF, be by in sleep wake because of motherboard this moment, so its value should be FF and is only normally, as undesired also should be to S470 misregistration number of times 1 time, whether normal value FF then enters the testing time that S455 judge to set and arrives in this way, as otherwise show present test result S465, and get back to S430 and continue next loop test, then test has been finished in representative in this way, so demonstration comprises testing time and the test result S460 of the number of times that makes a mistake.
The correlation step system of starting shooting again of program B is included in the S480 step errors number of will starting shooting and adds 1 and cut off mainboard power supply in the mode of delaying time 4 seconds, look to the S482 step whether the set point number of S3 sleep-awake test reaches then, then show test results and finish S490 to the S484 step in this way in entering thereafter, otherwise will get back to S410 and reopen power supply, carry out the test of S3 sleep-awake until enter S420 by S415 just now till starting shooting successfully with start.Because the purpose of this test procedure is to carry out the test of S3 sleep-awake, so also can replace step to stop to test in program B, this is start and unsuccessful therefore the time, can't carry out the event of S3 sleep-awake test in fact in some sense.Though power management sleep-awake test of the present invention is that act ACPI S3 power down mode is an example, the present invention can also test at other different battery saving modes and state.
In above-mentioned explanation, can conclude a kind of on-off test method for motherboard of computer, comprise the following steps: at first foundation one presumptive test program, send a test control command in regular turn, with control ON/OFF and replacement computer main frame panel; Again as calculated a standard interface decipher one particular port address of machine host plate write data, whether normal to judge computer main frame panel, and record shows its test result.
Test control command wherein comprises the electric power on/off order and the order of resetting, and its presumptive test program comprises the machine open/close test, reset test and the test of power management sleep-awake.And the standard interface that computer main frame panel provides is a pci interface, and use input/output end port address 80H is the particular port address of its error detection.In addition, the displayable test result of this method of testing comprises testing time and the number of times that makes a mistake, and the time interval of each test control command wherein is for setting.
The old friend, use a kind of computer main frame panel on-off test device provided by the invention, method and system thereof, then replace complicated manually-operated with automatic control program easily, carry out its repetition machine open/close test to finish, reset and test and the test of power management sleep-awake, and elasticity is adjusted testing time and test interval according to need, and when test is finished, and notes down automatically and shows test results, promote its tested performance widely, and can guarantee its test accuracy.
Though the present invention discloses as above with a preferred embodiment; right its is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, thus protection scope of the present invention when with claims and in conjunction with instructions and accompanying drawing the person of being defined be as the criterion.
Claims (10)
1. an on-off test method for motherboard of computer is characterized in that, comprises the following steps:
According to a presumptive test program, send a test control command in regular turn, with control ON/OFF and this computer main frame panel of resetting; And
The data that write through a standard interface decipher one particular port address of this computer main frame panel, whether normal to judge this computer main frame panel, and write down its test result.
2. on-off test method for motherboard of computer as claimed in claim 1 is characterized in that: comprise that also one shows the step of this test result.
3. on-off test method for motherboard of computer as claimed in claim 1 is characterized in that: this test control command comprises one of following at least: the electric power on/off order and the order of resetting.
4. on-off test method for motherboard of computer as claimed in claim 1 is characterized in that: this presumptive test program comprises one of following at least: the sleep-awake test of machine open/close test, reset test and power management.
5. on-off test method for motherboard of computer as claimed in claim 1 is characterized in that: this standard interface is a pci interface.
6. on-off test method for motherboard of computer as claimed in claim 5 is characterized in that: this particular port address is input/output end port address 80H.
7. on-off test method for motherboard of computer as claimed in claim 1 is characterized in that: this test result comprises the result of the number of times that makes a mistake.
8. on-off test method for motherboard of computer as claimed in claim 1 is characterized in that: the time interval of each this test control command is for setting.
9. on-off test method for motherboard of computer as claimed in claim 1, it is characterized in that: this computing machine comprises a computer main frame panel and a computer main frame panel on-off test device, be inserted on this computer main frame panel, and connecting line may command ON/OFF arranged and this computer main frame panel of resetting.
10. on-off test method for motherboard of computer as claimed in claim 1 is characterized in that: this presumptive test program can be set at the cycle index of same fc-specific test FC.
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| CN 02122499 CN1391164A (en) | 2002-06-04 | 2002-06-04 | On-off test method for motherboard of computer |
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| CN 02122499 CN1391164A (en) | 2002-06-04 | 2002-06-04 | On-off test method for motherboard of computer |
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| CN103914361B (en) * | 2013-01-09 | 2017-07-28 | 技嘉科技股份有限公司 | Detection jig and detection method of computer device |
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| CN106154072A (en) * | 2015-04-07 | 2016-11-23 | 上海炬力集成电路设计有限公司 | A kind of Testing System for Electronic Equipment and method |
| CN105302726A (en) * | 2015-11-13 | 2016-02-03 | 浪潮电子信息产业股份有限公司 | Test method and device |
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