CN1389970A - Power-factor correcting method for low ready power - Google Patents

Abstract

The invention discloses the controlling scheme for the preceding stage of correcting the switch type power factor. At the condition of stand by or light loading, the scheme possesses the character with very low power loss. Thus the input power is also very low, which is suitable for recent electronic equipment needed to reduce the influence on environment. At the condition of stand by or light loading, the most of the power loss is the power loss of the power supply in switch mode. Since the power loss is direct propertional to the switch frequency of the switch part, thus reducing the working frequency at the light loading also reduces the relevant power loss. The invention uses the special switch timing control to reach the purpose.

Description

The power-factor correcting method and the circuit arrangement thereof that are used for low standby power

The present invention relates to a kind of power-factor correcting method and circuit thereof.

In existing known technology, power factor correcting (PFC) is to realize by a threshold inductance current mode boost converter (boost converter) that ON time is fixed up in whole power cycle.It is satisfied to work under this scheme counterweight loading condition, but just not ideal enough for working under the light-load conditions.This is that ON time must be very short, and work in the threshold inductance current-mode for keeping because when underload, and switching frequency must be very fast, so the power loss of switching loss and holding state is all big.

In view of above-mentioned, order of the present invention ground is to propose a kind of controlling schemes that is used for switching regulator power factor correction prime.Under standby or underloading condition, this scheme has the low-down characteristic of power loss, thereby input power is also very low; This is highly suitable for those and wishes the modern electronics of minimizing to environmental impact.

Purpose of the present invention is achieved through the following technical solutions:

A kind of power factor correcting method that is used for low standby power, it adopts the structure of the preposition boost power converter of switching mode, in the half period, the ON time and the deadline of switch are constant at input voltage for this boost power converter, and work in discontinuous inductive current pattern.

The ON time of described switch periods has a lower limit, under the underloading condition, its output voltage can surpass a predetermined voltage stabilizing level, and electric circuit inspection is during to this situation, and the follow-up switch motion of supspending converter is till output voltage is returned to this predetermined voltage stabilizing level.

A kind of circuit arrangement that is used for power factor correction, it comprises inductor L1, switching tube Q1, diode D1, capacitor C1-C3, logic lock U5, comparator U1-U2, inverter U3, buffer U4, current source I1-I2, error amplifier U6, divider resistance R1-R2, wherein:

Current source I1, I2 provide charging current to capacitor C3, C2 respectively;

Inductor L1, switching tube Q1, diode D1 and capacitor C1 form a basic booster converter, and it is the basis that constitutes power factor correction work, and the work of switching tube Q1 is by the output voltage control of logic lock U5;

The output end vo ut of divider resistance R1-R2 series connection back connection circuit, its dividing point connects the input of error amplifier U6;

Error amplifier U6 is output as the integration of the difference of the sampled signal of Vout and reference voltage VR, and it connects the input of comparator U2;

Another input termination capacitor C 2 of comparator U2, its output shutoff/inhibit signal is to logic lock U5 and inverter U3, and the output of inverter U3 connects capacitor C 3, and capacitor C 3 is discharged by inverter U3;

The input termination threshold voltage of comparator U1, another input termination capacitor C 3, its output is opened signal to logic lock U5 and buffer U4, and the output of buffer U4 connects capacitor C 2, and capacitor C 2 is discharged by buffer U4;

Logic lock U5 has a shutoff/inhibit signal end and the signal end of opening by the control of comparator U1 output by the control of comparator U2 output, the output of logic lock U5 connects the input of switching tube Q1, Q1 ends when shutoff/inhibit signal is established, and keeps cut-off state; Q1 conducting when shutoff/inhibit signal is disengaged and opens signal and is established.

Under standby or underloading condition, the power loss of the power supply unit of switching mode, major part are switching losses.Because switching loss is directly proportional with the switching frequency of switching device, so the operating frequency during the minimizing underloading, also power loss that promptly can corresponding minimizing holding state.The present invention utilizes unique switch timing controlled to reach this purpose.

Advantage of the present invention:

1. simplicity of design;

2. effective power factor correcting under the heavy load condition;

3. during underloading, switching frequency is very low, has low-down power loss, thereby the standby input power is also very low.

Below in conjunction with drawings and Examples the present invention is elaborated.

Fig. 1 is the PFC schematic diagram of low standby power;

Fig. 2 is the operation waveform under the heavy duty;

Fig. 3 is the operation waveform under the underload;

Fig. 4 is the operation waveform under the standby load.

Please refer to the PFC schematic diagram of the low standby power of Fig. 1.Each symbol implication is as follows among the figure:

Vin: the circuit input voltage after the rectification, Vout: circuit output voltage, VR: reference voltage is used for control output voltage Vout, Vth: the inner threshold voltage that uses.

Circuit comprises inductor L1, switching tube Q1, diode D1, capacitor C1-C3, logic lock U5, comparator U1-U2, inverter U3, buffer U4, current source I1-I2, error amplifier U6, divider resistance R1-R2, wherein:

L1, Q1, D1 and C1 form a basic booster converter, and it is the basis that constitutes PFC work.The work of switching tube Q1 is by controlling with the output voltage of door U5.

U5 has two signal input parts, and one is the shutoff/inhibit signal end by the control of U2 output, and another is the signal end of opening by the control of U1 output.Q1 ends when shutoff/inhibit signal is established, and keeps cut-off state; Has only just conducting of Q1 when shutoff/inhibit signal is disengaged and opens signal and is established.

Shutoff/inhibit signal is driven by U2.When the last zigzag ramp voltage that produces of timing capacitor C2 was higher than error amplifier U6 output end voltage, U2 activated shutoff/inhibit signal.

U6 is an error amplifier, and it is output as the integration of the difference of the sampled signal of Vout and reference voltage VR.U6 is built-in with the timing component as the common dynamic compensation.Attention: if output voltage is enough high, the output voltage of U6 can be lower than the resetting voltage of C2, and shutoff/inhibit signal will be established to establish illegal state this moment.

I2 charges to C2, and the C2 both end voltage rose with the charging interval, and it has determined the ON time of Q1, and C2 is discharged by U4.

U4 is the buffer of a collector electrode (or letting out the utmost point) open circuit, and it is to open signal as input.Be undone whenever opening signal, the charging voltage at C2 two ends will reset to electronegative potential.Attention: the resetting voltage at C2 two ends can not be lower than the minimum output voltage of U6, otherwise circuit will can not enter the low-power illegal state.When opening signal and set up, the voltage on the C2 can be with linear rising of charging interval.

U1 drives and opens signal.When the wavy charging voltage of sawtooth rises to and is higher than threshold voltage Vth on C3, open signal and promptly be established.

C3 produces a zigzag charging voltage via current source I1 charging, and it has determined the deadline of Q1.The voltage of C3 can be released by U3.

U3 is the inverter of a collector electrode (or letting out the utmost point) open circuit, it with shutoff/inhibit signal as input.Whenever shutoff/inhibit signal is established, the voltage on the C3 promptly is reset to low level.And when shutoff/inhibit signal was removed, the voltage on the C3 can be with linear rising of charging interval.

R1 and R2 are divider resistances, and effect is that the high-voltage of Vout end is reduced to a suitable sample level, to meet the requirement of normal controller spare.

The work wave of following this circuit of surface analysis:

Normal load condition-the please refer to work wave under the heavy duty shown in Figure 2.Under general loading condition, fixed by timing component I1, C3, U1 and U3 the deadline of switch periods.And ON time promptly changes with the output voltage height of U6 (error amplifier).Yet the same with common PFC scheme, the dynamic response of U6 is through suitable compensation so that its output voltage keeps stable in AC power in the half period; The ON time of switch periods also thereby settle out.Since input voltage in the half period ON time and deadline all be constant, booster converter runs in the mode of fixed frequency and fixed duty cycle in essence.In theory, the PFC function that works in this mode is unsatisfactory, yet but very good of its practical manifestation can meet any practical requirement.We will have further instruction after a while.

Work wave under standby load condition-reference underload shown in Figure 3.When bearing power reduced, the output voltage of U6 reduced, and ON time also reduces.Under a fixed load, the output voltage of U6 can be reduced to almost near the reset level of C2, and at this moment, ON time is almost nil.But because there are transmission delay in U1, U4, U2 and U3, ON time can't fade to zero from a certain minimum value.That is to say,, just can not be cancelled at once because the time-delay of assembly as long as whenever open signal is established; Open signal and must continue a short time, the ON time of a Q1 thereby lower limit is arranged.

With reference to the operation waveform under the standby load shown in Figure 4.When bearing power further reduces, circuit promptly enters holding state.At holding state, load is very light, and the energy that single minimum ON time is transmitted is enough to make output voltage V out to keep one section greater than the deadline by I1, C3, U1 and U3 determined.In this case, Vout will rise gradually, suitably get involved because of disable period up to deadline to prolong.

Along with Vout rises, the output voltage of U6 descends gradually, and when the output voltage of U6 was lower than the reset level of C2, shutoff/inhibit signal promptly was established to activate disable period.The duration of disable period is identical with the time that the output voltage of U6 is lower than U4.When Vout descends, the output voltage of U6 will go up gradually, and shutoff/inhibit signal is cancelled, and enter next short turn-on cycle.Because the intervention of disable period, under holding state, the switch operating frequency of converter is low-down.

Next power factor correcting performance of the present invention is described.Traditionally, the power factor correcting function is to realize by the booster converter that is operated in the threshold inductance current-mode.Generally should be and have only this mode of operation that gratifying power factor correcting performance just can be provided.Yet, our booster converter is the discontinuous inductive current pattern that is operated in fixed duty cycle, although the power factor correcting function of this mode of operation is also imperfect in theory, the service behaviour that we can derive this pattern is enough to deal with any actual needs.The derivation of whole formula is omitted, and only lists the result of derivation below.

Based on following condition,

D＜1-K

The relation of power factor pf and K can be expressed as:

pf(K)＝-2/(K*SQRT(pi))* $1+\frac{\mathrm{pi}}{2*K}-\frac{\mathrm{pi}-\mathrm{ACOS}\left(K\right)}{K*\mathrm{SQRT}(1-\mathrm{K\Λ}2)}$ $\mathrm{SQRT}(\frac{1}{k*(1-\mathrm{K\Λ}2)}+\frac{\mathrm{pi}}{2*\mathrm{K\Λ}2}-\frac{(1-2*\mathrm{K\Λ}2)*(\mathrm{pi}-\mathrm{ACOS}\left(K\right))}{\mathrm{K\Λ}2*(1-\mathrm{K\Λ}2)\mathrm{\Λ}(3/2)})$

In the formula:

D=t_On/t_s; Duty ratio

K=V_m/V_out; It is a voltage ratio

The ON time of t_on:PFC switch

The switch periods of t_s:PFC switch

V_m: the ambassador of sinusoidal sloping input voltage of half period.

Numerical example

1. power factor is to the K value

K pf(K)

0.10 1.00

0.50 0.99

0.70 0.98

0.80 0.95

0.90 0.90

0.92 0.88

0.94 0.85

0.96 0.81

0.98 0.73

0.99 0.65

2. power factor is to the input and output magnitude of voltage

V_Out V_in K pf

(V) (V_rms)?(V_m)

380 200 282.8 0.74 0.97

380 230 325.3 0.86 0.93

380 264 373.4 0.98 0.72

400 200 282.8 0.71 0.97

400 230 325.3 0.81 0.95

400 264 373.4 0.93 0.86

420 200 282.8 0.67 0.98

420 230 325.3 0.77 0.96

420 264 373.4 0.89 0.91

As seen the power factor of this law is fairly good; In most cases greater than 0.9.Even when the K value is in close proximity to 1 (0.98), power factor still is higher than 0.7.

Claims (3)

1. power factor correcting method that is used for low standby power, it is characterized in that: the structure that adopts the preposition boost power converter of switching mode, this boost power converter is at input voltage in the half period, the ON time and the deadline of switch are constant, and work in discontinuous inductive current pattern.

2. the method for claim 1, the ON time that it is characterized in that described switch periods has a lower limit, under the underloading condition, its output voltage can surpass a predetermined voltage stabilizing level, electric circuit inspection is during to this situation, and the follow-up switch motion of supspending converter is till output voltage is returned to this predetermined voltage stabilizing level.

3. circuit arrangement that is used for power factor correction, it is characterized in that it comprises inductor L1, switching tube Q1, diode D1, capacitor C1-C3, logic lock U5, comparator U1-U2, inverter U3, buffer U4, current source I1-I2, error amplifier U6, divider resistance R1-R2, wherein:

Current source I1, I2 provide charging current to capacitor C3, C2 respectively;

Inductor L1, switching tube Q1, diode D1 and capacitor C1 form a basic booster converter, and it is the basis that constitutes power factor correction work, and the work of switching tube Q1 is by the output voltage control of logic lock U5;

The output end vo ut of divider resistance R1-R2 series connection back connection circuit, its dividing point connects the input of error amplifier U6;

Error amplifier U6 is output as the integration of the difference of the sampled signal of Vout and reference voltage VR, and it connects the input of comparator U2;

Another input termination capacitor C 2 of comparator U2, its output shutoff/inhibit signal is to logic lock U5 and inverter U3, and the output of inverter U3 connects capacitor C 3, and capacitor C 3 is discharged by inverter U3;

The input termination threshold voltage of comparator U1, another input termination capacitor C 3, its output is opened signal to logic lock U5 and buffer U4, and the output of buffer U4 connects capacitor C 2, and capacitor C 2 is discharged by buffer U4;

Logic lock U5 has a shutoff/inhibit signal end and the signal end of opening by the control of comparator U1 output by the control of comparator U2 output, the output of logic lock U5 connects the input of switching tube Q1, Q1 ends when shutoff/inhibit signal is established, and keeps cut-off state; Q1 conducting when shutoff/inhibit signal is disengaged and opens signal and is established.

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