CN1387321A - Digital phase-locked loop device and signal generating method - Google Patents
Digital phase-locked loop device and signal generating method Download PDFInfo
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- CN1387321A CN1387321A CN 02123113 CN02123113A CN1387321A CN 1387321 A CN1387321 A CN 1387321A CN 02123113 CN02123113 CN 02123113 CN 02123113 A CN02123113 A CN 02123113A CN 1387321 A CN1387321 A CN 1387321A
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Abstract
The present invention relates to a device of digital phase lock loop and a method for generating signal. The device includes the interpolator, the time sequence error detector, the loop filter and the locking controller. The method for generating the signal includes following steps. A value of the time sequence error of the synchronous sampled signal is detected by using the time sequence error detector. Based on the said value of the time sequence error, the interpolator outputs a interpolated value of the time sequence so as to provide the reference for the device of digital phase lock loop user in processing the signal of the asynchronous sampled value. When quality of the time sequence of the synchronus sampled signal value detected by the locking controller enters to bad condition, the loop filter outputs the fixed backup value of the interpolated time sequence as the reference to the device of digital phase lock loop.
Description
Technical field
The present invention relates to a kind of digital phase-locked loop device and signal generating method, refer to be applied to the digital phase-locked loop device and the signal generating method of data fetch device especially.
Background technology
Fig. 1 (a) is depicted as the part functional-block diagram of a given data reading device (for example disc accessing).((Analog-to-Digital Convertor ADC) forms an asynchronous sampling value signal (Asynchronous Samples) after 11 the processing via an analog-digital converter for Pick-Up Head, an analog voltage signal of PUH) being exported by read head.This asynchronous sampling value signal is again after the adjustment by the digital phase-locked loop device (All-digital PLL) 12 that is made of an interpolater (Interpolater) 121, a sequential error detector (Timing ErrorDetector) 122 and one loop filter 123 (timing system), form a synchronous sampling value signal (Synchronous Samples) output, further handle in order to follow-up functional circuit to be provided.
Wherein, interpolater 121 receives an asynchronous sampling value signal and handles and export a synchronous sampling value signal.And time detector 122 detects this synchronized sampling value signal of gained and the sequential error amount (shown in Fig. 1 (b)) between an expection synchronized sampling signal (expected synchronous samples).As for loop filter 123 is to export an interpolation sequential value to this interpolater 121 according to the variation of this time value, with provide this interpolater 121 with reference to and adjust, and then obtain better synchronized sampling value signal.
Yet, this analog voltage signal of exporting when read head because as unexpected factor such as the surperficial scratch of discs and when causing jumbo noise jamming, with the unsettled situation of asynchronous sampling value signal (Asynchronous Samples) timing sequence generating extreme that makes that analog-digital converter 11 is produced, the feasible digital phase-locked loop device of being finished with above-mentioned known technology (All-digital PLL) 12, must spend one section quite long recovery time and can recover normally, have a strong impact on disc accessing in the data read ability of this section period.
Summary of the invention
In view of this, the technical problem to be solved in the present invention is when there is jumbo noise jamming in analog voltage signal, effectively shortens recovery time long in the known technology and can read out more correct data in the scratch zone, thereby promote the reading capability of CD-ROM drive.
In order to achieve the above object, the invention provides a kind of PLL device, comprise: an interpolater, receive that an input signal is handled and and an output signal; One sequential error detector detects a sequential error amount of this output signal; One loop filter is exported an interpolation sequential value to this interpolater according to this time value; And a lockout controller, control this interpolation sequential value that this loop filter is exported according to the sequential quality of this output signal.
In the such scheme, this lockout controller in the digital phase-locked loop device of the present invention includes: a lock detector, send one according to the sequential quality of this output and read a signal or a backup signal again, when the sequential quality enters defective mode, send this and read signal again, and when the sequential quality enters a kilter, send this backup signal; One register is electrically connected on the output of this loop filter, in order to store this interpolation sequential backup value; An and multiplexer group, be electrically connected between this loop filter and this register, determine whether this interpolation sequential value at that time is stored in this register in response to this backup signal, in addition, in response to reading signal again, this determine whether to make this loop filter utilization to be stored in this interpolation sequential backup value in this register.
In the such scheme, this lock detector includes in the digital phase-locked loop device of the present invention: a sequential attribute test device, be pursuant to the ratio and the comparative result of a threshold value of absolute value of two adjacent output signals of zero crossover point both sides, and then send number signals or several signal on one once; On one/following counter, in response to number signal on this maybe this time number signal triggering and go up number or following the number moved; And a comparator bank, be electrically connected on this/following counter, in response on this/count value and a backup threshold value and of following counter read the comparative result of threshold value again, and then sends this backup signal or this reads signal again.
In the such scheme, this input signal is exported by an analog-digital converter in the digital phase-locked loop device of the present invention.
In the such scheme, this analog-digital converter is an analog voltage signal is taken a sample and to obtain this input signal in the digital phase-locked loop device of the present invention.
In the such scheme, this input signal is an asynchronous sampling value signal in the digital phase-locked loop device of the present invention, and this output signal is a synchronous sampling value signal.
In order to achieve the above object, the present invention also provides a kind of signal generating method, and this method comprises the following step: a sequential error amount that detects an input signal; Export an interpolation sequential value according to this time value, with reference when handling an output signal; When the sequential quality of this input signal during, carry out the frequency backup at kilter; And when the sequential quality of this input signal enters a defective mode,, this input signal is carried out interpolation to obtain an output signal according to the frequency that is backed up.
In the such scheme, signal generating method of the present invention is applicable to a digital phase-locked loop device, wherein this digital phase-locked loop device is to send one according to the sequential quality of this output signal to read a signal or a backup signal again, wherein when the sequential quality enters defective mode, send this and read signal again, and when the sequential quality enters a kilter, send this backup signal.
In the such scheme, this digital phase-locked loop device is to determine whether will store at that time this interpolation sequential value in response to this backup signal to upgrade this interpolation sequential backup value in the signal generating method of the present invention, in addition, in response to reading signal again, this determines whether to make this interpolation sequential backup value of this digital phase-locked loop device fixed reference.
In the such scheme, this digital phase-locked loop device is to be pursuant to the ratio of absolute value of two adjacent output signals of zero crossover point both sides and the comparative result of a threshold value in the signal generating method of the present invention, and then send on one the number signals or count signal once and produce a count value, and read the comparative result of threshold value again, and then send this backup signal or this reads signal again in response to this count value and a backup threshold value and.
In the such scheme, this input signal is to take a sample an analog voltage signal resultant by an analog-digital converter in the signal generating method of the present invention.
In the such scheme, this input signal is an asynchronous sampling value signal in the signal generating method of the present invention, and this output signal is a synchronous sampling value signal.
As from the foregoing, this analog voltage signal V that exports when read head because as unexpected factor such as the surperficial scratch of discs and when causing jumbo noise jamming, this interpolation sequential backup value that digital phase-locked loop device disclosed in this invention (All-digital PLL) can read when in good condition again apace and be backed up is also used, effectively shorten long recovery time in any means known, and then enhancement is used the disc accessing of the technology of the present invention in the data read ability of this section period, thoroughly improve above-mentioned known disappearance, successfully reach development main purpose of the present invention.
Description of drawings
Fig. 1 (a) is the functional-block diagram of digital phase locked loop in the known optical disc reading device.
Fig. 1 (b) is the sequential error amount schematic diagram between an actual synchronization sampling value signal and an expection synchronized sampling signal.
Fig. 2 is the functional-block diagram of the present invention for the preferred embodiment that is applied to the digital phase-locked loop device (All-digital PLL) in the disc accessing.
Fig. 3 is the functional-block diagram of the preferred embodiment of loop filter of the present invention and lockout controller.
Fig. 4 is the functional-block diagram of a preferred embodiment of lock detector of the present invention.
Fig. 5 (a) and Fig. 5 (b) are the waveform schematic diagrames of synchronized sampling value signal among the present invention.
Fig. 6 (a) and Fig. 6 (b) are that the present invention is for being applied to the digital phase-locked loop device (All-digital PLL) in the disc accessing and wherein improveing another preferred embodiment functional-block diagram that the back loop filter develops out.
Embodiment
The present invention of being shown in Figure 2 is applied to the functional-block diagram of the preferred embodiment of the digital phase-locked loop device (All-digital PLL) in the disc accessing.Digital phase-locked loop device consists predominantly of an interpolater (interpolator) 21, a sequential error detector (timing errordetector) 22, one loop filter (loop filter) 23 and one lockout controller (lockdetector) 24.This interpolater 21 receives an asynchronous sampling value signal and handles and export a synchronous sampling value signal.Time detector 22 detects the sequential error amount between this a synchronized sampling value signal and an expection synchronized sampling signal (expected synchronous samples).Loop filter 23 is exported an interpolation sequential value to this interpolater 21 according to the variation of this time value, so that this interpolater 21 references to be provided.
And the present invention utilizes lockout controller 24 to solve the disappearance of known technology.This lockout controller 24 is electrically connected on (or saying that it is parallel to time detector 22) between this interpolater 21 and this loop filter 23.Lockout controller 24 is characterised in that the sequential quality of this synchronized sampling value signal of being exported according to interpolater 21 controls this interpolation sequential value that this loop filter 23 is exported.And when the sequential quality enters a defective mode, make these loop filter 23 fixing output one interpolation sequential backup values to this interpolater 21, so that this interpolater 21 references to be provided.
See also Fig. 3 again, it is the functional-block diagram of the preferred embodiment of loop filter 23 of the present invention and lockout controller 24.Loop filter 23 mainly comprises a phase register 40 and a frequency register 41, and lockout controller 24 consists predominantly of a lock detector 241, a register 242 and a multiplexer group (2431,2432).Lock detector 241 sends one according to the sequential quality of this synchronized sampling value signal and reads (Restore) signal or backup (Back-up) signal again.Wherein when the sequential quality enters this defective mode, send this and read signal again, and when the sequential quality enters a kilter, send this backup signal.Register 242 is used to store this interpolation sequential backup value.2431 triggerings of first multiplexer in this multiplexer group in response to this backup signal, and will be at that time in the frequency register 41 in stored this interpolation sequential value the count value about frequency back up in this register, to upgrade original interpolation sequential backup value.2432 of second multiplexers make these loop filter 23 outputs be stored in this interpolation sequential backup value in this register 242 in response to this reads the triggering of signal again.
See also Fig. 4 again, it is the functional-block diagram of a preferred embodiment of above-mentioned lock detector 241.Lock detector 241 consists predominantly of on the sequential attribute test device 2411 ,/a following counter 2412 and a comparator bank 2413.The ratio of the absolute value of two adjacent synchronized sampling value signals of sequential attribute test device 2411 bases zero crossover point both sides and the comparative result of a threshold value, and then send and count signal on one or count signal once to being somebody's turn to do/following counter 2412.And should on/following counter 2412 just in response to number signal this on maybe the triggering of this time number signal go up and count or following the number moved and produced a count value.2413 of comparator bank in response on this/count value of following counter 2412 and the comparative result that a backup threshold value and reads threshold value again, send this backup signal or this reads signal again.When count value greater than backup during threshold value, backup signal is 1, otherwise is 0.And when count value when reading threshold value again, reading signal again is 0, otherwise is 1.When backup signal is 1, this represents the signal quality of this moment still good, so can back up frequency.When this backup signal is 0, the low extremely a certain degree of the signal quality of this moment because this represents (such as, influenced by defect area), if so continue to utilize the frequency of defect area gained to carry out interpolation, the time of gained is with under-represented; So in time, will temporarily stop this interpolation sequential value of frequency register 41 is stored in this register 242.When reading signal again and be 0, represent this moment signal quality be judged as good, so can directly utilize the frequency of loop filter gained to carry out interpolation.When reading signal again and be 1, represent this moment signal quality not good, thus not directly utilize the frequency of loop filter gained to carry out interpolation, and need utilize the frequency of storing in the register 242 to carry out interpolation.So, in the present invention, face to face when signal quality is not good because the frequency during with better signal quality backs up, so the time can utilize the good signal quality time frequency of gained carry out interpolation, can obtain data read ability preferably.
The waveform schematic diagram of the synchronized sampling value signal shown in (b) can be known and finds out and from Fig. 5 (a) and figure, when the synchronized sampling value signal is shown in Fig. 5 (a), because the ratio of the absolute value of the two adjacent samples value 51,52 of zero crossover point 50 both sides is quite near ideal value " 1 ", therefore sequential attribute test device 2411 will be judged sequential quality (timing qualty) at this moment for good, and then send and count signal on one to being somebody's turn to do/following counter 2412.When the synchronized sampling value signal is shown in Fig. 5 (b), because the ratio of the absolute value of the two adjacent samples value 51,52 of zero crossover point 50 both sides will be away from ideal value " 1 ", therefore sequential attribute test device 2411 will judge this moment sequential quality (timingquality) for bad, and then send and count signals to being somebody's turn to do/following counter 2412.
See also Fig. 6 (a) again, it is the functional-block diagram that the present invention is applied to another preferred embodiment of the digital phase-locked loop device (All-digital PLL) in the disc accessing.It mainly is to incorporate other assembly except lock detector 241 in the above-mentioned lockout controller 24 (as register 242 and multiplexer group 243) into loop filter 23 and form just like loop filter 61 after the improvement shown in Fig. 6 (b).
The present invention by have the knack of this technology the personage did modifies the neither protection range that takes off claims as all.
Claims (10)
1, a kind of PLL device is characterized in that comprising:
One interpolater, receive that an input signal is handled and and an output signal;
One sequential error detector detects a sequential error amount of this output signal;
One loop filter is exported an interpolation sequential value to this interpolater according to this time value; And
One lockout controller is controlled this interpolation sequential value that this loop filter is exported according to the sequential quality of this output signal.
2, PLL device as claimed in claim 1 is characterized in that this lockout controller includes:
One lock detector sends one according to the sequential quality of this output and reads a signal or a backup signal again, sends this and read signal again when the sequential quality enters defective mode, and send this backup signal when the sequential quality enters a kilter;
One register is electrically connected on the output of this loop filter, in order to store this interpolation sequential backup value; And
One multiplexer group, be electrically connected between this loop filter and this register, determine whether this interpolation sequential value at that time is stored in this register in response to this backup signal, in addition, in response to reading signal again, this determine whether to make this loop filter utilization to be stored in this interpolation sequential backup value in this register.
3, PLL device as claimed in claim 2 is characterized in that this lock detector includes:
One sequential attribute test device is pursuant to the ratio and the comparative result of a threshold value of absolute value of two adjacent output signals of zero crossover point both sides, sends number signals or several signal on one once;
On one/following counter, in response to number signal on this maybe this time number signal triggering and go up number or following the number moved; And
One comparator bank is electrically connected on this/following counter, in response on this/count value and a backup threshold value and of following counter read the comparative result of threshold value again, and then sends this backup signal or this reads signal again.
4, PLL device as claimed in claim 1 is characterized in that this input signal is exported by an analog-digital converter, and this analog-digital converter is an analog voltage signal is taken a sample and to obtain this input signal.
5, PLL device as claimed in claim 1 it is characterized in that this input signal is an asynchronous sampling value signal, and this output signal is a synchronous sampling value signal.
6, PLL device as claimed in claim 1 is characterized in that this lockout controller is a lock detector, and this lock detector comprises:
One sequential attribute test device is pursuant to the ratio and the comparative result of a threshold value of absolute value of two adjacent output signals of zero crossover point both sides, and then sends number signals or several signal on one once;
On one/following counter, in response to number signal on this maybe this time number signal triggering and go up number or following the number moved; And
One comparator bank is electrically connected on this/following counter, in response on this/count value and a backup threshold value and of following counter read the comparative result of threshold value again, and then sends this backup signal or this reads signal again.
7, a kind of signal generating method is characterized in that comprising the following step:
Detect a sequential error amount of an input signal;
Export an interpolation sequential value according to this time value, with reference when handling an output signal;
When the sequential quality of this input signal during, carry out the frequency backup at kilter; And
When the sequential quality of this input signal enters a defective mode,, this input signal is carried out interpolation to obtain an output signal according to the frequency that is backed up.
8, signal generating method as claimed in claim 7 is characterized in that also comprising:
Send one according to the sequential quality of this output signal and read a signal or a backup signal again, wherein when the sequential quality enters defective mode, send this and read signal again, and when the sequential quality enters a kilter, send this backup signal.
9, signal generating method as claimed in claim 7 is characterized in that also comprising:
Determine whether will store at that time this interpolation sequential value upgrading this interpolation sequential backup value according to this backup signal, and whether determine this interpolation sequential backup value of fixed reference in response to this reads signal again.
10, signal generating method as claimed in claim 8 is characterized in that also comprising:
Be pursuant to the ratio of absolute value of two adjacent output signals of zero crossover point both sides and the comparative result of a threshold value, send on one the number signals or count signal once and produce a count value, and read the comparative result of threshold value again, and then send this backup signal or this reads signal again in response to this count value and a backup threshold value and.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021231133A CN1194473C (en) | 2002-06-07 | 2002-06-07 | Digital phase-locked loop device and signal generating method |
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| CNB021231133A CN1194473C (en) | 2002-06-07 | 2002-06-07 | Digital phase-locked loop device and signal generating method |
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| CN1387321A true CN1387321A (en) | 2002-12-25 |
| CN1194473C CN1194473C (en) | 2005-03-23 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1328724C (en) * | 2003-06-30 | 2007-07-25 | 三星电子株式会社 | System and method for time synchronization between multimedia content and segment metadata |
| US7545222B2 (en) | 2006-01-06 | 2009-06-09 | Realtek Semiconductor Corp. | Phase lock loop for rapid lock-in and method therefor |
| CN1933000B (en) * | 2005-09-13 | 2010-08-25 | 凌阳科技股份有限公司 | Time sequence recovery device and method with protection function |
| CN107689792A (en) * | 2017-09-15 | 2018-02-13 | 北京华大九天软件有限公司 | A kind of High Linear low-voltage phase interpolation circuit |
| CN112468140A (en) * | 2019-09-09 | 2021-03-09 | 瑞昱半导体股份有限公司 | Clock data recovery apparatus and method |
-
2002
- 2002-06-07 CN CNB021231133A patent/CN1194473C/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1328724C (en) * | 2003-06-30 | 2007-07-25 | 三星电子株式会社 | System and method for time synchronization between multimedia content and segment metadata |
| CN1933000B (en) * | 2005-09-13 | 2010-08-25 | 凌阳科技股份有限公司 | Time sequence recovery device and method with protection function |
| US7545222B2 (en) | 2006-01-06 | 2009-06-09 | Realtek Semiconductor Corp. | Phase lock loop for rapid lock-in and method therefor |
| CN107689792A (en) * | 2017-09-15 | 2018-02-13 | 北京华大九天软件有限公司 | A kind of High Linear low-voltage phase interpolation circuit |
| CN107689792B (en) * | 2017-09-15 | 2020-04-07 | 北京华大九天软件有限公司 | High-linearity low-voltage phase interpolation circuit |
| CN112468140A (en) * | 2019-09-09 | 2021-03-09 | 瑞昱半导体股份有限公司 | Clock data recovery apparatus and method |
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| Publication number | Publication date |
|---|---|
| CN1194473C (en) | 2005-03-23 |
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