CN1374807A - Multiple frequency output clock pulse signal synthesizer and its synthesis method - Google Patents
Multiple frequency output clock pulse signal synthesizer and its synthesis method Download PDFInfo
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- CN1374807A CN1374807A CN 02108027 CN02108027A CN1374807A CN 1374807 A CN1374807 A CN 1374807A CN 02108027 CN02108027 CN 02108027 CN 02108027 A CN02108027 A CN 02108027A CN 1374807 A CN1374807 A CN 1374807A
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Abstract
The multiple frequency output time pulse signal synthesizer and its synthesis method is used in converter to convert progressive scanned image data into interlaced scanned image data. The converter provides one first frequency F1 reference time pulse signal. The time pulse signal synthesizer includes phase-locked loop vibrator, frequency dividing feedback circuit, the first frquency dividing output circuit and the second frequency dividing output circuit. The time pulse signal synthesizing process includes receiving the first frequency F1 reference time pulse signal of frequency F1 to output one time pulse signal of frequency F1xN; and diving the clock pulse signal of frequency F1xN to output one first output time pulse signal of frequency F1xN/P1 and one second output time pulse signal of frequency F1xN/P2 with the P2/P1 value being regulated based on horizontal scanning line pixel number ratio between the progressive data and the interlaced data.
Description
Technical field
The present invention relates to a kind of clock signal synthesizer and clock signal synthetic method of multi-frequency output, refer to be applied to the clock signal synthesizer and the clock signal synthetic method of the multi-frequency output in the television signal encoder especially.
Background technology
Along with the rapid progress of manufacturing technology, PC has become people's necessary product of living, and it has powerful operation capacity, and the user can utilize it to finish the function of many other electronic products.Utilizing PC to play videodiscs such as VCD, DVD is an example, but it is too small because of the PC screen size usually, cause actual inconvenience of viewing and admiring, therefore provide television signal output to bring in and utilize general domestic TV to show, become the critical function of display card in the PC.
Fig. 1 (a) is the partial function block schematic diagram of a display card (display adapter), wherein graph processing chips 10 (graphic chip) is exported pixel data digital signal to a random access storage device arranged side by side digital to analog converter (Random Access Memory Digital-to-AnalogConverter, be called for short RAM DAC) 11 and one television signal encoder (TV encoder) 12, and this pixel data digital signal arranged side by side is the analog signal that can provide computer display 13 to show after the conversion of this random access storage device digital to analog converter 11.After the processing of this television signal encoder 12, can produce power supply as for this pixel data digital signal arranged side by side and look 14 anolog TV signals that show, and these anolog TV signals generally can be divided into NTSC and two kinds of specifications of PAL.
Fig. 1 (b) is the part function block schematic diagram of above-mentioned television signal encoder 12 inside, and wherein this pixel data digital signal arranged side by side is through data acquisition device (Data Capture device) 121, color space converter (Color Space Converter) 122, picture dimension adjustment and anti-scintillator (Scaler and Deflicker) 123, first-in first-out buffer (First-In First-Out buffer) 124, power supply be can produce after the conversion of NTSC/PAL encoder (NTSC/PAL encoder) 125 and one digital to analog converter (Digital-to-Analog Converter) 126 and 14 NTSC specification TV signal that show or PAL specification TV signal looked.
Wherein this picture dimension adjustment and 123 processing one of anti-scintillator export it in first-in first-out buffer 124 to behind the image data line by line, and NTSC/PAL encoder 125 takes out described data processing again from first-in first-out buffer 124, and then the interlacing image data that is separated into Qi Tuchang (odd field) and bigraph field (even field) is to show on TV.Therefore, picture dimension adjustment and 123 processing required times of two horizontal scanning lines of anti-scintillator equal NTSC/PAL encoder 125 and handle the required times of a horizontal scanning line, so just relation as the following equation of the frequency Fe of the frequency Fsd of picture dimension adjustment and anti-scintillator 123 required clock signals and NTSC/PAL encoder 125 required clock signals are represented:
Fsd/Fe=2 * H_sd/H_e....................... (formula 1)
Wherein H_sd is the pixel number of picture dimension adjustment and anti-scintillator 123 handled horizontal scanning lines, and H_e then is the pixel number of NTSC/PAL encoder 125 handled horizontal scanning lines.
But because the inside of television signal encoder 12 only has a phase-locked loop clock pulse generator 127 to produce clock signal to offer picture dimension adjustment and anti-scintillator 123 and NTSC/PAL encoder 125 simultaneously, make Fsd=Fe, therefore when more and more (1024 points for example of the horizontal scanning line pixel quantity of picture dimension adjustment and anti-scintillator 123 handled image datas line by line, 1152 points, 1365 in addition to 1600 points) time, the image width that is shown in after treatment on the television image (needs to increase because of Fsd increases with horizontal scanning line pixel quantity with more and more narrow, Fe=Fsd again, and excessive Fe will cause the pixel output frequency of horizontal scanning line on the video screen too fast, and then cause the image narrowed width), can't fully use the original effective width of TV.And how to improve the shortcoming of these existing means, be development main purpose of the present invention.
Summary of the invention
The present invention is a kind of clock signal synthesizer of multi-frequency output, be applied to the image data displaying of lining by line scan is converted in the transducer of an interlacing scan image data displaying, provide in this transducer a frequency be F1 first with reference to clock signal, and this clock signal synthesizer comprises: a phase-locked loop oscillator produces clock signal that a frequency is F1 * N with reference to clock signal and by its output output according to received this of its input first; One frequency elimination feedback circuit is electrically connected on the input of this phase-locked loop oscillator, and it receives this frequency is that the clock signal of F1 * N carries out a frequency elimination operation divided by N, so feed back a frequency be F1 the feedback clock signal to this phase-locked loop oscillator for its reference; One first frequency elimination output circuit is electrically connected on this phase-locked loop oscillator, and it receives this frequency is that the clock signal of F1 * N carries out a frequency elimination operation divided by P1, and then exports the first output clock signal that a frequency is F1 * N/P1; And one second frequency elimination output circuit, be electrically connected on this phase-locked loop oscillator, it receives this frequency is that the clock signal of F1 * N carries out a frequency elimination operation divided by P2, and then export the second output clock signal that a frequency is F1 * N/P2, wherein the value of this P2/P1 is adjusted according to the variation of ratio between the horizontal scanning line pixel number of the horizontal scanning line pixel number of this image data displaying of lining by line scan and this interlacing scan image data displaying.
According to above-mentioned conception, this frequency is exported by a preposition frequency eliminating circuit with reference to clock signal by first of F1 in the clock signal synthesizer of multi-frequency of the present invention output, it is that the original reference clock signal of D * F1 carries out a frequency elimination operation divided by D with frequency, and then exports the first output clock signal that this frequency is F1.
According to above-mentioned conception, this transducer is arranged on the television signal encoder in the display card in the clock signal synthesizer of multi-frequency output of the present invention.
According to above-mentioned conception, this frequency is that the first output clock signal of F1 * N/P1 and the second output clock signal of this F1 * N/P2 are an adjusted size and an anti-scintillator and NTSC/PAL encoders that offers respectively in this television signal encoder in the clock signal synthesizer of multi-frequency output of the present invention.
According to above-mentioned conception, this first frequency elimination output circuit and this second frequency elimination output circuit are finished divided by the P2 counter divided by P1 counter and by one respectively in the clock signal synthesizer of multi-frequency output of the present invention.
Another aspect of the present invention is a kind of clock signal synthetic method of multi-frequency output, be applied to the image data displaying of lining by line scan is converted in the transducer of an interlacing scan image data displaying, provide in this transducer a frequency be F1 first with reference to clock signal, and this clock signal synthetic method comprises: receive this and first produce the clock signal output that a frequency is F1 * N with reference to clock signal; And to receive this frequency be that the clock signal of F1 * N carries out a frequency elimination operation divided by P1, and then export the first output clock signal that a frequency is F1 * N/P1; And to receive this frequency be that the clock signal of F1 * N carries out a frequency elimination operation divided by P2, and then export the second output clock signal that a frequency is F1 * N/P2, wherein the value of this P2/P1 is to adjust according to the variation of ratio between the horizontal scanning line pixel number of the horizontal scanning line pixel number of this image data displaying of lining by line scan and this interlacing scan image data displaying.
According to above-mentioned conception, this frequency is that first of F1 is that frequency is that the original reference clock signal of D * F1 carries out is one resultant divided by the frequency elimination operation of D with reference to clock signal in the clock signal synthetic method of multi-frequency of the present invention output.
According to above-mentioned conception, this transducer is arranged on the television signal encoder in the display card in the clock signal synthetic method of multi-frequency output of the present invention.
According to above-mentioned conception, this frequency is that the first output clock signal of F1 * N/P1 and the second output clock signal of this F1 * N/P2 are an adjusted size and anti-scintillator and the NTSC/PAL encoders that offers respectively in this television signal encoder in the clock signal synthetic method of multi-frequency output of the present invention.
Description of drawings
Fig. 1 (a) is the partial function block schematic diagram of a display card.
Fig. 1 (b) is the partial function block schematic diagram of television signal encoder inside.
Fig. 2 is the preferred embodiment schematic diagram of the clock signal synthesizer of the present invention's multi-frequency output of developing out.
Embodiment
Fig. 2 is the preferred embodiment schematic diagram that improves the clock signal synthesizer that a multi-frequency that above-mentioned existing means shortcoming develops out exports, and it mainly is made of preposition frequency eliminating circuit 20, phase-locked loop oscillator 21, frequency elimination feedback circuit 22, the first frequency elimination output circuit 23 and the second frequency elimination output circuit 24.
Its medium frequency is that to be undertaken one by preposition frequency eliminating circuit 20 be that the first output clock signal of F1 is to phase-locked loop oscillator 21 divided by the frequency elimination of D operation back output one frequency to the original reference clock signal of D * F1, and phase-locked loop oscillator 21 is that to produce a frequency be the clock signal of F1 * N and export frequency elimination feedback circuit 22 to reference to clock signal according to received this first, it is that the clock signal of F1 * N carries out a frequency elimination operation divided by N that frequency elimination feedback circuit 22 receives these frequencies, so feed back a frequency be F1 the feedback clock signal to this phase-locked loop oscillator for its reference.As for can be respectively with divided by P1 counter and the first frequency elimination output circuit 23 and the second frequency elimination output circuit 24 finished divided by the P2 counter, it receives this frequency is the clock signal of F1 * N and carry out respectively divided by an operation of the frequency elimination of P1 and a frequency elimination operation divided by P2, and then exports the second output clock signal that the first output clock signal that a frequency is F1 * N/P1 and a frequency are F1 * N/P2 respectively.
And the frequency that said apparatus produced to be the second output clock signal of first output clock signal and this F1 * N/P2 of F1 * N/P1 just can offer the adjusted size in this television signal encoder 12 respectively and prevent scintillator 123 and NTSC/PAL encoder 125.And can obtain equation as follows in the substitution formula 1:
Fsd/Fe=P2/P1=2 * H_sd/H_e....................... (formula 2)
Therefore Fsd can change by the value of adjusting P2/P1 with the ratio of Fe, so just can come P2/P1 is finely tuned according to the variation of ratio between the horizontal scanning line pixel number of the horizontal scanning line pixel number of this image data displaying of lining by line scan and this interlacing scan image data displaying.For example, under situation about P1 being adjusted to, will make Fe less than Fsd, and then the television image image width that originally narrows down can be relaxed to meeting the original effective width of TV less than P2, effectively improve the shortcoming of existing means, and then realize main purpose of the present invention.
The present invention can carry out various variations and modification easily by those of ordinary skill in the industry, but does not all take off the protection range that claims define.
Claims (9)
1. the clock signal synthesizer of multi-frequency output, be applied to the image data displaying of lining by line scan is converted in the transducer of an interlacing scan image data displaying, provide in this transducer a frequency be F1 first with reference to clock signal, it is characterized in that this clock signal synthesizer comprises:
One phase-locked loop oscillator produces clock signal that a frequency is F1 * N with reference to clock signal and by its output output according to received this of its input first;
One frequency elimination feedback circuit is electrically connected on the input of this phase-locked loop oscillator, and it receives this frequency is that the clock signal of F1 * N carries out a frequency elimination operation divided by N, so feed back a frequency be F1 the feedback clock signal to this phase-locked loop oscillator for its reference;
One first frequency elimination output circuit is electrically connected on this phase-locked loop oscillator, and it receives this frequency is that the clock signal of F1 * N carries out a frequency elimination operation divided by P1, and then exports the first output clock signal that a frequency is F1 * N/P1; And
One second frequency elimination output circuit, be electrically connected on this phase-locked loop oscillator, it receives this frequency is that the clock signal of F1 * N carries out a frequency elimination operation divided by P2, and then export the second output clock signal that a frequency is F1 * N/P2, wherein the value of this P2/P1 is to adjust according to the variation of ratio between the horizontal scanning line pixel number of the horizontal scanning line pixel number of this image data displaying of lining by line scan and this interlacing scan image data displaying.
2. the clock signal synthesizer of multi-frequency output as claimed in claim 1, it is characterized in that described frequency is exported by a preposition frequency eliminating circuit with reference to clock signal by first of F1, it is that the original reference clock signal of D * F1 carries out a frequency elimination operation divided by D with frequency, and then exports the first output clock signal that this frequency is F1.
3. the clock signal synthesizer of multi-frequency output as claimed in claim 1 is characterized in that described transducer is arranged on the television signal encoder in the display card.
4. the clock signal synthesizer of multi-frequency output as claimed in claim 3 is characterized in that described frequency is that the first output clock signal of F1 * N/P1 and the second output clock signal of this F1 * N/P2 are an adjusted size and an anti-scintillator and NTSC/PAL encoders that offers respectively in this television signal encoder.
5. the clock signal synthesizer of multi-frequency output as claimed in claim 1 is characterized in that described first frequency elimination output circuit and the described second frequency elimination output circuit are finished divided by the P2 counter divided by P1 counter and by one respectively.
6. the clock signal synthetic method of multi-frequency output, be applied to the image data displaying of lining by line scan is converted in the transducer of an interlacing scan image data displaying, provide in this transducer a frequency be F1 first with reference to clock signal, it is characterized in that this clock signal synthetic method comprises:
Receive this and first produce the clock signal output that a frequency is F1 * N with reference to clock signal; And
The clock signal that receives this frequency and be F1 * N carries out a frequency elimination operation divided by P1, and then exports the first output clock signal that a frequency is F1 * N/P1; And
The clock signal that receives this frequency and be F1 * N carries out a frequency elimination operation divided by P2, and then export the second output clock signal that a frequency is F1 * N/P2, wherein the value of this P2/P1 is to adjust according to the variation of ratio between the horizontal scanning line pixel number of the horizontal scanning line pixel number of this image data displaying of lining by line scan and this interlacing scan image data displaying.
7. the clock signal synthetic method of multi-frequency as claimed in claim 6 output is characterized in that described frequency is that first of F1 is that frequency is that the original reference clock signal of D * F1 carries out is one resultant divided by the frequency elimination operation of D with reference to clock signal.
8. the clock signal synthetic method of multi-frequency output as claimed in claim 6 is characterized in that described transducer is arranged on the television signal encoder in the display card.
9. the clock signal synthetic method of multi-frequency output as claimed in claim 8 is characterized in that described frequency is that the first output clock signal of F1 * N/P1 and the second output clock signal of this F1 * N/P2 are an adjusted size and anti-scintillator and the NTSC/PAL encoders that offers respectively in this television signal encoder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02108027 CN1212738C (en) | 2002-03-22 | 2002-03-22 | Multiple frequency output clock pulse signal synthesizer and its synthesis method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02108027 CN1212738C (en) | 2002-03-22 | 2002-03-22 | Multiple frequency output clock pulse signal synthesizer and its synthesis method |
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| Publication Number | Publication Date |
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| CN1374807A true CN1374807A (en) | 2002-10-16 |
| CN1212738C CN1212738C (en) | 2005-07-27 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 02108027 Expired - Lifetime CN1212738C (en) | 2002-03-22 | 2002-03-22 | Multiple frequency output clock pulse signal synthesizer and its synthesis method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101854171A (en) * | 2010-05-21 | 2010-10-06 | 中兴通讯股份有限公司 | Multi-frequency point simulating phase-locked loop circuit |
| CN102857221A (en) * | 2011-06-30 | 2013-01-02 | 中兴通讯股份有限公司 | Phase locked loop, wide band transmitter and carrier wave leakage correction method of wide band transmitter |
-
2002
- 2002-03-22 CN CN 02108027 patent/CN1212738C/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101854171A (en) * | 2010-05-21 | 2010-10-06 | 中兴通讯股份有限公司 | Multi-frequency point simulating phase-locked loop circuit |
| CN102857221A (en) * | 2011-06-30 | 2013-01-02 | 中兴通讯股份有限公司 | Phase locked loop, wide band transmitter and carrier wave leakage correction method of wide band transmitter |
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| Publication number | Publication date |
|---|---|
| CN1212738C (en) | 2005-07-27 |
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