CN1359156A

CN1359156A - CMOS semiconductor device and making method

Info

Publication number: CN1359156A
Application number: CN 01139390
Authority: CN
Inventors: 小山内润; 长谷川尚; 小岩进雄; 石井和敏
Original assignee: Seiko Instruments Inc
Current assignee: Ablic Inc
Priority date: 2000-09-01
Filing date: 2001-09-01
Publication date: 2002-07-17
Anticipated expiration: 2021-09-01
Also published as: CN100543999C

Abstract

In a power management semiconductor device or analog semiconductor device having a CMOS and a resistor, a conductivity type of a gate electrode of the CMOS is P-type as to both an NMOS and a PMOS, a short channel and a low threshold voltage are possible since an E-type PMOS is surface channel type, the short channel and the low threshold voltage are possible since a buried channel type NMOS is extremely shallow for the reason that arsenic having a small diffusion coefficient can be used as an impurity for threshold control, and the resistor used in a voltage dividing circuit or CR circuit is formed of polycrystalline silicon thinner than the polycrystalline silicon of the same layer as the gate electrode or a thin film metal. Thus, the power management semiconductor device or analog semiconductor device, which is advantageous in terms of cost, manufacturing period and element performance in comparison with the conventional CMOS with an N+polycrystalline silicon gate single polarity or the same polarity gate CMOS in which a channel and a gate electrode have the same polarity, can be realized.

Description

Cmos semiconductor device and manufacture method thereof

TECHNICAL FIELD OF THE INVENTION

The present invention relates to make the method for semiconductor device, require low voltage operating, low-power consumption and high driving ability in this semiconductor device, The present invention be more particularly directed to power control semiconductor device, such as voltage detector (calling VD in the following text), voltage regulator (calling VR in the following text) or switching regulaor (calling SWR in the following text), perhaps simulation semiconductor device is such as operational amplifier or comparator.

The explanation of correlation technique

Figure 89 is the profile of conventional semiconductor device.This semiconductor device is made of a complementary MOS structure (calling CMOS in the following text) and a resistor, CMOS is made up of a N raceway groove (N-channel) MOS transistor (calling NMOS in the following text) and a P raceway groove (P-channel) MOS transistor (calling PMOS in the following text), the grid that is formed in NMOS on P type (P-type) Semiconductor substrate is made of N+ type (N+type) polysilicon, the grid that is formed at N trap (N-well) district in PMOS also is made of N+ type polysilicon, resistor is used for bleeder circuit and separates the voltage that forms on the field insulating membrane, perhaps is used for the CR circuit and comes the setting-up time constant.Resistor is formed by polysilicon, and it is with one deck and has identical conduction type with the grid with N type (N-type) conduction of CMOS, so that the simplification of its manufacture method and easy.

In having the semiconductor device of above-mentioned conventional structure, because having the grid of the enhancement mode NMOS (calling E type NMOS in the following text) of the level threshold value voltage of about 0.7V is made of N+ polysilicon (N+polycrystalline silicon), according to the relation of the work function of grid and Semiconductor substrate, the raceway groove that forms on the surface of Semiconductor substrate is a surface channel.On the other hand, in the enhancement mode PMOS of the level threshold value voltage with pact-0.7V (calling E type PMOS in the following text), according to the relation of the work function of grid that is made of the N+ polysilicon and N trap, the raceway groove that forms from the inner side surface of Semiconductor substrate is buried channel.

In buried channel E type PMOS, when for low voltage operating with threshold voltage settings for for example-0.5V or when higher, subthreshold value characteristic as an index of MOS transistor low voltage operating becomes bad significantly, and the leakage current when causing PMOS to end thus increases.As a result, the consumed current of biding one's time such as semiconductor device obviously increases.So produced such problem, be difficult to this semiconductor device application in the portable set such as portable phone and portable terminal, and portable set demand is very big and estimate that the future market will further expand in recent years.

As solving the above-mentioned low voltage operating and the technological means of low-power consumption problem, the homopolarity gate technique is known, and wherein, the conduction type of NMOS grid is set at the N type, and the conduction type of PMOS grid is set at the P type.In this case, E type NMOS and E type PMOS are the surface channel MOS transistor, and therefore, the reduction of threshold value can not cause that the remarkable change of subthreshold value characteristic is bad.Thus, low voltage operating and low-power consumption are possible.

Yet, be that the CMOS of N+ polysilicon one pole compares with grid, homopolarity grid CMOS has the problem that manufacturing process, manufacturing cost and manufacturing cycle increase, because will form grid respectively for NMOS and PMOS in manufacture process.

In addition, reference voltage circuit is a significant element circuit forming the power control semiconductor device such as VD, VR and SWR.Reference voltage circuit is always exported constant voltage with respect to the current potential of low-voltage power supply end from output, and irrelevant with the current potential of high voltage supply end.In many cases, reference voltage circuit is connected in series and is formed by an E type NMOS and a depletion type NMOS (calling D type NMOS in the following text).Polarity at grid is under the situation of N type, and according to the relation of grid and trap or substrate work function, E type NMOS is a surface channel, and D type NMOS is buried channel.Output voltage is a key property of reference voltage circuit for a short time with variation of temperature.But between surface channel and buried channel, the threshold voltage of MOS is greatly different with mutual conductance with the variation of temperature degree.As a result, reference voltage circuit has and is difficult to reduce the problem of output voltage with variation of temperature.

Summary of the invention

The present invention is based on the problems referred to above and proposes, and therefore an object of the present invention is to provide a kind of structure, and this structure makes it possible to realize the power control semiconductor device or the simulation semiconductor device of low cost, short manufacturing cycle, low voltage operating and low-power consumption.

In order to address the above problem, the present invention has adopted following measure.

According to the present invention, a kind of cmos semiconductor device is provided, and it has a N-channel MOS transistor, a P channel MOS transistor and a resistor, it is characterized in that, the conduction type of the transistorized grid of N-channel MOS is the P type, and the conduction type of the grid of P channel MOS transistor is the P type.

In addition, according to the present invention, a kind of cmos semiconductor device is provided, it is characterized in that, the P type grid of N-channel MOS transistorized P type grid and P channel MOS transistor comprises the first polysilicon individual layer separately, and this layer has the film thickness scope of 2000 dusts ()-6000 dust and comprises that impurity concentration is 1 * 10 ¹⁹Atom/cm ³Or higher boron (B) or BF ₂

In addition, according to the present invention, a kind of cmos semiconductor device is provided, it is characterized in that, the P type grid of N-channel MOS transistorized P type grid and P channel MOS transistor has a multilayer (polycide) structure separately, this structure comprises the lamination of first polysilicon and first refractory metal silicide, and first polysilicon has the film thickness of 1000 dusts-4000 dust and comprises that impurity concentration is 1 * 10 ¹⁹Atom/cm ³Or higher boron or BF ₂, first refractory metal silicide is selected from following material group: molybdenum silicide, tungsten silicide, titanium silicide and platinum silicide, and the film thickness scope is 500 dusts-2500 dusts.

In addition, according to the present invention, provide a kind of cmos semiconductor device, it is characterized in that, resistor is the polysilicon that forms in the layer identical with first polysilicon that constitutes grid, and has the film thickness scope identical with first polysilicon.

In addition, according to the present invention, provide a kind of cmos semiconductor device, it is characterized in that resistor is second polysilicon, its film thickness scope is 500 dusts-2000 dusts.

In addition, according to the present invention, a kind of cmos semiconductor device is provided, it is characterized in that, resistor is the film metal resistor that is formed by a kind of material that is selected from the following material group: Ni-Cr alloy, Cr-SiO alloy, molybdenum silicide and beta-iron silicide, and the film thickness scope is 100 dusts-300 dusts.

In addition,, provide a kind of cmos semiconductor device, it is characterized in that, comprised that the impure concentration of resistor packages of first or second polysilicon is 1 * 10 according to the present invention ¹⁴-9 * 10 ¹⁸Atom/cm ³Phosphorus or arsenic, and comprise a N transistor npn npn of low concentration, its film resistor is in the magnitude of a few k Ω/mouth-tens k Ω/mouth.

In addition,, provide a kind of cmos semiconductor device, it is characterized in that, comprised that the impure concentration of resistor packages of first or second polysilicon is 1 * 10 according to the present invention ¹⁹Atom/cm ³Or higher phosphorus or arsenic, and comprising the 2nd N transistor npn npn of higher concentration, its film resistor is in the magnitude of about 100 Ω/mouth-hundreds of Ω/mouth, and its temperature coefficient is in the magnitude of hundreds of ppm/ ℃-Yue 1000ppm/ ℃.

In addition,, provide a kind of cmos semiconductor device, it is characterized in that, comprised that the impure concentration of resistor packages of first or second polysilicon is 1 * 10 according to the present invention ¹⁴-9 * 10 ¹⁸Atom/cm ³Boron or BF ₂, and comprising a P transistor npn npn of low concentration, its film resistor is in the magnitude of a few k Ω/mouth-tens k Ω/mouth.

In addition,, provide a kind of cmos semiconductor device, it is characterized in that, comprised that the impure concentration of resistor packages of first or second polysilicon is 1 * 10 according to the present invention ¹⁹Atom/cm ³Or higher boron or BF ₂, and comprising the 2nd P transistor npn npn of higher concentration, its film resistor is in the magnitude of hundreds of Ω/mouth-Yue 1k Ω/mouth, and its temperature coefficient is in the magnitude of hundreds of ppm/ ℃-Yue 1000ppm/ ℃.

In addition, according to the present invention, a kind of cmos semiconductor device is provided, it is characterized in that, N-channel MOS transistor and P channel MOS transistor comprise a MOS transistor with first structure of single drain electrode structure, this structure comprises the diffusion layer with high impurity concentration, and wherein source electrode and drain electrode are with the overlapping P type of planar fashion grid.

In addition, according to the present invention, a kind of cmos semiconductor device is provided, it is characterized in that, N-channel MOS transistor and P channel MOS transistor comprise a MOS transistor with second structure, this structure comprises: a diffusion layer with low impurity concentration, wherein have only drain side with planar fashion overlapping P type grid or source side and drain side all with the overlapping P type of planar fashion grid; With a diffusion layer with high impurity concentration, wherein have only drain side not with planar fashion overlapping P type grid or source side and drain side all not with the overlapping P type of planar fashion grid.

In addition, according to the present invention, a kind of cmos semiconductor device is provided, it is characterized in that, N-channel MOS transistor and P channel MOS transistor comprise a MOS transistor with the 3rd structure, this structure comprises: a diffusion layer with low impurity concentration, wherein have only drain side with planar fashion overlapping P type grid or source side and drain side all with the overlapping P type of planar fashion grid; Diffusion layer with high impurity concentration, wherein have only drain side not with planar fashion overlapping P type grid or source side and drain side all not with the overlapping P type of planar fashion grid; And a dielectric film, it is between diffusion layer with high impurity concentration and P type grid, and its film thickness is greater than gate insulating film.

In addition, according to the present invention, a kind of cmos semiconductor device is provided, it is characterized in that, N-channel MOS transistor and P channel MOS transistor comprise a MOS transistor with the 4th structure, this structure comprises: a diffusion layer with high impurity concentration, and wherein source electrode and drain electrode are all with the overlapping P type of planar fashion grid; With a diffusion layer with low impurity concentration, wherein have only drain side all further to spread in the raceway groove side in the further diffusion of raceway groove side or source side and drain side, thereby by the overlapping P type of planar fashion grid.

In addition, according to the present invention, provide a kind of cmos semiconductor device, it is characterized in that, in the N-channel MOS transistor, the raceway groove that threshold voltage improves is buried channel.

In addition, according to the present invention, provide a kind of cmos semiconductor device, it is characterized in that, in the P channel MOS transistor, the raceway groove that threshold voltage improves is a surface channel.

In addition, according to the present invention, a kind of cmos semiconductor device is provided, it is characterized in that, low impurity concentration diffusion layer in the MOS transistor of the MOS transistor of the MOS transistor of second structure, the 3rd structure and the 4th structure uses arsenic or phosphorus as impurity in the N-channel MOS transistor, and impurity concentration is 1 * 10 ¹⁶-1 * 10 ¹⁸Atom/cm ³, and in the P channel MOS transistor, use boron or BF ₂As impurity, impurity concentration is 1 * 10 ¹⁶-1 * 10 ¹⁸Atom/cm ³High impurity concentration diffusion layer in the MOS transistor of the MOS transistor of the MOS transistor of the MOS transistor of first structure, second structure, the 3rd structure and the 4th structure uses arsenic or phosphorus as impurity in the N-channel MOS transistor, and impurity concentration is 1 * 10 ¹⁶-1 * 10 ¹⁸Atom/cm ³Or higher, and in the P channel MOS transistor, use boron or BF ₂As impurity, impurity concentration is 1 * 10 ¹⁶-1 * 10 ¹⁸Atom/cm ³Or it is higher.

In addition,, provide a kind of method of making the cmos semiconductor device, may further comprise the steps according to the present invention:

In Semiconductor substrate, be formed for defining the trap of the respective area of N-channel MOS transistor and P channel MOS transistor;

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

In Semiconductor substrate, mix the impurity that is used to control threshold value;

On Semiconductor substrate, form first polysilicon film;

In first polysilicon film, optionally mix low concentration N type impurity, in first polysilicon film, to form a N type district;

In first polysilicon film, optionally mix the high concentration p type impurity, in first polysilicon film, to form first p type island region;

In the whole zone of first polysilicon film, mix the low concentration p type impurity, in first polysilicon film, to form second p type island region;

On first polysilicon film, form first dielectric film;

First dielectric film and first polysilicon film are carried out composition, in order to forming grid and wiring, and form resistor by a N type multi-crystal silicon area and the 2nd P type multi-crystal silicon area by a P type multi-crystal silicon area;

Optionally remove first dielectric film on the resistor;

To the zone that becomes transistorized source electrode of N-channel MOS and drain electrode and to a part or the whole zone of the resistor that forms by a N type multi-crystal silicon area, mix high concentration N type impurity; With

To the zone of source electrode that becomes the P channel MOS transistor and drain electrode and to a part or the whole zone of the resistor that forms by the 2nd P type multi-crystal silicon area, mix the high concentration p type impurity.

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

In the whole zone of first polysilicon film, mix the high concentration p type impurity, in first polysilicon film, to form first p type island region;

On first polysilicon film, form refractory metal silicide film;

On refractory metal silicide film, form first dielectric film;

First polysilicon film to first dielectric film, refractory metal silicide film and first p type island region carries out composition, in order to form grid and wiring;

On Semiconductor substrate, form the 4th dielectric film;

On the 4th dielectric film, form second polysilicon film;

In second polysilicon film, optionally mix low concentration N type impurity, in second polysilicon film, to form a N type district;

In the whole zone of second polysilicon film, mix the low concentration p type impurity, in second polysilicon film, to form second p type island region;

Second polysilicon film is carried out composition, form resistor;

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

In the whole zone of first polysilicon film, mix the high concentration p type impurity, to form first p type island region of first polysilicon film;

On first polysilicon film, form high melting point metal film;

The high melting point metal film that contacts with first polysilicon film is heat-treated, to obtain refractory metal silicide film;

On refractory metal silicide film, form first dielectric film;

On Semiconductor substrate, form the 4th dielectric film;

On the 4th dielectric film, form second polysilicon film;

Second polysilicon film is carried out composition, form resistor;

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

On first polysilicon film, form first dielectric film;

Low concentration N type impurity is mixed in the zone that optionally becomes transistorized source electrode of N-channel MOS and drain electrode in Semiconductor substrate;

In Semiconductor substrate, become the source electrode of P channel MOS transistor and the zone of drain electrode and mix the low concentration p type impurity;

Deposit the 3rd dielectric film on Semiconductor substrate;

By anisotropic dry etch methods, etching the 3rd dielectric film is isolated to form side on the sidewall of first polysilicon film;

Optionally remove first dielectric film on the resistor;

To a part or the whole zone of zone that becomes transistorized source electrode of N-channel MOS and drain electrode and the resistor that forms to a N type district, mix high concentration N type impurity by first polysilicon film; With

To a part or the whole zone of the zone of source electrode that becomes the P channel MOS transistor and drain electrode and the resistor that forms to second p type island region, mix the high concentration p type impurity by first polysilicon film.

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

On first polysilicon film, form first dielectric film;

First dielectric film and first polysilicon film are carried out composition, in order to forming grid and wiring, and form resistor area by the zone except that a P type polysilicon film district by a P type multi-crystal silicon area;

Optionally remove first dielectric film on the resistor area;

Optionally to the zone that becomes transistorized source electrode of N-channel MOS and drain electrode and to the polysilicon film except that a P type polysilicon film district, mix low concentration N type impurity, with the N type source electrode of formation low concentration and the N type district in the drain electrode and first polysilicon film;

Optionally to the zone of source electrode that becomes the P channel MOS transistor and drain electrode and to first polysilicon film except that a P type polysilicon film district and a N type polysilicon film district, mix the low concentration p type impurity, with the P type source electrode of formation low concentration and second p type island region in the drain electrode and first polysilicon film;

Deposit the 3rd dielectric film on Semiconductor substrate;

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

In first polysilicon film, mix the high concentration p type impurity, to form a P type multi-crystal silicon area;

On first polysilicon film, form first dielectric film;

First dielectric film and first polysilicon film are carried out composition, in order to form grid and wiring by first multi-crystal silicon area;

Optionally in Semiconductor substrate, become the zone of transistorized source electrode of N-channel MOS and drain electrode, mix low concentration N type impurity;

Optionally in Semiconductor substrate, become the source electrode of P channel MOS transistor and the zone of drain electrode, mix the low concentration p type impurity;

Deposit the 3rd dielectric film on Semiconductor substrate;

On Semiconductor substrate, form second polysilicon film;

Optionally in second polysilicon film, mix low concentration N type impurity, to form a N type impurity range;

In the whole zone of second polysilicon film, mix the low concentration p type impurity, to form and P type multi-crystal silicon area;

Second polysilicon film is carried out composition, form resistor;

Optionally, mix high concentration N type impurity to a part or the whole zone of zone that becomes transistorized source electrode of N-channel MOS and drain electrode and the resistor that forms to a N type district by second polysilicon film; With

Optionally, mix the high concentration p type impurity to a part or the whole zone of the zone of source electrode that becomes the P channel MOS transistor and drain electrode and the resistor that forms to second p type island region by second polysilicon film.

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

Optionally in first polysilicon film, mix low concentration N type impurity, to form a N type multi-crystal silicon area;

Optionally in first polysilicon film, mix the high concentration p type impurity, to form a P type multi-crystal silicon area;

In the whole zone of first polysilicon film, mix the low concentration p type impurity, to form the 2nd P type multi-crystal silicon area;

On first polysilicon film, form second dielectric film;

Optionally remove second dielectric film on first p type island region of first polysilicon film;

On Semiconductor substrate, form refractory metal silicide film;

Optionally remove on second dielectric film of composition and near refractory metal silicide film;

Remove second dielectric film of composition;

On the refractory metal silicide film and first polysilicon film, form first dielectric film;

First dielectric film, first polysilicon film and refractory metal silicide film are carried out composition, in order to forming grid and wiring, and form resistor by a N type district and second p type island region of first polysilicon film by first p type island region of first polysilicon film and the lamination of refractory metal silicide film;

Deposit the 3rd dielectric film on Semiconductor substrate;

By anisotropic dry etch methods, etching the 3rd dielectric film is isolated to form side on the sidewall of first polysilicon film and refractory metal silicide film;

Optionally remove first dielectric film on the resistor;

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

On first polysilicon film, form second dielectric film;

On Semiconductor substrate, form refractory metal silicide film;

Remove second dielectric film of composition;

First dielectric film, first polysilicon film and refractory metal silicide film are carried out composition, in order to forming grid and wiring, and form resistor area by the zone except that first p type island region of first polysilicon film by first p type island region of first polysilicon film and the lamination of refractory metal silicide film;

Optionally remove first dielectric film on the resistor area;

Optionally, mix low concentration N type impurity, in first polysilicon film, to form low concentration N type source electrode and a drain electrode and a N type district to zone that becomes transistorized source electrode of N-channel MOS and drain electrode and first polysilicon film except that first p type island region;

Optionally to the zone of source electrode that becomes the P channel MOS transistor and drain electrode and first polysilicon film except that first p type island region and a N type district, mix the low concentration p type impurity, in first polysilicon film, to form low concentration P type source electrode and the drain electrode and second p type island region;

Deposit the 3rd dielectric film on Semiconductor substrate;

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

On first polysilicon film, form second dielectric film;

On Semiconductor substrate, form high melting point metal film;

Optionally remove the unreacted high melting point metal film on second dielectric film;

Remove second dielectric film of composition;

Deposit the 3rd dielectric film on Semiconductor substrate;

Optionally remove first dielectric film on the resistor;

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

On first polysilicon film, form second dielectric film;

On Semiconductor substrate, form high melting point metal film;

Remove second dielectric film of composition;

Optionally remove first dielectric film on the resistor area;

Optionally, mix low concentration N type impurity, with the N type source electrode of formation low concentration and the N type district in the drain electrode and first polysilicon film to zone that becomes transistorized source electrode of N-channel MOS and drain electrode and first polysilicon film except that first p type island region;

Deposit the 3rd dielectric film on Semiconductor substrate;

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

On first polysilicon film, form refractory metal silicide film;

On refractory metal silicide film, form first dielectric film;

First polysilicon film to first dielectric film, refractory metal silicide film and first p type island region carries out composition, to form grid and wiring;

Deposit the 3rd dielectric film on Semiconductor substrate;

On Semiconductor substrate, form second polysilicon film;

Optionally in second polysilicon film, mix low concentration N type impurity, to form a N type multi-crystal silicon area;

In the whole zone of second polysilicon film, mix the low concentration p type impurity, to form the 2nd P type multi-crystal silicon area;

Second polysilicon film is carried out composition, to form resistor;

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

On first polysilicon film, form high melting point metal film;

On refractory metal silicide film, form first dielectric film;

First dielectric film, refractory metal silicide film and first polysilicon film are carried out composition, to form grid and wiring;

Deposit the 3rd dielectric film on Semiconductor substrate;

On Semiconductor substrate, form second polysilicon film;

Second polysilicon film is carried out composition, to form resistor;

To a part or the whole zone of zone that becomes transistorized source electrode of N-channel MOS and drain electrode and the resistor that forms to a N type district, mix high concentration N type impurity by second polysilicon film; With

To a part or the whole zone of the zone of source electrode that becomes the P channel MOS transistor and drain electrode and the resistor that forms to second p type island region, mix the high concentration p type impurity by second polysilicon film.

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

Optionally in first polysilicon film, mix the high concentration p type impurity, in first polysilicon film, to form a P type multi-crystal silicon area;

In the whole zone of first polysilicon film, mix the low concentration p type impurity, in first polysilicon film, to form the 2nd P type multi-crystal silicon area;

First polysilicon film is carried out composition, form grid and wiring, and form resistor by a N type district and second p type island region of first polysilicon film in order to first p type island region by first polysilicon film;

In Semiconductor substrate, mix low concentration N type impurity, so that source electrode and drain electrode are with the transistorized grid of the overlapping N-channel MOS of planar fashion;

Optionally in Semiconductor substrate, mix the low concentration p type impurity, so that source electrode and drain electrode or have only the grid of drain side with the overlapping P channel MOS transistor of planar fashion;

Optionally high concentration N type impurity is mixed in the part of the resistor that forms to the N type district by first polysilicon film or whole zone and to not with the source electrode and the drain region of the transistorized grid of the overlapping N-channel MOS of planar fashion; With

Optionally the high concentration p type impurity is mixed in the part of the resistor that forms to second p type island region by first polysilicon film or whole zone and do not have only drain side not with the zone of the overlapping grid of planar fashion with the zone or the source side of the grid of the overlapping P channel MOS transistor of planar fashion with the overlapping grid of planar fashion to source electrode and drain electrode.

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

First polysilicon film is carried out composition, form grid and wiring, and form resistor by the zone except that first p type island region of first polysilicon film in order to first p type island region by first polysilicon film;

Optionally in first polysilicon film except that source electrode and drain electrode in the Semiconductor substrate and the zone first p type island region with the transistorized grid of the overlapping N-channel MOS of planar fashion, mix low concentration N type impurity, in low concentration N type source electrode and the drain electrode and first polysilicon film, to form a N type district;

Optionally in first polysilicon film except that source electrode and drain electrode or have only drain side with in the zone Semiconductor substrate, first p type island region and the N type district of the grid of the overlapping P channel MOS transistor of planar fashion, mix the low concentration p type impurity, with in the low concentration source electrode and the drain electrode of P channel MOS transistor or have only and form second p type island region in the drain electrode and first polysilicon film;

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

In first polysilicon film, mix the high concentration p type impurity, in first polysilicon film, to form a P type multi-crystal silicon area;

First polysilicon film is carried out composition, in order to form grid and wiring by first p type island region;

On Semiconductor substrate, form the 4th dielectric film;

On Semiconductor substrate, form second polysilicon film;

Optionally in second polysilicon film, mix low concentration N type impurity, in second polysilicon film, to form a N type district;

Second polysilicon film is carried out composition, form resistor;

In Semiconductor substrate, mix low concentration N type impurity, make source electrode and drain electrode with the transistorized grid of the overlapping N-channel MOS of planar fashion;

In Semiconductor substrate, mix the low concentration p type impurity, make source electrode and drain electrode or have only the grid of drain side with the overlapping P channel MOS transistor of planar fashion;

Optionally high concentration N type impurity is mixed in the part of the resistor that forms to the N type district by second polysilicon film or whole zone and to not with the source electrode and the drain region of the transistorized grid of the overlapping N-channel MOS of planar fashion; With

Optionally the high concentration p type impurity is mixed in the part of the resistor that forms to second p type island region by second polysilicon film or whole zone and do not have only drain side not with the zone of the overlapping grid of planar fashion with the zone or the source side of the grid of the overlapping P channel MOS transistor of planar fashion with the overlapping grid of planar fashion to source electrode and drain electrode.

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

On Semiconductor substrate, form the 4th dielectric film;

On Semiconductor substrate, form second polysilicon film;

Second polysilicon film is carried out composition, in order to form resistor;

Optionally in the zone and second polysilicon film of source electrode and drain electrode transistorized grid of overlapping N-channel MOS with planar fashion, mix low concentration N type impurity, in the transistorized low concentration source electrode of N-channel MOS and the drain electrode and second polysilicon film, to form a N type district simultaneously;

Optionally to source electrode and drain electrode or have only in the zone and second polysilicon film of drain side grid of overlapping P channel MOS transistor with planar fashion, mix the low concentration p type impurity, with simultaneously in the low concentration source electrode and the drain electrode of P channel MOS transistor or have only and form second p type island region in the drain electrode and second polysilicon film;

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

Optionally in first polysilicon film, mix low concentration N type impurity, in first polysilicon film, to form a N type multi-crystal silicon area;

On first polysilicon film, form second dielectric film;

Optionally remove second dielectric film on the P type multi-crystal silicon area of first polysilicon film;

On Semiconductor substrate, form refractory metal silicide film;

Remove second dielectric film of composition;

First polysilicon film and refractory metal silicide film are carried out composition, forming grid and wiring, and form resistor area by a N type district and second p type island region of first polysilicon film by first p type island region of first polysilicon film and the lamination of refractory metal silicide film;

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

Optionally in first polysilicon film, mix the high concentration p type impurity, in first polysilicon film, to form first p type island region;

On first polysilicon film, form second dielectric film;

On Semiconductor substrate, form refractory metal silicide film;

Remove second dielectric film of composition;

First polysilicon film and refractory metal silicide film are carried out composition, forming grid and wiring, and form resistor area by the zone except that first p type island region of first polysilicon film by first p type island region of first polysilicon film and the lamination of refractory metal silicide film;

Optionally in the zone and first polysilicon film except that first p type island region of source electrode and drain electrode transistorized grid of overlapping N-channel MOS with planar fashion, mix low concentration N type impurity, in the transistorized low concentration source electrode of N-channel MOS and the drain electrode and first polysilicon film, to form a N type district simultaneously;

Optionally to source electrode and drain electrode or have only in the zone and first polysilicon film except that first p type island region and a N type district of grid of drain side overlapping P channel MOS transistor with planar fashion, mix the low concentration p type impurity, with simultaneously in the low concentration source electrode and the drain electrode of P channel MOS transistor or have only and form second p type island region in the drain electrode and first polysilicon film;

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

Optionally in first polysilicon film, mix low concentration N type impurity, in first polysilicon film, to form a N type district;

On first polysilicon film, form second dielectric film;

On Semiconductor substrate, form high melting point metal film;

The high melting point metal film that contacts first polysilicon film is heat-treated, to obtain refractory metal silicide film;

Remove second dielectric film of composition;

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

On first polysilicon film, form second dielectric film;

On Semiconductor substrate, form high melting point metal film;

Remove second dielectric film of composition;

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

In first polysilicon film, mix the high concentration p type impurity, in first polysilicon film, to form first p type island region;

On first polysilicon film, form refractory metal silicide film;

The refractory metal silicide film and first polysilicon film are carried out composition, to form grid and wiring by first p type island region of first polysilicon film and the lamination of refractory metal silicide film;

On Semiconductor substrate, form the 4th dielectric film;

On Semiconductor substrate, form second polysilicon film;

Second polysilicon film is carried out composition, form resistor;

Optionally in Semiconductor substrate, mix the low concentration p type impurity, make source electrode and drain electrode or have only the grid of drain side with the overlapping P channel MOS transistor of planar fashion;

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

On first polysilicon film, form refractory metal silicide film;

On Semiconductor substrate, form the 4th dielectric film;

On Semiconductor substrate, form second polysilicon film;

Second polysilicon film is carried out composition, form resistor;

Optionally to source electrode and drain electrode or have only in the zone and second polysilicon film of drain side grid of overlapping P channel MOS transistor with planar fashion, mix the low concentration p type impurity, with simultaneously in the low concentration source electrode and the drain electrode of P channel MOS transistor or have only formation second p type island region in the drain electrode and second polysilicon film;

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

On first polysilicon film, form high melting point metal film;

On Semiconductor substrate, form the 4th dielectric film;

On Semiconductor substrate, form second polysilicon film;

Second polysilicon film is carried out composition, form resistor;

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

On first polysilicon film, form high melting point metal film;

On Semiconductor substrate, form the 4th dielectric film;

On Semiconductor substrate, form second polysilicon film;

Second polysilicon film is carried out composition, form resistor;

Optionally low concentration N type impurity is mixed in the part of the resistor that forms to the N type district by second polysilicon film or whole zone and to not with the source electrode and the drain region of the transistorized grid of the overlapping N-channel MOS of planar fashion; With

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

On first polysilicon film, form refractory metal silicide film;

On refractory metal silicide film, form first dielectric film;

On Semiconductor substrate, form the 4th dielectric film;

On Semiconductor substrate, form second polysilicon film;

Second polysilicon film is carried out composition, form resistor;

Optionally in Semiconductor substrate, mix low concentration N type impurity, make source electrode and drain electrode or have only drain side with the transistorized grid of the overlapping N-channel MOS of planar fashion;

Optionally low concentration N type impurity is mixed in the part of the resistor that forms to the N type district by second polysilicon film or whole zone and to not having only drain side not with the zone of the overlapping grid of planar fashion with the source electrode of the transistorized grid of the overlapping N-channel MOS of planar fashion and drain region or source side with the overlapping grid of planar fashion; With

In addition,, provide a kind of cmos semiconductor device, it is characterized in that Semiconductor substrate is the P type semiconductor substrate, and the zone of N-channel MOS transistor and P channel MOS transistor is defined by forming N type trap respectively according to the present invention.

In addition,, provide a kind of cmos semiconductor device, it is characterized in that Semiconductor substrate is the P type semiconductor substrate, and the zone of N-channel MOS transistor and P channel MOS transistor is defined by forming N type trap and P type trap respectively according to the present invention.

In addition,, provide a kind of cmos semiconductor device, it is characterized in that Semiconductor substrate is the N type semiconductor substrate, and the zone of N-channel MOS transistor and P channel MOS transistor is defined by forming P type trap respectively according to the present invention.

In addition,, provide a kind of cmos semiconductor device, it is characterized in that Semiconductor substrate is the N type semiconductor substrate, and the zone of N-channel MOS transistor and P channel MOS transistor is defined by forming N type trap and P type trap respectively according to the present invention.

In addition,, provide a kind of method of making the cmos semiconductor device, it is characterized in that Semiconductor substrate is the P type semiconductor substrate, and the zone of N-channel MOS transistor and P channel MOS transistor is defined by forming N type trap respectively according to the present invention.

In addition, according to the present invention, a kind of method of making the cmos semiconductor device is provided, it is characterized in that, Semiconductor substrate is the P type semiconductor substrate, and the zone of N-channel MOS transistor and P channel MOS transistor is defined by forming N type trap and P type trap respectively.

In addition,, provide a kind of method of making the cmos semiconductor device, it is characterized in that Semiconductor substrate is the N type semiconductor substrate, and the zone of N-channel MOS transistor and P channel MOS transistor is defined by forming P type trap respectively according to the present invention.

In addition, according to the present invention, a kind of method of making the cmos semiconductor device is provided, it is characterized in that, Semiconductor substrate is the N type semiconductor substrate, and the zone of N-channel MOS transistor and P channel MOS transistor is defined by forming N type trap and P type trap respectively.

In addition, according to the present invention, provide a kind of method of making the cmos semiconductor device, it is characterized in that, the step that forms element isolation zone on Semiconductor substrate realizes by the LOCOS method.

In addition, according to the present invention, provide a kind of method of making the cmos semiconductor device, it is characterized in that, the step that forms element isolation zone on Semiconductor substrate realizes by shallow trench isolation method.

In addition, according to the present invention, a kind of method of making the cmos semiconductor device is provided, it is characterized in that, the step of mixing the impurity that is used for threshold value control realizes by ion injection method, and the impurity that is used for the transistorized threshold value control of N-channel MOS is arsenic or phosphorus.

In addition,, provide a kind of method of making the cmos semiconductor device, it is characterized in that first polysilicon film forms by chemical vapor deposition method according to the present invention.

In addition, according to the present invention, provide a kind of method of making the cmos semiconductor device, it is characterized in that, second polysilicon film forms by chemical vapor deposition method or sputtering method.

In addition,, provide a kind of method of making the cmos semiconductor device, it is characterized in that first p type island region of first polysilicon film forms by the following method: with boron or BF according to the present invention ₂Method for implanting as impurity; With boron as the pre-deposited method in electric furnace of impurity with drive into (drive-in) method; With the molecular layer doping method of boron as impurity.

In addition, according to the present invention, a kind of method of making the cmos semiconductor device is provided, it is characterized in that, the step that forms first p type island region of first polysilicon film realizes by chemical vapor deposition method, is used for deposit polysilicon and while doped with boron as impurity.

In addition, according to the present invention, provide a kind of method of making the cmos semiconductor device, it is characterized in that, first dielectric film is the silicon oxide film that forms by chemical vapor deposition method or thermal oxidation process, and has the film thickness of 1000 -2000 .

In addition, according to the present invention, provide a kind of method of making the cmos semiconductor device, it is characterized in that, first dielectric film is the silicon oxide film that forms by chemical vapor deposition method, and has the film thickness of 1000 -2000 .

In addition, according to the present invention, provide a kind of method of making the cmos semiconductor device, it is characterized in that, the lower floor of first dielectric film is the silicon oxide film that forms by chemical vapor deposition method or thermal oxidation process; Its upper strata forms by chemical vapor deposition method; And total film thickness of first dielectric film is 1000 -3000 .

In addition, according to the present invention, provide a kind of method of making the cmos semiconductor device, it is characterized in that, second dielectric film forms by chemical vapor deposition method, and has the film thickness of 1000 -4000 .

In addition, according to the present invention, provide a kind of method of making the cmos semiconductor device, it is characterized in that, the 3rd dielectric film is the silicon oxide film that forms by chemical vapor deposition method, and has total film thickness of 2000 -6000 .

In addition, according to the present invention, provide a kind of cmos semiconductor device, it is characterized in that, refractory metal silicide film forms by chemical vapor deposition method or sputtering method.

In addition, according to the present invention, provide a kind of method of making the cmos semiconductor device, it is characterized in that, refractory metal silicide film forms by chemical vapor deposition method or sputtering method.

In addition, according to the present invention, provide a kind of method of making the cmos semiconductor device, it is characterized in that, refractory metal is cobalt (Co) or the titanium (Ti) that forms by sputtering method, and has the film thickness of 100 -500 .

In addition, according to the present invention, a kind of cmos semiconductor device is provided, it is characterized in that, in a reference voltage circuit, the grid of an enhancement mode nmos pass transistor of grid and drain short circuit and drain electrode are connected to the grid and the source electrode of a depletion type nmos transistor of grid and source electrode short circuit, and connected node is as output node, in this circuit, the polarity of the grid of enhancement mode nmos pass transistor and depletion type nmos transistor is the P type.

In addition, according to the present invention, a kind of cmos semiconductor device is provided, it is characterized in that, in a reference voltage circuit, the source electrode of an enhancement mode nmos pass transistor of grid and drain short circuit is connected to the drain electrode of a depletion type nmos transistor of grid and source electrode short circuit, and connected node is as output node, in this circuit, the polarity of the grid of enhancement mode nmos pass transistor and depletion type nmos transistor is the P type.

In addition, according to the present invention, a kind of cmos semiconductor device is provided, it is characterized in that in a reference voltage circuit, the grid of an enhancement mode nmos pass transistor of grid and drain short circuit and drain electrode are connected to the source electrode of a depletion type nmos transistor, the source electrode short circuit of the grid of depletion type nmos transistor and enhancement mode nmos pass transistor, and connected node is as output node, and in this circuit, the polarity of the grid of enhancement mode nmos pass transistor and depletion type nmos transistor is the P type.

In addition, according to the present invention, a kind of cmos semiconductor device is provided, it is characterized in that, in a reference voltage circuit, the drain electrode of a depletion type nmos transistor of grid and source electrode short circuit is connected to first enhancement mode PMOS transistor drain and grid, and the transistorized source electrode of the first enhancement mode PMOS is connected to a power supply; The second enhancement mode PMOS transistor drain is connected to the grid and the drain electrode of the short circuit of an enhancement mode nmos pass transistor, and the transistorized source electrode of the second enhancement mode PMOS is connected to a power supply, and its grid is typically connected to the first enhancement mode PMOS transistor; And connected node is as output node, and in this circuit, the polarity of the grid of enhancement mode nmos pass transistor and depletion type nmos transistor is the P type.

In addition, according to the present invention, a kind of cmos semiconductor device is provided, it is characterized in that, in a reference voltage circuit, the drain electrode of first depletion type nmos transistor of grid and source electrode short circuit is connected to the grid and the source electrode of second depletion type nmos transistor of grid and source electrode short circuit; The drain electrode of second depletion type nmos transistor is connected to a power supply; The source electrode of first depletion type nmos transistor is connected to an enhancement mode nmos pass transistor of grid and drain short circuit; And connected node is as output node, and in this circuit, the polarity of the grid of enhancement mode nmos pass transistor, first depletion type nmos transistor and second depletion type nmos transistor is the P type.

In addition, according to the present invention, a kind of cmos semiconductor device is provided, it is characterized in that, in a reference voltage circuit, the grid of an enhancement mode nmos pass transistor of grid and drain short circuit and drain electrode are connected to the source electrode of first depletion type nmos transistor, and the grid of first depletion type nmos transistor is connected to the source electrode of enhancement mode nmos pass transistor; The drain electrode of first depletion type nmos transistor is connected to the grid and the source electrode of second depletion type nmos transistor of grid and source electrode short circuit; The drain electrode of second depletion type nmos transistor is connected to a power supply; The connected node of the source electrode of the drain electrode of enhancement mode nmos pass transistor and first depletion type nmos transistor is as output node, in this circuit, the polarity of the grid of enhancement mode nmos pass transistor, first depletion type nmos transistor and second depletion type nmos transistor is the P type.

Brief description of drawings

In the accompanying drawing:

Fig. 1 is the profile by the cmos semiconductor device of first embodiment of the invention;

Fig. 2 is the profile by the cmos semiconductor device of second embodiment of the invention;

Fig. 3 is the overall construction drawing of the positive VR of semiconductor device formation;

Fig. 4 is the profile of first embodiment of the reference voltage circuit that constitutes of semiconductor device of the present invention;

Fig. 5 is the profile of second embodiment of the reference voltage circuit that constitutes of semiconductor device of the present invention;

Fig. 6 to 11 is respectively the instance graph of the reference voltage circuit of semiconductor device formation;

Figure 12 to 21 is respectively a profile of showing the method for the cmos semiconductor device of making first embodiment of the invention;

Figure 22 is the profile of showing by the cmos semiconductor device of third embodiment of the invention;

Figure 23 to 32 is respectively the profile of first embodiment of method that show to make the cmos semiconductor device of third embodiment of the invention;

Figure 33 and 34 is respectively the profile of second embodiment of method that show to make the cmos semiconductor device of third embodiment of the invention;

Figure 35 is the profile by the cmos semiconductor device of fourth embodiment of the invention;

Figure 36 to 42 is respectively the profile of first embodiment of method that show to make the cmos semiconductor device of fourth embodiment of the invention;

Figure 43 and 44 is respectively the profile of second embodiment of method that show to make the cmos semiconductor device of fourth embodiment of the invention;

Figure 45 is the profile by the cmos semiconductor device of fifth embodiment of the invention;

Figure 46 to 57 is respectively a profile of showing the method for the cmos semiconductor device of making fifth embodiment of the invention;

Figure 58 is the profile by the cmos semiconductor device of sixth embodiment of the invention;

Figure 59 to 63 is respectively the profile of first embodiment of method that show to make the cmos semiconductor device of sixth embodiment of the invention;

Figure 64 to 66 is respectively the profile of second embodiment of method that show to make the cmos semiconductor device of sixth embodiment of the invention;

Figure 67 is the profile of showing by the cmos semiconductor device of seventh embodiment of the invention;

Figure 68 is the profile of showing by the cmos semiconductor device of eighth embodiment of the invention;

Figure 69 to 74 is respectively the profile of first embodiment of method that show to make the cmos semiconductor device of eighth embodiment of the invention;

Figure 75 and 76 is respectively the profile of second embodiment of method that show to make the cmos semiconductor device of eighth embodiment of the invention;

Figure 77 is the profile of showing by the cmos semiconductor device of ninth embodiment of the invention;

Figure 78 to 82 is respectively a profile of showing the method for the cmos semiconductor device of making ninth embodiment of the invention;

Figure 83 is the profile by the cmos semiconductor device of tenth embodiment of the invention;

Figure 84 is a profile of showing the method for the cmos semiconductor device of making tenth embodiment of the invention;

Figure 85 is the profile by the cmos semiconductor device of eleventh embodiment of the invention;

Figure 86 is the profile by the cmos semiconductor device of twelveth embodiment of the invention;

Figure 87 is the profile by the cmos semiconductor device of thriteenth embodiment of the invention;

Figure 88 is the profile by the cmos semiconductor device of fourteenth embodiment of the invention;

Figure 89 to 91 is respectively the profile of conventional cmos semiconductor device.

DETAILED DESCRIPTION OF THE PREFERRED

Hereinafter with reference to the description of drawings embodiments of the invention.

Fig. 1 is the profile by an embodiment of cmos semiconductor device of the present invention.The CMOS that this cmos semiconductor device is formed by NMOS 113 that forms on the P type semiconductor substrate 101 and PMOS 112, P-resistor (P-resistor) 114 and N-resistor (N-resistor) 115 constitute.In NMOS113, grid forms with P+ polysilicon (P+polycrystalline silicon) 107, and source electrode and drain electrode have so-called single drain electrode structure; In PMOS 112, grid is formed on the N well region 102 and by P+ polysilicon 107 and forms, and source electrode and drain electrode have single drain electrode structure.P-resistor 114 and N-resistor 115 are formed on the field insulating membrane 106, are used to cut apart the bleeder circuit of voltage or the CR circuit of setting-up time constant.The P+ polysilicon 107 that forms grid preferably has as far as possible little resistance value, and therefore, containing concentration is 1 * 10 ¹⁹Atom/cm ³Or higher acceptor impurity, as B or BF ₂The polysilicon layer that resistor 114,115 usefulness are identical with the grid of CMOS forms.

Among the PMOS 112, grid is a P+ polysilicon 107, and therefore, according to the relation of the work function of N trap 102 and grid, the raceway groove of E type PMOS is a surface channel.In the surface channel PMOS, threshold voltage settings is-0.5V or bigger not cause the obvious change of subthreshold value (sub-threshold) coefficient bad.Therefore, low-work voltage and low-power consumption are possible.

On the other hand, among the NMOS 113, the relation of the grid that constitutes according to P+ polysilicon 107 and the work function of P type semiconductor substrate 101, E type NMOS raceway groove is a buried channel.The little arsenic of diffusion coefficient is as donor impurity, at threshold setting is to be used for threshold value control under the situation of predetermined value, and therefore, raceway groove is extremely shallow buried channel.Therefore, E type PMOS with dark buried channel compares with the grid that has the N+ polysilicon to form, the subthreshold value that can obviously suppress among the E type NMOS becomes bad and the leakage current increase, dark buried channel requires with the acceptor impurity of the boron of big diffusion coefficient as threshold value control arranged, and even be little value in threshold voltage settings, for example 0.5V or more hour still needs big ion and injects the projection scope.

As mentioned above, should be understood that by among the CMOS of the present invention that grid is a P+ polysilicon one pole, is that the CMOS of N+ polysilicon electrode compares with the grid of routine, and aspect low-work voltage and low-power consumption, the present invention is a kind of otherwise effective technique.

Resistor of P-shown in Fig. 1 114 and N-resistor 115.But, consider the characteristic of these resistors and the performance of product requirement, in order to reduce number of process steps and to reduce cost, one of P-resistor 114 or N-resistor 115 can only be installed.

Fig. 2 is the profile by second embodiment of cmos semiconductor device of the present invention.

P+ polysilicon one pole CMOS structure is identical with structure embodiment illustrated in fig. 1, and at aspects such as low-work voltage, low-power consumption, low costs same effect is arranged.But second embodiment and difference embodiment illustrated in fig. 1 are that the resistor that polysilicon constitutes is P+ resistor 116 and the N+ resistor 117 that has than high impurity concentration and small resistor value.P-resistor in embodiment illustrated in fig. 1 or N-resistor are that effectively they have higher film (thin layer) resistance value, and wherein certain accuracy is very important in the resistor circuit such as bleeder circuit.But, at the very important resistor of absolute value precision or require in the little resistor of temperature coefficient, as being used for the CR circuit of setting-up time constant, high impurity concentration and less resistance value can be improved absolute value precision and temperature coefficient.

By in the forming process of the source electrode of NMOS and PMOS and drain electrode, giving polysilicon doping simultaneously, can form P+ resistor 116 and N+ resistor 117.Under this situation, for P+ resistor 116, concentration is about 1 * 10 ¹⁹Atom/cm ³Or higher B or BF ₂As impurity, thin-film electro resistance scope be hundreds of Ω/mouth to 1K Ω/mouth, the temperature coefficient scope is hundreds of ppm/ ℃ to 1000ppm/ ℃.For N+ resistor 117, concentration is 1 * 10 ¹⁹Atom/cm ³Or higher phosphorus or arsenic is as impurity, thin-film electro resistance scope be 100 Ω/mouths to hundreds of Ω/mouth, temperature coefficient is that hundreds of is to 1000ppm/ ℃.Fig. 2 shows N+ resistor 117 and P+ resistance value device 116.But, consider, to reduce cost the characteristic of desired characteristic of semiconductor device and resistor that one of these two resistors just can constitute semiconductor device in order to reduce the quantity of processing step.

Afterwards, illustrate that with reference to Fig. 3 the present invention is used for the concrete effect under the situation of actual product.Fig. 3 is the overall construction drawing of the positive VR of semiconductor device formation.The bleeder circuit 157 that VR is made up of reference voltage circuit 150, error amplifier 151, PMOS output element 152 and resistor 156 constitutes, it is the semiconductor device with such function: even give input 153 input free voltages, it exports the current value of constant voltage and requirement also can for output 155 all the time.

In recent years, need obtain the VR that mancarried device is particularly used from the market, to realize following performance: low input, low-power consumption, even big electric current output, high output voltage precision, low cost, miniaturization etc. also should be arranged under the little situation of I/O potential difference.Especially, override needs the low and miniaturization of cost.For above requirement, by the present invention, error amplifier, PMOS output element and reference voltage circuit constitute with the CMOS of the low low threshold voltage of cost, and bleeder circuit is low with cost, resistance value is big and high-precision P-resistor constitutes.Therefore can realize low-work voltage, low-power consumption and high output voltage precision.

To specifically describe the remarkable result that structure of the present invention is brought for the low cost of override requirement below, promptly to reducing the remarkable result that chip size or miniaturization bring.

The output current of VR is that tens mA are to hundreds of mA.This depends on the driving force of PMOS output element fully, and according to specific product, the PMOS output element account for chip area roughly half.Therefore, how many sizes of PMOS output element can reduce, and is the key factor of the low and miniaturization of decision cost.

On the other hand, as mentioned above, input voltage is the requirement of low-voltage and is strong to market demands that the output of big electric current is arranged under the little situation of I/O potential difference.This shows the big electric current in the unsaturated operating state, and wherein, the voltage that adds to grid in the PMOS output element is little, and the voltage between source electrode and the drain electrode is little.

The drain current of MOS transistor is expressed as in the unsaturated operating state:

Id=(μ .cox.W/L) * (Vgs-Vth)-1/2.Vds} * Vds...... formula (1)

Id in the formula: drain current; μ: mobility; Cox: the electric capacity of gate insulating film; W: channel width; L: channel length; Vgs: the voltage between grid and the source electrode; Vth: threshold voltage; Vds: the voltage between drain electrode and the source electrode.

For under the situation that does not increase surface area, even also enough big drain current can be reached,, channel length and Vth must be reduced by formula (1) with little Vgs and Vds.

At P type one pole (monopole) is in the CMOS structure of grid, can reduce threshold voltage, reduces channel length, the leakage current in the time of suppressing simultaneously to end.Therefore, should be understood that the CMOS structure is a utmost point effective and efficient manner to reducing cost and making above-mentioned VR miniaturization.

As the advantage of P type one pole grid CMOS structure of the present invention, the temperature characterisitic of reference voltage circuit can be improved among the VR.Following with reference to description of drawings.

Fig. 4 is the profile of first embodiment of the reference voltage circuit of showing that semiconductor device of the present invention constitutes.In the present embodiment, show the reference voltage circuit of Fig. 6, wherein, E type NMOS and D type NMOS are connected in series.

Use N type semiconductor substrate 118, and, E type NMOS 125 and D type NMOS 126 are set respectively in P type trap 119 for fear of reverse bias.

With the P+ polysilicon of wiring metal (not shown) short circuit as the drain and gate of E type NMOS 125.And, be shown in the source electrode of E type NMOS and this example GND () the low-voltage supply side 122 of line is connected.

As the source electrode of D type NMOS 126 and the P+ polysilicon of grid, and the P+ polysilicon is connected with high voltage supply side 123 with the short circuit of wiring metal (not shown).

Among the present invention, the P+ polysilicon is used for E type NMOS 125 and D type NMOS 126.But, when the P of films of opposite conductivity type is used as the grid of NMOS, is under the situation of predetermined value can not carry out so-called channel doping fully with ion implantation with the threshold voltage settings of NMOS, threshold voltage is generally 1.0V or higher, although threshold voltage is relevant with P trap (P-well) concentration with the thickness of gate oxidation films.Under many circumstances, the about 0.7V of threshold voltage of E type NMOS for setting this threshold voltage, uses the channel doping method in the NMOS with P type grid, and arsenic or phosphorus are introduced in the semiconductor as opposite impurity.As a result, the raceway groove of MOS transistor is formed in the part of least concentration, and E type NMOS 125 is buried channels.In addition, the threshold voltage of D type NMOS is about-0.3V usually, for setting this threshold voltage, uses the channel doping method, and phosphorus or arsenic are introduced as opposite impurity.Therefore, D type NMOS 126 also is a buried channel.Therefore, by utilizing P type grid, E type NMOS and D type NMOS all are buried channels.

Because E type NMOS and D type NMOS all are buried channels, therefore, with D type NMOS with N type grid is that buried channel and E type NMOS are that the regular situation of surface channel is compared, and variations in threshold voltage degree or the mutual conductance of MOS of the present invention can be accomplished unanimity with the variation of temperature degree.As a result, can make the temperature characterisitic of reference voltage circuit smooth.

Fig. 5 is the profile of second embodiment of the reference voltage circuit of showing that semiconductor device of the present invention constitutes.So-called multilayer (Polycide) structure, that is, the laminated construction of refractory metal silicide (as tungsten silicide or molybdenum silicide) and polysilicon is as grid, so that grid has low resistance.Described with reference to Figure 4, do the lower floor of grid, make reference voltage circuit that smooth temperature characterisitic be arranged with the P+ polysilicon.In addition,, compare, embodiment illustrated in fig. 5ly can make high-speed high performance integrated circuit with embodiment illustrated in fig. 4 because the resistance of grid is little.

The present invention is used for reference voltage circuit, the reference voltage circuit that is suitable for output LOW voltage of Fig. 8 and the reference voltage circuit that is used to avoid using the reverse bias effect under the P type semiconductor substrate situation among Fig. 9 to the current potential output constant voltage of high voltage supply side of being used among reference voltage circuit that following reference voltage circuit can reach same effect: Fig. 6, Fig. 7.

In the circuit example shown in Figure 9, E type PMOS is as load elements.The grid of this PMOS is set at the P+ type as the grid of NMOS, and thus, PMOS is a surface channel.Therefore, compare,, also can suppress the leakage current of PMOS even threshold setting must be lower with the situation of buried channel.Therefore, can make reference voltage circuit with low-work voltage and low-power consumption.In addition, make and become simple and easy, NMOS and PMOS all use P+ type (P+type) grid, can reduce cost.

In addition, the circuit that the present invention is used for Figure 10 or 11 can reach same effect, and P type grid is used for E type NMOS and two D type NMOS in Figure 10 or 11, so that can stablize output reference voltage, and circuit is not superimposed upon the noise jamming on the high voltage supply side.

The effect of P type one pole grid has been described with E type NMOS and D type NMOS as mentioned above.But, for reference voltage circuit of the present invention, even use the structure of the reference voltage circuit of the E type PMOS of opposite polarity N+ type grid and D type PMOS, also as in NMOS, reference voltage circuit has gratifying temperature characterisitic.

In addition, be used to avoid the structure of reverse bias effect and circuit to be described with reference to Fig. 4 to 11 pair.But needless to say, P type one pole grid CMOS of the present invention is used for adding back-biased reference voltage circuit jointly wherein for E type MOS transistor and D type MOS transistor, also can make reference voltage circuit that smooth temperature characterisitic is arranged.

In addition, by P+ one pole grid CMOS structure of the present invention, owing to there is the D type threshold voltage variation of conventional N+ polysilicon gate construction big, therefore, the practicality of also failing of the E/D type reference voltage circuit of PMOS.Thereby, can select NMOS and PMOS in the E/D type reference voltage circuit, and the present invention also has the advantage of the degree of freedom that has increased circuit design.

Illustrated that more than the present invention is a effect in the reference voltage circuit in the element circuitry of VR and VR.In addition, will illustrate that below SWR neutralization that the present invention is used for installing high output element is used for the VD of an urgent demand low-work voltage, low-power consumption, low cost and miniaturization, can obtain the remarkable result as in VR.

Hereinafter with reference to the method for description of drawings manufacturing by the cmos semiconductor device of first embodiment of the invention.

Among Figure 12, after forming N trap 102 on the P type semiconductor substrate 101, use the field insulating membrane 106 of LOCOS method formation, and optionally mix threshold value control impurity with ion implantation in the channel region for each NMOS and PMOS as element isolation zone.Afterwards, by for example thermal oxidation formation gate insulating film 105 in electric furnace, afterwards, deposit polysilicon 131 on it.

In the present embodiment, show single N well structure with the P type semiconductor substrate.By noise testing and customer requirements,, form the P trap with the N type semiconductor substrate making under the Vdd end situation identical with the current potential of installation sheet.Under this situation, can obtain and similar effect under the situation of P type semiconductor substrate N trap method, can realize low-work voltage, low-power consumption and low cost by CMOS of the present invention.

In addition, to be formed in the semiconductor of concentration much at one at NMOS and PMOS and consider again under the situation of balance of the parasitic capacitance of two MOS devices or minimum length L, promptly can use under the situation of two trap methods, also can reach effect by CMOS of the present invention, can realize low-work voltage, low-power consumption and low cost, and needn't be considered as the conduction type of raw-material Semiconductor substrate, promptly no matter Semiconductor substrate is P type or N type, can both reach the effect of CMOS.

Figure 12 shows the LOCOS method that is used for element separation.But, in order to reduce isolated area,, also can reach effect by CMOS of the present invention with not shown shallow trench isolation (STI), can realize low-work voltage, low-power consumption and low cost.Usually select LOCOS method or STI method for use according to maximum working voltage.Maximum working voltage is under the situation of several volts, considers that area preferably selects the STI method for use.On the other hand, under the situation of maximum working voltage greater than several volts, the metallization processes that conforms to the principle of simplicity considers preferably to select for use the LOCOS method.

As mentioned above, in order to control threshold value, channel region is mixed with ion implantation.Because the conduction type of grid is the P+ polysilicon, be used as the phosphorus of donor impurity or arsenic impurity as E type NMOS and D type NMOS.As mentioned above, the surface channel type is well suited for low threshold value, therefore, and the most handy arsenic that big diffusion coefficient is arranged.Donor impurity also is used for E type PMOS, but acceptor impurity B or BF ₂Be used for D type PMOS.

Under the D type PMOS situation, consider that threshold property surface channel type is the most desirable, therefore, use BF usually ₂, it can keep the Impurity Distribution after ion injects is shallow.Although impurity dose is relevant with the threshold size of requirement, the scope of impurity dose is usually 10 ¹¹Atom/cm ²To 10 ¹²/ cm ²

Decompose silane gas with the CVD method and on oxide-film, form polysilicon.Consider the most handy thick film from the low resistance of grid or wiring.But, as mentioned above, owing to also form resistor with same rete, therefore for the most handy film of high resistance.Consider the corrosion selection ratio of composition throughput, bottom gate oxidation films and the corrosion selection ratio of polysilicon, the thickness scope normally 2000 (dust) to 6000 .

Afterwards, as shown in figure 13, to photoresist 132 compositions, so as with photoetching process at the part opening that will form N type resistor, and donor impurity phosphorus or arsenic-selective ground are introduced in the polysilicon with ion implantation.

Described as follows, inject the acceptor impurity of low concentration in step subsequently, for the whole surface ion of polysilicon.But in this step, conduction type also is the N type after ion injects even impurity dose is set at.Impurity dose scope normally 10 ¹⁴To 10 ¹⁵Atom/cm ², the net concentration scope is 1 * 10 approximately ¹⁴To 9 * 10 ¹⁸Atom/cm ³Thin-film electro resistance scope is that a few k Ω/mouth is to tens k Ω/mouth.For the current drain that is caused by resistance in the bleeder circuit is set at is μ A or littler at least, must be located at the thin-film electro resistance in the above-mentioned scope.

In addition, according to the requirement of circuit or product, there is the high-resistance situation that does not need N type polysilicon.Under this situation, can save step shown in Figure 13.

Afterwards, photoresist is stripped from.Afterwards, as shown in figure 14, photoresist 132 compositions so that will form the part opening of P+ grid and wiring with photoetching process, and with ion implantation as the BF of acceptor impurity ₂Optionally introduce in the polysilicon.Because grid and wiring preferably have as far as possible little resistance, so the condition that ion injects is: concentration is 1 * 10 ¹⁹Atom/cm ³Or higher, impurity dose is 1 * 10 ¹⁵Atom/cm ³Or it is higher.

And, although not shown, below form the P+ multi-crystal silicon area among Figure 14.That is, after the step of Figure 13, peel off photoresist, and on polysilicon, form oxide-film with the CVD method, the oxide-film composition so that after the heat treatment by photoetching process with the wet corrosion of HF solution, form the part opening of P+ grid and wiring.Afterwards, after photoresist is peeled off, in electric furnace, carry out pre-deposited and drive into (drive-in).Perhaps, after molecular layer mixes, heat-treat, remove oxide-film.This situation requires to form oxide-film and carry out corrosion treatment, therefore, compares with the situation that ion implantation forms the P+ multi-crystal silicon area with make mask with the photoresist among Figure 14, and the many shortcomings of number of process steps are arranged.But it is little that the advantage of above-mentioned situation is a resistance, because compare with ion implantation, can make the concentration of acceptor impurity obviously become big.Usually, adopt photoetching process and ion implantation to form the P+ multi-crystal silicon area and can make impurity concentration be convenient to control, and simple.

Afterwards, after photoresist 132 is peeled off, for forming P type resistor area shown in Figure 15, use ion implantation, B or BF as acceptor impurity ₂Introduce in the polysilicon.Usually the impurity dose scope is 10 ¹⁴To 10 ¹⁵Atom/cm ², the net concentration scope is 1 * 10 approximately ¹⁴To 9 * 10 ¹⁸Atom/cm ³The thin-film electro resistance is that a few k Ω/mouth is to tens k Ω/mouth.As under the situation of N type resistor, be μ A or littler at least for the current drain that is caused by resistance in the bleeder circuit is set at, must be located at the thin-film electro resistance in the above-mentioned scope.

And, also as under the situation of N type resistor,, there is the high-resistance situation that does not need P type polysilicon according to circuit or product requirement.Can save the step among Figure 15 in this case.

Through the step shown in Figure 13 to 15, in polysilicon, form N type resistor area, P type resistor area and P+ district (P+region).But, needn't adopt this sequence of steps.Step shown in available Figure 13 to 15 forms above-mentioned 3 districts in any order.

Afterwards, as shown in figure 16, form first dielectric film 134 with the CVD method on polysilicon, heat-treat in electric furnace in inert gas atmosphere, according to circumstances inert gas is for example nitrogen or argon gas.

First dielectric film is provided as mask, is entering in the P+ grid with the source electrode of self-aligned manner formation NMOS and the process donor impurity of drain electrode after being used for preventing.In order to make first dielectric film that the mask function be arranged, the acceleration of injecting at the forming process intermediate ion of the source electrode of NMOS and drain electrode can be less than 100Kev.Therefore, even consider the maximum magnitude of ion, the thickness of 1000 to 2000 also is enough to play the effect of preventing.Make first insulating film material with oxide-film or nitride film.As described below, in step subsequently, must peel off first dielectric film on the resistor, and under many circumstances,, use the oxide-film that can use HF solution wet corrosion in order to simplify technology and the damage that prevents resistor.

Afterwards, as shown in figure 17, give first dielectric film and polysilicon composition, to form grid, wiring and resistor with photoetching process and etch.

Form (grid, wiring and resistor) with two kinds of methods.A kind of method is, give the photoresist composition with photoetching process after, make mask corrosion first dielectric film with photoresist, afterwards, the corrosion polysilicon stays photoresist simultaneously, removes photoresist then.Other method is, give the photoresist composition with photoetching process after, make mask corrosion first dielectric film with photoresist, afterwards, peel off photoresist, make the mask corrosion polysilicon with first dielectric film then.

Because precision prescribed is with anisotropic dry corrosion treatment grid or resistor.In corrosion, the sidewall protecting film effect of the product that forms with photoresist realizes anisotropic etch, and therefore, usually, the dry corrosion polysilicon stays photoresist simultaneously.

First dielectric film is under the situation of oxide-film, and available wet corrosion or dry corrosion are handled.But, consider the most handy dry corrosion from precision.And be under the situation of nitride film at first dielectric film, the composition of making mask with photoresist does not have suitable corrosive agent, so corrosion is limited to dry corrosion.But, under the situation of nitride film,, therefore the advantage of corroding is continuously arranged in identical etching apparatus (etcher) because the corrosion rate of the corrosion rate of dry corrosion and polysilicon is roughly the same.

Afterwards, as shown in figure 18, to photoresist 132 compositions, grid or wiring that photoresist 132 is covered except that resistor are regional with photoetching process, and with first dielectric film on the erosion removal resistor.

Under this situation, owing to require, so the wet corrosion that wherein only carries out corrosion treatment preferably with chemical reaction not because of corrosion damages resistor.Thereby, as mentioned above, can carry out the suitable material of making first dielectric film 134 of oxide-film of wet corrosion with HF solution.About this point, because nitride film does not have suitable corrosive agent (wherein, can make mask material with photoresist), so nitride film has shortcoming.But, because field insulating membrane is an oxide-film under the situation that a lot of first dielectric films are oxide-films, so in this step, must reduce the thickness of field insulating membrane.

Afterwards, after photoresist is peeled off, as shown in figure 19, with photoetching process to photoresist 132 compositions, at the part opening of NMOS that will contact and N type resistor with wiring metal.Afterwards, the donor impurity of for example phosphorus or arsenic and so on is introduced P type substrate and N type resistor with high concentration, form corresponding to the source electrode of NMOS and the N+ district 103 and the N+ multi-crystal silicon area 109 of drain electrode with ion implantation.

Usually with there being the arsenic of little diffusion coefficient to make shallow-source electrode and shallow drain electrode as impurity.In order to obtain alap resistance, impurity dose is 1 * 10 ¹⁵Atom/cm ²Or higher, under this situation, concentration is 1 * 10 ¹⁹Atom/cm ³Or it is higher.

In addition, under this situation, because the grid of NMOS is provided with first dielectric film, the alms giver can not enter the P+ grid of NMOS.Thus, work function and resistance value are constant.

Afterwards, after photoresist is peeled off, if desired, heat-treat activator impurity.Afterwards, as shown in figure 20, with photoetching process to photoresist 132 compositions, at the part opening of PMOS that will contact and P type resistor with wiring metal.Afterwards, such as BF ₂Or the acceptor impurity of B and so on introduces in N trap and the P type resistor with high concentration, forms corresponding to the source electrode of PMOS and the P+ district 104 and the P+ multi-crystal silicon area 108 of drain electrode.Owing to should do lowly as far as possible as resistance among the NMOS, so impurity dose is 1 * 10 ¹⁵Atom/cm ²Or higher, the concentration under this situation is 1 * 10 ¹⁹Atom/cm ³Or it is higher.

Afterwards, after photoresist is peeled off, as shown in figure 21,, and heat-treat and make intermediate insulating film smooth with CVD method deposit intermediate insulating film 135.

Intermediate insulating film has double-layer structure, and wherein, lower floor is plain silicate glass (NSG) film or nitride film, and the upper strata is phosphosilicate glass (PSG) film or boron phosphorus silicate glass (BPSG) film.PSG and BPSG are used for making the smooth effect of glass flows more effective by heat treatment.In addition, NSG or the nitride film as lower floor is used for preventing that advancing the polyresistor neutralization in the heat treatment process diffusion of impurities avoids the resistance value fluctuation.Thickness is that 1000 or bigger lower floor have and be enough to prevent the ability that spreads.

Handle through hot-leveling shown in Figure 21, finish acceptor impurity and should so limit: make boron not advance channel region from the P+ gate diffusions as acceptor impurity with the required heat of high concentration introducing polysilicon.Although heat treatment is relevant with the thickness of gate insulating film, heat treatment is carried out dozens of minutes under 800 ℃ to 900 ℃ in electric furnace, and under the situation of rapid thermal annealing (RTA), heat treatment handled for tens seconds at 1000 ℃ to 1100 ℃.

In the step subsequently, in CMOS technology, form contact hole and wiring metal.

As mentioned above, by the step of Figure 12 to Figure 21, can make the structure of the cmos semiconductor device of first embodiment of the invention shown in Figure 1.

In addition, make the cmos semiconductor device of second embodiment of the invention as follows.Promptly, step by Figure 12 to Figure 21, in source electrode shown in Figure 19 and 20 and drain electrode, introduce in the step of impurity, under the situation of N+ resistor (N+resistor), there is the impurity of same concentrations to introduce whole resistor area with source electrode and the drain electrode of NMOS, and under the situation of P+ resistor (P+resistor), have the impurity of same concentrations to introduce whole resistor area with the source electrode of PMOS and drain electrode.Do not need any additional step.

Figure 22 is the profile of the cmos semiconductor device of third embodiment of the invention.

With the difference of cmos semiconductor device of the present invention illustrated in figures 1 and 2 be, grid has so-called sandwich construction, it is the laminated construction of refractory metal silicide 127 and P+ polysilicon 107, and the resistor that is formed on the field insulating membrane 106 is film P-resistor 138 and film N-resistor 139, and these resistors are that the thinner polysilicon of polysilicon of using the lower floor than grid to use is made.

Consider at a high speed, in order to make grid and wiring alap resistance is arranged, sandwich construction is to be 1 * 10 containing concentration ¹⁹Atom/cm ³Or higher B or BF ₂And so on the P+ polysilicon 107 of acceptor impurity on establish refractory metal silicide 127.Compare with tens Ω/mouths under the single level polysilicon situation, the thin-film electro resistance can be made little extremely several Ω/mouth to 10 Ω/mouths.

The polysilicon that resistor 138 and 139 usefulness are so thin forms, even make the thin-film electro resistance set to such an extent that highly also can be enough to keep absolute value and resistance ratio precision.

The structure of the cmos semiconductor device of the 3rd embodiment is identical with the structure of P+ grid cmos semiconductor device illustrated in figures 1 and 2, and except that grid structure and thin film resistor, other is basis of the present invention.Therefore, the effect of low-work voltage and low-power consumption is identical.

The method of the cmos semiconductor device of third embodiment of the invention is made in explanation below with reference to accompanying drawings.

Show following state among Figure 23.The same in the step shown in the image pattern 12, behind the formation N trap 102, form field insulating membrane 106, and the channel region of using for the threshold value control of each NMOS and PMOS with ion implantation mixes optionally in the P type semiconductor substrate 101 as element isolation zone.After this, form gate insulating film and deposit first polysilicon 131.

Polysilicon 131 is lower floors of the grid of sandwich construction, and therefore, the situation that forms grid with single level polysilicon is compared, and requires polysilicon 131 to approach.

Polysilicon 131 requires that certain thickness is arranged, because if polysilicon 131 (too) is thin, can damage Semiconductor substrate or gate insulating film in the deposition process of formation refractory metal silicide subsequently on polysilicon.Consider the composition throughput, with the corrosion selection ratio of bottom gate oxidation films and the corrosion selection ratio of sandwich construction, the thickness scope is 1000 to 4000 normally.

Afterwards, as shown in figure 24, BF ₂Introduce first polysilicon 131 as acceptor impurity with ion implantation, to form P+ polysilicon 133.

The condition that grid carries out the ion injection is: impurity concentration is 1 * 10 ¹⁹Atom/cm ³Or higher, impurity dose is 1 * 10 ¹⁵Atom/cm ²Or higher, exhaust (depletion) to prevent the gate electrode side limit.

By the method for driving in pre-deposited and the electric furnace or carry out heat treatment step after molecular layer mixes, acceptor impurity is introduced first polysilicon 131.

The advantage of these methods is to exhaust because with ion implantation mutually specific energy improve acceptor impurity concentration significantly.But in these methods, concentration is controlled poor, and can diffuse into raceway groove through gate insulation layer from grid as the B of acceptor impurity, thereby because the heat treatment in the subsequent step causes the threshold voltage fluctuation.Therefore, ion injection formation method is safe.

In addition, can obtain the structure identical, wherein, when first polysilicon 131 shown in Figure 23 forms, introduce acceptor impurity in order to simplify step with structure shown in Figure 24 with doping CVD method.Under this situation, in order to obtain low resistance, impurity concentration is set at 1 * 10 ¹⁹Atom/cm ³Or it is higher.

Afterwards, as shown in figure 25, the deposit refractory metal silicide 127 on P+ polysilicon 133 with sputtering method or CVD method.And, with CVD method deposit dielectric film 134 on refractory metal silicide.

Make refractory metal silicide with one of molybdenum silicide, tungsten silicide, titanium silicide and platinum silicide, the thickness of refractory metal silicide is 500 to 2500 .Damage although worry to produce, consider, form refractory metal silicide with sputtering method usually from the cementability of refractory metal silicide and polysilicon.Compare with the grid that constitutes with single level polysilicon and the tens Ω/mouth resistance value of wiring, refractory metal silicide can make the thin-film electro resistance of grid and wiring significantly drop to several Ω/mouth to 10 Ω/mouths.Therefore, improved the function of semiconductor article.

With the described identical reason of Figure 16, establish dielectric film 134 and make mask, be used to prevent that donor impurity from entering grid.Oxide-film or nitride film are as the material of dielectric film 134, and thickness is 1000 to 2000 .If desired, after dielectric film 134 deposits, about 30 minutes of about 900 ℃ of heat treatments.

Below, as shown in figure 26,, give dielectric film 134, refractory metal silicide 127 and P+ polysilicon 133 compositions with photoetching process and etch, form grid and wiring.

Form (grid, wiring) with two kinds of methods.A kind of method is, give the photoresist composition with photoetching process after, make mask corrosion dielectric film 134 with photoresist, corrosion refractory metal silicide 127 and P+ polysilicon 133 stay photoresist simultaneously, afterwards, remove photoresist.Other method is, with photoetching process to the photoresist composition after, make mask corrosion dielectric film 134 with photoresist, peel off photoresist, afterwards, make mask corrosion refractory metal silicide 127 and P+ polysilicon 133 with dielectric film 134.

Because precision prescribed is with anisotropic dry corrosion treatment grid or resistor.In corrosion, the sidewall protecting film effect of the product that forms with photoresist realizes anisotropic etch, and therefore, usually, dry corrosion refractory metal silicide and polysilicon stay photoresist simultaneously.

In the corrosion of the multilayer film of multiple material, detect etching of upper strata, and carry out the corrosion of multilayer film by the requirement change gas by etching apparatus itself by material or when needing with end point determination mechanism.

Below, as shown in figure 27, after dielectric film 137 forms, deposition film polysilicon 136.

Dielectric film for example is the oxide-film of the thick hundreds of that forms with thermal oxidation method or with the oxide-film of the thick hundreds of of CVD method formation.

Forming under the situation of grid and wiring, use CVD method deposition film polysilicon 136 equally with polysilicon.But, deposition film polysilicon 136 under low deposition temperature is because of its thickness is 500 to 2000 , thinner than the polysilicon that is used to constitute grid and wiring.In addition, available sputtering method deposited film in this step.

The polysilicon thinner than the polysilicon that constitutes grid and wiring with its thickness forms resistor.Therefore, even the thin-film electro resistance of resistor is set at up to a few k Ω/mouth to tens k Ω/mouth, also be enough to keep the precision of resistance value.

Below as shown in figure 28, with photoetching process to photoresist 132 compositions, at the part opening that will constitute N type resistor, and with ion implantation as in the phosphorus of donor impurity or the arsenic-selective ground introducing membrane polysilicon 136.

The situation that may exist is in the next step of Miao Shuing, to inject the whole surface of acceptor impurity being introduced membrane polysilicon with low concentration by ion in the back.But, impurity dose be set in addition ion inject the back conduction type also be N type and impurity concentration within the specific limits.Impurity dose scope normally 10 ¹⁴To 10 ¹⁵Atom/cm ², the net concentration scope is 1 * 10 approximately ¹⁴To 9 * 10 ¹⁸Atom/cm ³The thin-film electro resistance is several to tens K Ω/mouth.For the current loss that causes owing to resistance in the bleeder circuit is set in μ A or lower at least, must be set at above-mentioned value to the thin-film electro resistance.

In addition, have such situation: according to the requirement of circuit or product, N type polysilicon needn't have high resistance.Under this situation, can save the step among Figure 28.

Afterwards, after photoresist 132 is peeled off, as shown in figure 29, use ion implantation B or BF as acceptor impurity ₂Introduce in the membrane polysilicon 136, form P type resistor area.

Impurity dose scope normally 10 ¹⁴To 10 ¹⁵Atom/cm ², the net concentration scope is 1 * 10 approximately ¹⁴To 9 * 10 ¹⁸Atom/cm ³。The thin-film electro resistance is several to tens k Ω/mouth.As in N type resistor, be set in μ A or lower at least in order to make the power consumption that causes by resistance in the bleeder circuit, the thin-film electro resistance should be set at above-mentioned value.

In addition, have such situation: according to the requirement of circuit and product, P type polysilicon needn't have high resistance.Under this situation, can save step shown in Figure 29.

By step shown in Figure 28 and 29, in membrane polysilicon, form N type resistor area and P type resistor area.But, needn't adopt this sequence of steps.By the exchange of step shown in Figure 28 and 29, can form N type resistor area and P type resistor area equally.

Afterwards, as shown in figure 30, use photoetching process and etch, form resistor the second polysilicon composition.

Therefore the processing requirements precision of resistor is handled with the anisotropic dry etch.

Subsequently, after photoresist is peeled off, as shown in figure 31, give photoresist 132 compositions with photoetching process, at the part opening of NMOS that will contact and N type resistor with wiring metal.Then, with high concentration donor impurity such as phosphorus or arsenic are introduced P type substrate and N type resistor with ion implantation, and form corresponding to the source electrode of NMOS and the N+ district 103 and the N+ multi-crystal silicon area 109 of drain electrode.

Usually make impurity with the little arsenic of diffusion coefficient, make shallow-source electrode and shallow drain electrode.For making resistance low as far as possible, impurity dose is 1 * 10 ¹⁵Atom/cm ³Or higher, and concentration is 1 * 10 under this situation ¹⁹Atom/cm ³Or it is higher.

In addition, under this situation, owing to

dielectric film

134 and 137 is formed on the grid of NMOS, so alms giver's (impurity) can not enter the grid of NMOS.Therefore work function and resistance value are constant.

And although not shown, in order to improve temperature coefficient, the N+ resistor that membrane polysilicon forms can form whole N+ resistor area and all be in high concentration.

Afterwards, after photoresist is peeled off, can heat-treat activator impurity if desired.After this, shown in figure 32, with photoetching process to photoresist 132 compositions, at the part opening of PMOS that will contact and P type resistor with wiring metal.Afterwards, use ion implantation acceptor impurity BF ₂Or B introduces N trap and P type resistor with high concentration, and forms corresponding to the source electrode of PMOS and the P+ district 104 and the P+ multi-crystal silicon area 108 of drain electrode.Because the resistance among the NMOS should be done lowly as far as possible, so impurity dose is 1 * 10 ¹⁵Atom/cm ³Or higher, and concentration is 1 * 10 under this situation ¹⁹Atom/cm ³Or it is higher.

In addition, in this step, as described in Figure 31, also can on whole zone, form the P+ resistor with high concentration.

After the above-mentioned steps, the same in the step shown in the image pattern 21, form intermediate insulating film 135.As a result, can be made into the structure of the cmos semiconductor device of third embodiment of the invention shown in Figure 22.

Second embodiment of the method for the cmos semiconductor device of making third embodiment of the invention below is described.

Among Figure 33, after step shown in Figure 23 and 24, with the refractory metal 140 of sputtering method deposit such as Co or Ti and so on P+ polysilicon 133.

The thickness range of Co and Ti is 100 to 500 .When using Co, can overlapping thickness tens to Ti or the TiN of hundreds of .

Afterwards, with rapid thermal treatment (RTP) for example,, make the refractory metal part silication that contacts with polysilicon 131 in 600 ℃ to 750 ℃ tens seconds to 1 of heat treatment minute.Afterwards, carry out tens seconds of RTP at 700 ℃ to 900 ℃.The state that obtains as shown in figure 34.

By with the described manufacture method of Figure 25 to 32 in identical step carry out subsequent step.As a result, make the structure of the cmos semiconductor device of the 3rd embodiment shown in Figure 22.

Figure 35 is the profile of the cmos semiconductor device of fourth embodiment of the invention.

This cmos semiconductor device is to use the NMOS 113 that lightly doped drain electrode (LDD) structure is arranged and the PMOS 112 that the LDD structure is arranged and P-resistor 114 and N-resistor 115 formations, wherein, the grid that is formed on the NMOS 113 on the P type semiconductor substrate 101 constitutes with P+ polysilicon 107, and its source electrode and drain electrode each have the N diffusion layer that is used for electric field tension and relaxation (relaxation); The grid that is formed on the PMOS 112 on the N well region 102 also constitutes with P+ polysilicon 107; P-resistor 114 and N-resistor 115 be formed on grid on the field insulating membrane 106 and use with one deck polysilicon and constitute.

The advantage of structure shown in Figure 35 is little and its reliability of its grid length, because MOS has the LDD structure.But except that above-mentioned advantage, the structure among Figure 35 is identical with the structure as the P+ grid cmos semiconductor device on basis of the present invention shown in Fig. 1,2 and 22.Therefore, the effect of low-work voltage and low-power consumption is identical.

The following method of making the cmos semiconductor device of fourth embodiment of the invention with reference to description of drawings.

Carry out with Figure 12 to 17 in identical step, form grid, wiring and resistor area.In the present embodiment, the lower floor in the laminated construction is a silicon oxide film, and the upper strata is a silicon nitride film, and this laminated construction is as the dielectric film 134 on the polysilicon.

Form silicon oxide film with polysilicon thermal oxidation or CVD method, form silicon nitride film with the CVD method.The total thickness of dielectric film 134 is 1000 to 3000 .The gross thickness of oxide-film and nitride film becomes to make dielectric film 134 to play the mask effect with the thickness setting of each tunic, prevent that donor impurity enters the P+ grid in the source electrode of NMOS and the forming process that drains, and in side isolation (this will be explained below) forms, do not expose as the oxide-film of dielectric film 134 lower floors.For example, silicon nitride thickness 2000 , silica thickness 1000 .

Lower floor at dielectric film 134 when using the oxide-film of CVD method formation, carries out close thermal behind the formation dielectric film 134 and handles.

During grid and resistor pattern form,, carry out corrosion as the dielectric film of the lamination of oxide-film and nitride film by detecting etch end point and between nitride film and oxide-film, changing gas.In addition, if desired, not only change gas, also can change etching apparatus itself, therefore can carry out to fault-free the corrosion of dielectric film 134.By selecting suitable gas and etching apparatus, similarly carry out polysilicon corrosion subsequently.

Carried out after the above-mentioned steps, as shown in figure 36, with photoetching process to photoresist 132 compositions, with the NMOS opening.Afterwards, with low concentration the donor impurity of phosphorus or arsenic and so on is introduced P type substrate with ion implantation, and form corresponding to the low concentration source electrode of NMOS and the N-district (N-regions) 142 of drain electrode.

The operating voltage of impurity concentration decision semiconductor product, but impurity dose is usually 10 ¹²To 10 ¹⁴Atom/cm ²Concentration range is 10 under this situation ¹⁶To 10 ¹⁸Atom/cm ³

Then, after removing photoresist, as shown in figure 37, with photoetching process to photoresist 132 compositions, with the PMOS opening.Afterwards, with ion implantation with low concentration B or BF ₂And so on acceptor impurity introduce the N trap, and form corresponding to the low concentration source electrode of PMOS and the P-district (P-regions) 143 of drain electrode.

Identical among impurity concentration and the NMOS, impurity dose is usually 10 ¹²To 10 ¹⁴Atom/cm ²Concentration range is 10 under this situation ¹⁶To 10 ¹⁸Atom/cm ³

Then, after removing photoresist, as shown in figure 38, on Semiconductor substrate, form the dielectric film 144 that will become later the side isolation with the CVD method.Under this situation, need so to form side and isolate: stay dielectric film 134 on the polysilicon as dielectric film.Therefore use silicon oxide film, it has with respect to the corrosion selection ratio as the silicon nitride film on dielectric film 134 upper stratas.Although the thickness of dielectric film is relevant with the electric field tension and relaxation degree of requirement, the thickness scope of dielectric film 144 is 2000 to 6000 normally.After dielectric film 144 deposits, can carry out the heat treatment of tight oxide-film etc.

Then, dielectric film 144 is carried out the anisotropy dry corrosion, thus on as the sidewall of the polysilicon of grid and form side on the sidewall of wiring and resistor (not shown) and isolate 141.Side is isolated 141 width decision etching condition, but is generally 0.2 μ m to 0.5 μ m.

Isolated 141 o'clock in the formation side, because dielectric film 144 is silicon oxide films, the upper strata of the dielectric film 134 on the polysilicon is silicon nitride films, therefore can be enough to the selection ratio that keeps big in anisotropic etch.Therefore, polysilicon does not need to expose in the corrosion.

In the present embodiment, the upper strata of the dielectric film 134 on the polysilicon is silicon nitride films, and the dielectric film 144 that is used to isolate is silicon oxide films.But,, can obtain identical structure when dielectric film 134 is silicon oxide film and the dielectric film 144 that is used to isolate when being silicon nitride film.

Afterwards, as shown in figure 40, to photoresist 132 compositions, grid and wiring that photoresist 132 is covered except that resistor are regional with photoetching process.Afterwards, the dielectric film 134 on the resistor is removed in corrosion.

Under this situation, resistor is worthless because of etching process damages.Therefore, in this example, remove silicon nitride film, and remove the silicon oxide film as dielectric film lower floor of direct resistor contact with the wet corrosion that only carries out chemical reaction as the upper strata of dielectric film 134 with dry corrosion.

Then, after removing photoresist, as shown in figure 41, to photoresist 132 compositions, give the NMOS that will contact and the part opening of N type resistor with wiring metal with photoetching process.Afterwards, give donor impurity such as the phosphorus or the arsenic of P type substrate and N type resistor introducing high concentration with ion implantation, and form corresponding to the source electrode of NMOS and the N+ district 103 and the N+ multi-crystal silicon area 109 of drain electrode.

Usually with there being the arsenic of little diffusion coefficient to make impurity, form shallow-source electrode and shallow drain electrode.In order to make resistance low as far as possible, impurity dose is 1 * 10 ¹⁵Atom/cm ²Or higher, and concentration is 1 * 10 in this case ¹⁹Atom/cm ³Or it is higher.

In addition, under this situation, owing on the grid of NMOS, form dielectric film, so donor impurity does not enter the P+ grid of NMOS.Therefore, work function and resistance value are constant.In addition, donor impurity does not enter the part under the zone that is provided with the side isolation, therefore, can produce low electric field in the end of drain electrode.

In addition, although not shown, in order to improve temperature coefficient, can form the N+ resistor that is made of polysilicon by this step, wherein whole N type resistance area is in high concentration.

Afterwards, after photoresist is peeled off, and if necessary after carrying out impurity activation heat treatment, with photoetching process to photoresist 132 compositions, with part opening at PMOS that will contact and P type resistor with wiring metal.Afterwards, use ion implantation, introduce high concentration acceptor impurity such as B or BF for N trap and P type resistor ₂, and form should be in the source electrode of PMOS and the P+ district 104 and the P+ multi-crystal silicon area 108 of drain electrode.Because resistance is done lowly as far as possible resembling among the NMOS, so impurity dose is 1 * 10 ¹⁵Atom/cm ²Or higher, concentration in this case is 1 * 10 ¹⁹Atom/cm ³Or it is higher.

In addition, can be similarly constructed on the P+ resistor that has high concentration in the whole P type resistor area with the N+ resistor by this step.

In the step afterwards, step is the same shown in the image pattern 21, forms intermediate insulating film.

As mentioned above, by the step of Figure 36 to 43, can make the cmos semiconductor device architecture of fourth embodiment of the invention shown in Figure 35.

Second embodiment of the method for the cmos semiconductor device of making fourth embodiment of the invention below will be described.Carry out the step identical, form grid, wiring and resistor area with step shown in Figure 12 to 17.But, in the present embodiment, do not carry out the step that the polyresistor shown in Figure 13 and 15 is introduced impurity.

Carrying out after the above-mentioned steps, carrying out the step identical, removing the dielectric film 134 on the resistor with step shown in Figure 40.

Afterwards, as scheme shown in Figure 43ly,, give the part opening of NMOS and N type resistor photoresist 132 compositions.Afterwards, introduce low concentration donor impurity such as phosphorus or arsenic for P type semiconductor substrate and polysilicon, form low concentration source electrode and the N-district 142 of drain electrode and the N-polysilicon that will become N type resistor simultaneously corresponding to NMOS with ion implantation.

Although in above-mentioned a plurality of embodiment, form low concentration LDD source area and drain region and the N-polyresistor of NMOS respectively with different step, but because their impurity concentration is approaching mutually, therefore as mentioned above, they can form simultaneously by the specification requirement of product.Thereby can reduce manufacturing cost and reduce manufacturing time.

Then, after removing photoresist, as shown in figure 44, to photoresist 132 compositions, give as shown in figure 43 PMOS and the part opening of P type resistor.Afterwards, use ion implantation, introduce low concentration acceptor impurity such as BF for N trap and polysilicon ₂Or B, and form low concentration source electrode and the P-district 143 of drain electrode and the P-polysilicon (P-polycrystallinesilicon) 110 that will become P type resistor simultaneously corresponding to PMOS.Therefore, owing to, can reduce manufacturing cost and shorten manufacturing time with reference to Figure 43 explanation.

Following step is identical with the step in the manufacture method shown in Figure 38 to 42.As a result, can make the structure of the cmos semiconductor device of fourth embodiment of the invention shown in Figure 35.By above-mentioned another manufacture method of the present invention, can reduce mask step, therefore the advantage that reduces manufacturing cost and shorten manufacturing time is arranged.

But, should be noted that its resistance value may change as a result owing to when the formation side is isolated, carry out the anisotropy dry corrosion under the state of not establishing dielectric film on the resistor, so resistor may cause damage because of being exposed to plasma in the corrosion process.

Figure 45 is the profile of the cmos semiconductor device of fifth embodiment of the invention.

This cmos semiconductor device is with the cmos device that has the NMOS 113 of LDD structure, the PMOS112 that the LDD structure is arranged and film P-resistor 138 and film N-resistor 139 to constitute, wherein, the grid that is formed on the NMOS 113 on the P type semiconductor substrate 101 constitutes with a P+ polysilicon 107, and its source electrode and drain electrode are used for the electric field tension and relaxation; The grid that is formed on the PMOS 112 on the N well region 102 also constitutes with a P+ polysilicon 107; Film P-resistor 138 and film N-resistor 139 are made of the membrane polysilicon that is formed on the field insulating membrane 106.

Make the MOS structural reason as for cmos semiconductor device description shown in Figure 35 with the LDD structure.Equally, adopt reason that membrane polysilicon makes resistor as for the 3rd embodiment explanation shown in Figure 22.But owing to form the CMOS structure on basis of the present invention is the P+ grid, so the effect of low-work voltage operation and low-power consumption is same as the previously described embodiments.

Make the 5th embodiment of the method for cmos semiconductor device of the present invention hereinafter with reference to description of drawings.

Carry out with Figure 23 and 24 in the identical step of step, form P+ polysilicon gate 133.The thickness scope of P+ polysilicon is 2000 to 6000 , because grid constitutes with single level polysilicon.

Afterwards, as shown in figure 46, form dielectric film 134 on the polysilicon.In the manufacture method of the cmos semiconductor device of above-mentioned the 4th embodiment, be that lower floor and silicon nitride film are that the laminated construction on upper strata constitutes this dielectric film 134 with silicon oxide film.The gross thickness of dielectric film 134 is 1000 to 3000 .

Next, as shown in figure 47, use photoetching process and anisotropy dry corrosion, form grid and wiring dielectric film 134 and P+ polysilicon composition.

Form (grid and wiring) with two kinds of methods.That is, a kind of method is, with photoetching process to the photoresist composition after, make the mask corrosion dielectric film with photoresist, the corrosion polysilicon stays photoresist simultaneously, after this, removes photoresist.Another kind method is, give the photoresist composition with photoetching process after, make the mask corrosion dielectric film with photoresist, peel off photoresist, afterwards, make the mask corrosion polysilicon with dielectric film.

Afterwards, as shown in figure 48, give photoresist 132 compositions, give the NMOS opening with photoetching process.Afterwards, introduce low concentration donor impurity such as phosphorus or arsenic for P type substrate with ion implantation, and form corresponding to the low concentration source electrode of NMOS and the N-district 142 of drain electrode.

The operating voltage of impurity concentration decision semiconductor product, but impurity dose normally 10 ¹²To 10 ¹⁴Atom/cm ²Concentration is 10 under this situation ¹⁶Atom/cm ³To 10 ¹⁸Atom/cm ³

Then, after removing photoresist, as shown in figure 49, to photoresist 132 compositions, give the PMOS opening with photoetching process.Afterwards, introduce low concentration acceptor impurity such as B or BF2 for the N trap with ion implantation, and form corresponding to the low concentration source electrode of PMOS and the P-district 143 of drain electrode.

Afterwards, after removing photoresist, as shown in figure 50, on Semiconductor substrate, form the dielectric film 144 that will become later the side isolation with the CVD method.Under this situation, need so to form side and isolate: stay dielectric film 134 on the polysilicon as dielectric film.Therefore, make this dielectric film 144 with silicon oxide film, silicon oxide film has with respect to the corrosion selection ratio as the silicon nitride film on the upper strata of dielectric film 134.Although the thickness of dielectric film 144 is relevant with the electric field tension and relaxation degree of requirement, be generally 2000 to 6000 .Can carry out the oxide-film close thermal after dielectric film 144 deposits handles.

Afterwards, shown in Figure 51, dielectric film 144 is carried out the anisotropy dry corrosion, thus, form side on as the sidewall of the polysilicon of grid or wiring and isolate 141.

In the formation of side isolation 141, because dielectric film 144 is silicon oxide films, the upper strata of the dielectric film 134 on the polysilicon is silicon nitride films, therefore, can obtain enough big selection ratio in anisotropic etch.Therefore, do not corrode the dielectric film on the polysilicon in the corrosion process, make and leave dielectric film on the polysilicon.

Afterwards, shown in Figure 52, deposition film polysilicon 136.

As constitute grid and wiring with polysilicon, with CVD method deposition film polysilicon.But, under many circumstances,, therefore hanging down deposition film polysilicon under the deposition temperature because thickness has only 500 to 2000 .In addition, also available sputtering method carries out thin film deposition.

Owing to constitute resistor with membrane polysilicon, therefore,, also be enough to keep the precision of resistance value even be set in up to a few K Ω/mouth to the situation of tens K Ω/mouth in the thin-film electro resistance of resistor.

Next, shown in Figure 53, to photoresist 132 compositions, give the part opening of N type resistor, phosphorus or arsenic are optionally introduced in the membrane polysilicon 136 as donor impurity with ion implantation with photoetching process.

As will be described later, available ion implantation is pressed acceptor impurity in the whole surface of low concentration introducing membrane polysilicon in next step.But it is the N type that the setting of impurity dose should make the conduction type after ion injects.The scope of impurity dose normally 10 ¹⁴To 10 ¹⁵Atom/cm ², the net concentration scope is 1 * 10 approximately ¹⁴To 9 * 10 ¹⁸Atom/cm ³Thin-film electro resistance scope is several to tens K Ω/mouth.In order to make the current drain that causes owing to resistance in the bleeder circuit be set in μ A or lower at least, the thin-film electro resistance need be set at above-mentioned value.

And according to the requirement of circuit or product, the high resistance of N type polysilicon may be optional.Under this situation, can save the step among Figure 53.

Next, after peeling off photoresist 132, shown in Figure 54, use ion implantation acceptor impurity such as B or BF ₂Press low concentration and introduce in the membrane polysilicon 136, to form P type resistor area.

The scope of impurity dose normally 10 ¹⁴To 10 ¹⁵Atom/cm ², the net concentration scope is 1 * 10 approximately ¹⁴To 9 * 10 ¹⁸Atom/cm ³Thin-film electro resistance scope is several to tens K Ω/mouth.In N type resistor, be set in μ A or lower at least in order to make the current drain that causes owing to resistance in the bleeder circuit, the thin-film electro resistance need be set at above-mentioned value.

In addition, according to the requirement of circuit or product, the high resistance of P type polysilicon may be optional.Under this situation, can save the step among Figure 54.

In membrane polysilicon, form N type resistor area and P type resistor area by the step in Figure 53 and 54.But, needn't adopt this sequence of steps.Step among conversion Figure 53 and 54 can form N type resistor area and P type resistor area equally.

Afterwards, as shown in figure 30, use photoetching process and etch, form resistor membrane polysilicon 136 compositions.

Because the processing requirements precision of resistor is so use the anisotropic dry etch.Usually, in dry corrosion, the selection ratio of polysilicon and nitride film can not be set very big.Thereby, in the membrane polysilicon corrosion, remove nitride film fully as the upper strata of the dielectric film 134 on the P+ polysilicon 133 that is used for grid and wiring.But oxide-film is as the lower floor of dielectric film 134, and can guarantee in dry corrosion has enough big selection ratio to polysilicon film.As a result, owing to the dielectric film of not removing fully on the P+ polysilicon 133 134, it has the function as mask fully in the ion implantation process that carries out when forming source electrode and drain electrode, and this will be explained below.

Afterwards, after photoresist 132 is peeled off, shown in Figure 56, to the photoresist composition, give the NMOS that to contact with wiring metal and the part opening of N type resistor with photoetching process.Afterwards, use ion implantation the donor impurity of high concentration such as phosphorus or arsenic introducing P type substrate and N type resistor, and form corresponding to the source electrode of NMOS and the N+ district 103 and the N+ multi-crystal silicon area 109 of drain electrode.

Usually make shallow-source electrode and shallow drain electrode with the little arsenic of diffusion coefficient as impurity.In order to obtain alap resistance, impurity dose is 1 * 10 ¹⁵Atom/cm ³Or higher, and concentration is 1 * 10 under this situation ¹⁹Atom/cm ³Or it is higher.

In addition, under this situation, owing to dielectric film 134 is formed on the grid of NMOS, so donor impurity does not enter the P+ grid of NMOS.Therefore work function and resistance value are constant.And donor impurity does not enter and forms the following part in zone that side is isolated, so drain edge can form low electric field.

In addition, although not shown, in order to improve temperature coefficient, can form the N+ resistor that membrane polysilicon constitutes, wherein whole N type resistor area is in high concentration.

Afterwards, after photoresist is peeled off, carry out impurity activation heat treatment if desired.Afterwards, shown in Figure 57, to the photoresist composition, give the PMOS that to contact with wiring metal and the part opening of P type resistor with photoetching process.Afterwards, use ion implantation high concentration acceptor impurity BF ₂Or B introducing N trap and P type resistor, and form corresponding to the source electrode of PMOS and the P+ district 104 and the P+ multi-crystal silicon area 108 of drain electrode.In NMOS, because resistance is done lowly as far as possible, so impurity dose is 1 * 10 ¹⁵Atom/cm ²Or higher, and concentration is 1 * 10 under this situation ¹⁹Atom/cm ³Or it is higher.

And, in this step, also can as described in reference Figure 56, on whole zone, form high concentration P+ resistor.

As mentioned above, by Figure 23 and 24 and Figure 46 to 57 in step, can make the structure of the cmos semiconductor device of fifth embodiment of the invention shown in Figure 45.

Figure 58 is the profile of the cmos semiconductor device of sixth embodiment of the invention.

This cmos device is the cmos device that is made of the NMOS 113 that the LDD structure is arranged, the PMOS 112 that the LDD structure is arranged and P-resistor 114 and N-resistor 115, wherein, the grid that is formed on the NMOS 113 on the P type semiconductor substrate 101 has the so-called sandwich construction of the lamination formation of using refractory metal silicide 127 and P+ polysilicon 107, and its source electrode and drain electrode have the LDD structure; Be formed on the so-called sandwich construction that the lamination of the also useful refractory metal silicide 127 of grid of the PMOS 112 on the N well region 102 and P+ polysilicon 107 constitutes; P-resistor 114 and N-resistor 115 are that the same one deck polysilicon that is used as the lower floor that is formed on the multi-layered electrode on the field insulating membrane 106 constitutes.

Constituting because resistor is the same one deck polysilicon that is used as the lower floor of sandwich construction electrode, so the thickness of resistor is little, is 1000 to 4000 .Therefore, resistance value can reach very high degree of precision.

Adopting the LDD structure to make the MOS structure has two reasons, is to realize miniaturization and improve reliability, has illustrated as the 4th embodiment with reference to cmos semiconductor device shown in Figure 35.Similarly, the reason that adopts the grid of sandwich construction is in order to reach high-speed, as illustrating with reference to the 3rd embodiment shown in Figure 22.But, be the P+ grid owing to constitute the CMOS structure on basis of the present invention, so the effect of low-work voltage and low-power consumption is the same with the foregoing description.

Make the method for the cmos semiconductor device of sixth embodiment of the invention hereinafter with reference to description of drawings.

Following state has been shown among Figure 59.With the step shown in Figure 12 to 15, in polysilicon 131, behind formation P+ multi-crystal silicon area 133, N-multi-crystal silicon area 111 and the P-multi-crystal silicon area 110, use CVD method deposit dielectric film 145.Afterwards, give dielectric film 145 compositions, it is deposited on N-multi-crystal silicon area 111 and the P-multi-crystal silicon area 110 with photoetching process and etch.

Here the difference with step shown in Figure 12 to 15 is, the thickness of polysilicon 131 is little, and the thickness scope is at 1000 to 4000 .This is in order to obtain the sandwich construction of grid.

As dielectric film 145, its thickness range is at 1000 to 4000 usually for silicon oxide film.After dielectric film 145 deposits, it can be 900 ℃ of heat treatments 30 minutes in electric furnace, to improve the tightness of film.

Afterwards, shown in Figure 60, the deposit refractory metal on P+ polysilicon 133 and dielectric film 145 with sputtering method or CVD method.One of molybdenum silicide, tungsten silicide, titanium silicide and platinum silicide are as refractory metal silicide, and its thickness scope is at 500 to 2500 .When forming refractory metal silicide,, consider, form refractory metal silicide with sputtering method usually from the cementability of refractory metal silicide and polysilicon although worry to take place some possible damages.

Afterwards, shown in Figure 61, give photoresist 132 compositions, give dielectric film 145 and near opening thereof, optionally remove refractory metal silicide with the dry corrosion method with photoetching process.

Afterwards, remove photoresist, and behind the dielectric film of removing with wet corrosions such as HF solution on the resistor 145, form dielectric film 134 at refractory metal silicide 127 with on, shown in Figure 62 as the polysilicon of resistor.This dielectric film is a laminated construction, and its lower floor is a silicon oxide film, and its upper strata is a silicon nitride film.Form silicon nitride film with the CVD method.Equally, also form silicon oxide film with the CVD method.The gross thickness of silicon nitride film and silicon oxide film is set for each tunic is thick: make dielectric film 134 that the mask function be arranged, to prevent that donor impurity enters grid in the source electrode of NMOS and the formation that drains, and the silicon oxide film as the lower floor of insulating barrier 134 in side isolate to form does not expose, and this will illustrate below.For example, the thickness setting of silicon nitride film is 2000 , and the thickness setting of silicon oxide film is 1000 .

And, in this step, can heat-treat to improve the tightness of film behind the formation dielectric film 134.

Afterwards, shown in Figure 63, give dielectric film 134, refractory metal silicide 127 and polysilicon composition, form grid, wiring and resistor with photoetching process and etch.For the resistor part,, before corrosion grid and wiring region, just finished corrosion owing to do not have refractory metal silicide 127 on the polysilicon.But underlying membrane is thick field insulating membrane 106, so can not have problems.

The step of carrying out is identical with step shown in Figure 36 to 42 subsequently, can make the structure of the cmos semiconductor device of the 6th embodiment shown in Figure 58 thus.

Among Figure 64, carrying out shown in Figure 59 after the step, with sputtering method deposit refractory metal 140 of Co or Ti for example on P+ polysilicon 107 and dielectric film 145.

The thickness scope of Co or Ti is 100 to 500 .When using Co, can stacked thick tens to Ti or the TiN of hundreds of .

Afterwards, with rapid thermal treatment (RTP),, make the part silication of the refractory metal that contacts with polysilicon in 600 ℃ to 750 ℃ tens seconds to 1 of following heat treatment minute.Afterwards, for example use the mixed solution of hydrogen peroxide and ammoniacal liquor, or, optionally remove the refractory metal that does not have reaction on the dielectric film 145 with the mixed solution of sulfuric acid and hydrogen peroxide.This moment, state was shown in Figure 65.

Afterwards, at 700 ℃ to the 900 ℃ RTP that carried out for tens seconds.Afterwards, with the dielectric film 145 on the HF solution corrosion removal polyresistor.Therefore, make structure shown in Figure 66.

Among this second embodiment,, can on grid and wiring region, stay refractory metal silicide by self-aligned manner with the foregoing description contrast.Therefore the advantage of second embodiment is with the foregoing description ratio, can reduce lithography step.

By with the manufacture method shown in Figure 62 in identical step and step subsequently, can make the structure of the cmos semiconductor device of the 6th embodiment shown in Figure 58.

In addition, to in grid and wiring region, form the said method of refractory metal silicide electrode and combine with self-aligned manner, and can make the structure of the cmos semiconductor device of the 6th embodiment shown in Figure 58 in the method that the low concentration region of the NMOS of multi-crystal silicon area and PMOS and resistor area mixes simultaneously.Under this situation, can further reduce step, the manufacturing cycle is significantly shortened, manufacturing cost obviously reduces.

In addition, in the method for the cmos semiconductor device of making the 6th embodiment, in state shown in Figure 59, corresponding to step shown in Figure 12 to 15, after in polysilicon, forming N-multi-crystal silicon area 111, P-multi-crystal silicon area 110 and P+ multi-crystal silicon area 107, deposit dielectric film 145, and to its composition.But, following possibility is arranged, that is, the order of above-mentioned steps can change.After N-

multi-crystal silicon area

111 and 110 formation of P-multi-crystal silicon area, to dielectric film 145 compositions, shown in Figure 59.Afterwards, the usefulness dielectric film 145 of composition is made mask, and P+ district 107 is formed in the polysilicon.Under this situation, reduced mask step, thereby can shorten the manufacturing cycle and reduce manufacturing cost.

Figure 67 is the profile of the cmos semiconductor device of seventh embodiment of the invention.

This cmos semiconductor device is the cmos device with NMOS 113, the PMOS 112 that the LDD structure is arranged and P-resistor 138 and N-resistor 139 formations, wherein, the grid that is formed on the NMOS 113 on the P type semiconductor substrate 101 has the laminated construction of refractory metal silicide 127 and P+ polysilicon 107 formations, and its source electrode and drain electrode have the LDD structure; The grid that is formed on the PMOS 112 on the N well region 102 has the sandwich construction of the lamination formation of refractory metal silicide 127 and P+ polysilicon 107; The membrane polysilicon that P-resistor 138 and N-resistor 139 usefulness are formed on the P type semiconductor substrate 101 constitutes.

Adopting this structural reason identical with the reason of the cmos semiconductor device of the 4th embodiment shown in Figure 35, is for miniaturization and raising reliability.The reason that forms resistor with membrane polysilicon is identical with the 5th embodiment, is in order to improve resistance precision.But, be the P+ grid as the CMOS structure on basis of the present invention.Therefore, the effect of low-work voltage and low-power consumption is same with the above-mentioned embodiment.

The manufacture method of the cmos semiconductor device by making up the 3rd to the 6th embodiment, for example, the step of combination Figure 23 to 26 and Figure 48 to 57 can constitute the cmos semiconductor device of the seventh embodiment of the invention shown in Figure 67.

Figure 68 is the profile of the cmos semiconductor device of eighth embodiment of the invention.

Grid has CMOS, P-resistor 113 and the N-resistor 115 that unipolarity P+ polysilicon is arranged, and P-resistor 113 and N-resistor 115 are to constitute with the same one deck polysilicon that constitutes grid, and this is basis of the present invention.

Same as the previously described embodiments, the cmos semiconductor device of present embodiment has low-work voltage, low-power consumption and effect cheaply.And, this cmos semiconductor device has so-called drain electrode to extend the MOS structure, wherein, source electrode and drain electrode or have only the drain electrode be low diffusion layer N-142 or P-143 of impurity concentration, and source electrode and drain electrode or have only the drain electrode be high diffusion layer N+103 or P+104 of impurity concentration, to improve the modulation of channel length in the analog circuit, suppress the reliability decrease that hot carrier causes, improve the withstand voltage of drain electrode.This structure is fit to the boosting type SWR that the VD and the VR of high input voltage arranged and high output voltage is arranged.

From grid to the distance of leaving the high impurity concentration diffusion layer that grid forms, i.e. deflected length, although relevant with the input voltage of semiconductor device,, deflected length is 0.5 to a few μ m usually.Among Figure 68, the side of PMOS112 adopts off-set construction, and off-set construction is adopted in the both sides of NMOS 113.But, can be suitable for the suitable construction of the PMOS of element circuitry by the purposes selection of circuit, and not consider the conduction type of MOS transistor.Usually, be that two-way and source electrode and drain electrode according to condition change and need under the two-way withstand voltage situation at the sense of current, off-set construction is all adopted in source electrode and drain electrode.On the other hand, be unidirectional and source electrode and drain electrode are under the situation of fixing at the sense of current, in order to reduce parasitic capacitance, having only drain electrode to adopt off-set construction.

The following method of making the cmos semiconductor device of the eighth embodiment of the invention among Figure 68 with reference to description of drawings.

Step in carry out Figure 12 to 15 is made structure shown in Figure 69.

Grid as basis of the present invention has CMOS, P-resistor 113 and the N-resistor 115 that unipolarity P+ polysilicon is arranged, and P-resistor 113 and N-resistor 115 are to constitute with the same one deck polysilicon that constitutes grid.

The cmos semiconductor device of present embodiment is as the foregoing description, and low-work voltage, low-power consumption and effect are cheaply arranged.And, this cmos semiconductor device has so-called drain electrode extended structure, wherein, source electrode and drain electrode or have only the drain electrode be low diffusion layer N-142 or P-143 of impurity concentration, and source electrode and drain electrode or have only the drain electrode be high diffusion layer N+103 or P+104 of impurity concentration, to improve the modulation of channel length in the analog circuit, the reliability that suppresses to cause because of hot carrier reduces, and the raising drain electrode is withstand voltage.This structure is suitable for the boosting type SWR that the VD and the VR of high input voltage arranged and high output voltage is arranged.

From grid to the distance of leaving the high impurity concentration diffusion layer that grid forms, i.e. deflected length, although relevant with the input voltage of semiconductor device, normally 0.5 to a few μ m.In Figure 68, the side of PMOS 112 adopts off-set construction, and off-set construction is adopted in the both sides of NMOS 113.But, can be applicable to the suitable construction of the PMOS of element circuitry by the selection of circuit purposes, and not consider the conduction type of MOS transistor.Usually, be two-way and source electrode and drain electrode and under the two-way withstand voltage situation of needs at the sense of current according to condition changing, off-set construction is all adopted in source electrode and drain electrode.On the other hand, be unidirectional and source electrode and drain electrode are under the situation of fixing at the sense of current, in order to reduce parasitic capacitance, having only drain electrode to adopt off-set construction.

Below the method for the semiconductor device of eighth embodiment of the invention among Figure 68 is made in explanation.

Step in carry out Figure 12 to 15 is made structure shown in Figure 69.

Afterwards, shown in Figure 70, give polysilicon 131 compositions, form grid, wiring and resistor with photoetching process and etch.

In the so-called mask skew CMOS structure in Figure 70, in the source electrode and drain electrode formation of high concentration, can form the mask of photoresist, therefore, can prevent that the high concentration donor impurity from entering the grid of NMOS grid.Therefore, forming the step of dielectric film on the required polysilicon 131 in the manufacturing of the cmos semiconductor device of first to the 7th embodiment, is unwanted here.

Afterwards, shown in Figure 71, give photoresist 132 compositions, give the NMOS opening with photoetching process.Afterwards,, form low concentration donor impurity such as phosphorus or arsenic introducing P type substrate with ion implantation corresponding to the low concentration source electrode of NMOS and the N-district 142 of drain electrode.

The operating voltage of impurity concentration decision semiconductor product, but impurity dose is usually 10 ¹²To 10 ¹⁴Atom/cm ²Concentration is 10 in this case ¹⁶Atom/cm ³To 10 ¹⁸Atom/cm ³

As mentioned above, in the high concentration source electrode and drain electrode formation of NMOS, must make gate mask and introduce impurity with photoresist.Therefore, in the step, source electrode and drain electrode all need to introduce the low concentration donor impurity shown in Figure 71.At this moment, donor impurity is also introduced the P+ polysilicon gate of NMOS.But, the magnitude of donor impurity (order) difference, therefore work function and the resistance value to grid there is not influence.

In addition, available same photoresist figure is made mask, introduces acceptor impurity with ion implantation with higher-energy, forms so-called p type island region (pocket) with the bottom in low concentration N-district 142.

Afterwards, after removing photoresist, give photoresist 132 compositions, give the PMOS opening with photoetching process.Afterwards, use ion implantation acceptor impurity such as B or BF ₂Low concentration is introduced the N trap, forms corresponding to the low concentration source electrode of PMOS and the P-district 143 of drain electrode.

A side that among Figure 72 is PMOS forms the P-district,, only forms the P-district in drain electrode one side that is.But, as mentioned above, can be that source electrode and drain electrode all form the P-district by the purposes of PMOS circuit.

In addition, in this step, available ion implantation is introduced donor impurity with higher energy, with as in the step of Figure 71, forms so-called N type district in the bottom in low concentration P-district 143.

Next, after photoresist 132 is peeled off, shown in Figure 73, give photoresist 132 compositions with photoetching process, at the part opening of NMOS that will contact and N type resistor with wiring metal.Afterwards, donor impurity such as phosphorus or arsenic are introduced P type substrate with high concentration, form corresponding to the source electrode of NMOS and the N+ district 103 and the N+ multi-crystal silicon area 109 of drain electrode with ion implantation.

Usually with there being the arsenic of little diffusion coefficient to make impurity, constitute shallow-source electrode and shallow drain electrode.In order to obtain alap resistance, impurity dose is 1 * 10 ¹⁵Atom/cm ²Or higher, and concentration is 1 * 10 under this situation ¹⁹Atom/cm ³Or it is higher.

In addition, under this situation, owing to photoresist is located on the grid of NMOS, so donor impurity does not enter the P+ grid of NMOS.Therefore, work function and resistance value are constant.

At this moment, to the photoresist composition, make photoresist become the mask of the part of the source electrode of adjacent gate and drain electrode, as mentioned above, the mask width is generally 0.5 to a few μ m.But photoresist is located on source electrode one side, does not need to consider hot carrier and channel length modulation, and it is the mask as grid.Thereby, only need make photoresist from grid stretch out with at this moment photoetching method the corresponding distance of alignment error value of used aligner.For example, to be about 0.3 μ m just enough for the mask width.

Next, after photoresist is peeled off, and if desired after carrying out impurity activation heat treatment, shown in Figure 74, give photoresist 132 compositions, to the PMOS that will contact and the part opening of P-resistor with wiring metal with photoetching process.Afterwards, use ion implantation, acceptor impurity such as BF ₂Or B introduces N trap and P type resistor with high concentration, and forms corresponding to the source electrode of PMOS and the P+ district 104 and the P+ multi-crystal silicon area 108 of drain electrode.In NMOS, owing to will make resistance low as far as possible, impurity dose is 1 * 10 ¹⁵Atom/cm ²Or higher, concentration is 1 * 10 under this situation ¹⁹Atom/cm ³Or it is higher.

By above-mentioned step, can make the structure of the cmos semiconductor device of the 8th embodiment shown in Figure 68.

Figure 75 and 76 demonstrates second embodiment of the method for the cmos semiconductor device of making the 8th embodiment among Figure 68.

In the manufacture method shown in Figure 12 to 15, under the situation that does not form N-polysilicon 111 among Figure 13 and the P-polysilicon 110 among Figure 15, to the P-polysilicon composition shown in Figure 70, formation is the zone of grid, wiring and resistor.Afterwards, shown in Figure 75, to photoresist 132 compositions, to the part opening that will be NMOS and N type resistor.Afterwards, donor impurity such as phosphorus or arsenic are introduced the P type semiconductor substrate with low concentration, form corresponding to the N-district 142 of the low concentration source electrode of NMOS and drain electrode simultaneously and will be the N-polysilicon 111 of N type resistor with ion implantation.

The impurity concentration of the offset source polar region of the low impurity concentration of NMOS and the impurity concentration of drain region and N type polyresistor is closer to each other.Therefore, can carry out forming above-mentioned the time technology by the specification requirement of product.

After removing photoresist, shown in Figure 76, give photoresist 132 compositions, shown in Figure 75, to the part opening that will be PMOS and P type resistor.Afterwards, use ion implantation acceptor impurity such as B or BF ₂Introduce N trap and polysilicon with low concentration, and form corresponding to the P-district 143 of the low concentration source electrode of PMOS and drain electrode and will be the P-polysilicon 110 of P type resistor.

The step of carrying out is identical with step in the manufacture method shown in Figure 73 and 74 subsequently, with the structure of the cmos semiconductor device of making the 8th embodiment shown in Figure 68.By above-mentioned second kind of manufacture method of the present invention, can reduce mask step, thereby reduce cost and shortened the manufacturing cycle.

In addition, in the explanation of the manufacture method of the cmos semiconductor device of above-mentioned the 8th embodiment,, before high-concentration diffusion region forms, form the low-concentration diffusion region of MOS for NMOS and PMOS.But, even when before low-concentration diffusion region forms, forming high-concentration diffusion region, also can make the structure of the cmos semiconductor device of the 8th embodiment among Figure 68.The effect of semiconductor device is identical.

Figure 77 is the profile of the cmos semiconductor device of ninth embodiment of the invention.

Grid has CMOS, P+ resistor 138 and the N-resistor 139 that unipolarity P+ polysilicon 107 is arranged, and P+ resistor 138 and N-resistor 139 are to use the polysilicon thinner than grid to constitute, and this is basis of the present invention.

This MOS has the drain electrode extended structure, and to improve the modulation of channel length, the reliability that suppresses to cause because of hot carrier reduces, and the raising drain electrode is withstand voltage, and approaches in order to improve precision resistor.But as those above-mentioned embodiment, the semiconductor device of present embodiment also has low-work voltage, low-power consumption and effect cheaply.

Make the method for the cmos semiconductor device of ninth embodiment of the invention among Figure 77 hereinafter with reference to description of drawings.

In those steps of step shown in Figure 46, save the step that on P+ polysilicon 133, forms dielectric film 134, and give P+ polysilicon 133 compositions with photoetching process and dry corrosion.Make structure shown in Figure 78.Do not need the reason of dielectric film 134 to be, make mask, can prevent that donor impurity from entering the P+ polysilicon gate with photoresist.

Because grid constitutes with the polysilicon individual layer, so P+ monocrystalline silicon 133 thickness are 2000 to 6000 .

Below, shown in Figure 79, after forming dielectric film 137, deposition film polysilicon 136.

Dielectric film 137 for example is the thick oxide-film of hundreds of that forms with thermal oxidation method, or with the thick oxide-film of hundreds of of CVD method formation.

In low deposition temperature, form membrane polysilicon 136 with CVD method or sputtering method.

With forming resistor than the thin polysilicon of polysilicon that constitutes grid and wiring usefulness.Therefore, even be set in up to a few K Ω/mouth to the situation of tens K Ω/mouth, also can fully keep the precision of resistance value in the thin-film electro resistance of resistor.

Below, shown in Figure 80, give photoresist 132 compositions with photoetching process, to the part opening that will be N type resistor, and phosphorus or arsenic are optionally introduced membrane polysilicon 136 as donor impurity with ion implantation.

As described below, in the step afterwards, acceptor impurity is injected in the whole surface of membrane polysilicon with the low concentration ion.But impurity dose is set for: even conduction type also should be that N type and concentration are in the certain limit after ion injects.Impurity dose scope normally 10 ¹⁴To 10 ¹⁵Atom/cm ², the net concentration scope is 1 * 10 ¹⁴To 9 * 10 ¹⁸Atom/cm ³The thin-film electro resistance is several to tens K Ω/mouth.For the current drain that will cause owing to resistance in the bleeder circuit is set in μ A or lower at least, the thin-film electro resistance must be set at above-mentioned value.

In addition, according to the requirement of circuit or product, the high resistance of N type polysilicon may be optional.Under this situation, can save step shown in Figure 80.

Then, after photoresist 132 is peeled off, shown in Figure 81, use ion implantation, B or BF ₂Introduce in the whole membrane polysilicon 136 as acceptor impurity, to form P type resistor area.

Impurity dose scope normally 10 ¹⁴To 10 ¹⁵Atom/cm ², the net concentration scope is 1 * 10 ¹⁴To 9 * 10 ¹⁸Atom/cm ³The thin-film electro resistance is several to ten K Ω/mouth.In N type resistor,, must be set in above-mentioned value to the thin-film electro resistance for the current drain that will cause owing to resistance in the bleeder circuit is set in μ A or lower at least.

In addition, in N type resistor, according to the requirement of circuit or product, the high resistance of P type polysilicon may be optional.In this case, can save step among Figure 81.

By step shown in Figure 80 and 81, in membrane polysilicon 136, form N type resistor area and P type resistor area.But, needn't adopt this sequence of steps.Step forms N type and P type resistor area equally shown in exchange Figure 80 and 81.

Below, shown in Figure 82, use photoetching process and etch to membrane polysilicon 136 compositions, form resistor.

Because the processing to resistor has required precision, so use the anisotropy dry corrosion.

Carry out step identical in the CMOS manufacture method with the 8th embodiment shown in Figure 71 and step subsequently, make the structure of the cmos semiconductor device of the 9th embodiment shown in Figure 77.

Figure 83 is the profile of the cmos semiconductor device of tenth embodiment of the invention.

Grid has: the CMOS, P-resistor 114 and the N-resistor 115 that are made of the laminated construction of P+ polysilicon 107 and refractory metal silicide 127, the polysilicon of P-resistor 114 and N-resistor 115 usefulness and grid lower floor is that the polysilicon with one deck constitutes, and this is basis of the present invention.

Sandwich construction use in grid and wiring, and this structure is suitable for strengthening high speed operation, and in the MOS structure, and with the drain electrode extended structure, to improve channel length modulation, the reliability that suppresses to cause because of hot carrier reduces, and improve drain withstand voltage.But,, still have low-work voltage, low-power consumption and effect cheaply as the foregoing description.

The method of the cmos semiconductor device of making tenth embodiment of the invention is described with reference to Figure 83 below.

In step shown in Figure 59 to 63, can save the step that on N-polyresistor, P-polyresistor and refractory metal silicide 127, forms dielectric film 134.The sandwich construction that the lamination of refractory metal silicide and polysilicon is constituted with photoetching process and dry corrosion method and by the resistor area composition that single level polysilicon forms is made structure shown in Figure 84.The reason that does not need dielectric film 134 is identical with reason in the manufacture method of the 9th embodiment, that is, available photoresist prevents that as mask donor impurity from entering the P+ grid.

For the relevant manufacturing step behind the above-mentioned state, identical with step in the manufacture method of the CMOS structure of eighth embodiment of the invention shown in the Figure 71 of front.As a result, shown in Figure 83, can make the structure of the cmos semiconductor device of tenth embodiment of the invention.

Figure 85 is the profile of the cmos semiconductor device of eleventh embodiment of the invention.Grid has the CMOS that the lamination by P+ polysilicon 107 and refractory metal silicide 127 constitutes, and this is basis of the present invention, and has P-resistor 138 and N-resistor 139, and these resistors use the polysilicon layer thinner than lower floor's polysilicon of grid to constitute.

Grid adopts sandwich construction with connecting up, and this is suitable for strengthening high speed operation, and in the MOS structure, with the drain electrode extended structure, thereby can improve channel length modulation, the reliability decrease that inhibition causes because of hot carrier, and the raising drain electrode is withstand voltage.And, do thinlyyer for improving its precision resistor.But, in the above embodiments, still have the low effect of low-work voltage, low-power consumption and cost.

The manufacture method of the cmos semiconductor device of appropriate combination the 8th embodiment to the ten embodiment just obtains the manufacture method by the cmos semiconductor device of eleventh embodiment of the invention.

In addition, by in the cmos semiconductor device of the 8th to the tenth embodiment, make mask with photoresist and can prevent that donor impurity from mixing in the P+ grid.Therefore, do not form on the grid as insulating 134 and so on hard mask material.But, shown in first to the 7th embodiment, can form hard mask material on the grid.Under this situation, extend in the MOS structure in drain electrode, can make the overlapping of N+ (polysilicon) and grid, wherein, the source electrode one side high concentration in NMOS spreads, and the result can reduce the parasitic capacitance of source electrode one side.

In addition, in the manufacture method of the cmos semiconductor device of the present invention the the the 3rd, the 5th, the 7th, the 9th and the 11 embodiment, form the membrane polysilicon that back formation will become resistor at grid.But, also can be pre-formed the resistor that constitutes with membrane polysilicon, and then form grid.

Figure 86 is the profile by the cmos semiconductor device of twelveth embodiment of the invention.Grid is the single electrode CMOS that constitutes with P+ polysilicon 107, and this is basis of the present invention, and therefore, the same with the foregoing description have low-work voltage, low-power consumption and an effect cheaply.But, in the present embodiment, mos transistor structure constitutes with so-called " double-diffused drain electrode (DDD) " structure, wherein, in source electrode and drain electrode, be provided with the diffusion layer N+103 and the P+104 of high impurity concentration, and and gate overlap, and on source electrode and the drain electrode both sides or only drain electrode one side is provided with the diffusion layer N-142 and the P-143 of low impurity concentration and and gate overlap.The DDD structure is used to guarantee reliability and improves withstand voltage.But, the diffusion layer cover gate of high impurity concentration is arranged, thereby has the advantage that when MOS works, can reduce parasitic capacitance greatly.But the shortcoming of DDD structure is, grid and drain electrode are overlapping, thereby reflectivity (mirror capacity) is big, the result, and this structure is not suitable for high-frequency work.

In Figure 86 illustrated embodiment, only on PMOS 112 1 sides, establish high pressure-resistance structure, and on the NMOS112 both sides, establish high pressure-resistance structure.But,, can select suitable structure to be used for circuit, and needn't consider the conduction type of MOS transistor according to the using method of device in circuit.Usually, direction of current flow be two-way and different situations under source electrode and drain electrode exchange and need under the two-way withstand voltage situation, high pressure-resistance structure is all used in source electrode and drain electrode.On the other hand, be unidirectional and source electrode and drain electrode are the situations of fixing in direction of current flow, have only a side, promptly have only the high pressure-resistance structure of drain electrode one side, with the reduction parasitic capacitance.In addition, in the example shown in Figure 86, grid individual layer P+ polysilicon.But also available P+ sandwich construction is made grid, and is same, all can be elected to be resistor arbitrarily in P-resistor, N-resistor, P+ resistor and the N+ resistor.

Manufacture method described in appropriate combination the foregoing description can constitute the manufacture method of the cmos semiconductor device shown in Figure 86 of twelveth embodiment of the invention.

Figure 87 is the profile by the cmos semiconductor device of thriteenth embodiment of the invention.Grid is the unipolar CMOS that is made of P+ polysilicon 107, and this is basis of the present invention, and therefore the same with the foregoing description have low-work voltage, low-power consumption and an effect cheaply.But, in the present embodiment, adopt such mos transistor structure: in source electrode and drain electrode both sides, or only establish the diffusion layer N-142 and the P-143 of low impurity concentration in drain electrode one side, and establish the diffusion layer N+103 and the P+104 of high impurity concentration, wherein, source electrode and drain electrode or just form certain distance between drain electrode and the grid form field insulating membrane 106 therebetween.Form the thick insulating film of thick several thousand between high impurity concentration diffusion layer and the grid to about 1 μ m.As a result, tangible electric field tension and relaxation effect is arranged, its advantage is that this structure can be born for example tens volts of high working voltages to several hectovolts.But shortcoming is to reduce device size.

In Figure 87 illustrated embodiment, only on the side of PMOS 112, establish high pressure-resistance structure, and on the both sides of NMOS113, establish high pressure-resistance structure.But, according to the using method of device in the circuit, can select to be used for the suitable construction of circuit, and not consider the conduction type of MOS transistor.Usually, direction of current flow be two-way and different situations under source electrode and drain electrode exchange and need under the two-way withstand voltage situation, high pressure-resistance structure is all used in source electrode and drain electrode.On the other hand, be unidirectional and source electrode and drain electrode are the situations of fixing in direction of current flow, have only a side, promptly have only the high pressure-resistance structure of drain electrode one side, with the reduction parasitic capacitance.In addition, in the example shown in Figure 87, grid individual layer P+ polysilicon.But also available P+ sandwich construction is made grid, and is same, all can be elected to be resistor arbitrarily in P-resistor, N-resistor, P+ resistor and the N+ resistor.

The cmos semiconductor device by thriteenth embodiment of the invention shown in Figure 87 can be made like this: when LOCOS forms, promptly when channel stop layer forms, constitute drift (drift) district N-142 and P-143.Afterwards, by the manufacture method of appropriate combination the foregoing description, make this device.

Figure 88 is the profile of the cmos semiconductor device of fourteenth embodiment of the invention.

Grid has the thin film resistor 146 that has CMOS that unipolarity P+ polysilicon 107 constitutes and film metal to constitute, and this is basis of the present invention.

Ni-Cr closes, Cr-SiO alloy, molybdenum silicide or beta-iron silicide oxysome be as the material of film metal 147, and its thickness scope is 100 to 300 .

Be used at film metal under the situation of resistor, compare with the resistor that polysilicon constitutes, its voltage is little to the dependence of resistance value.Therefore, the advantage of the ratio precision that improves resistance value is arranged, its shortcoming is to have limited heat treatment or step in the manufacturing of cmos semiconductor device.Usually, form the back in grid, source electrode and drain electrode and form thin film resistor.

Same as the previously described embodiments, the cmos semiconductor device of fourteenth embodiment of the invention shown in Figure 88 has low-work voltage, low-power consumption and effect cheaply.

As mentioned above, in power control semiconductor device that CMOS and resistor are arranged and simulation semiconductor device, for NMOS and PMOS, the types of conductors of the grid of CMOS all is the P type, because E type PMOS is the surface channel type, therefore short channel and low threshold voltage are possible, because buried channel type NMOS is extremely shallow, therefore, short channel and low threshold voltage are possible, its reason is that the arsenic that diffusion coefficient is little can be used as the impurity of threshold value control, and thin polysilicon or the film metal of polysilicon that the resistor of using in bleeder circuit or the CR circuit is used than grid with its thickness constitutes.Therefore, comparing with the have unipolar CMOS of N+ polysilicon gate or the same polarity grid CMOS identical with grid polarity with raceway groove of routine, is that cost is low, the manufacturing cycle is short, element function is good by the advantage of power control semiconductor device of the present invention or simulation semiconductor device.

Claims

1, a kind of cmos semiconductor device has a N-channel MOS transistor, a P channel MOS transistor and a resistor, and wherein, the conduction type of the transistorized grid of N-channel MOS is the P type, and the conduction type of the grid of P channel MOS transistor is the P type.

2, press the cmos semiconductor device of claim 1, wherein, the P type grid of N-channel MOS transistorized P type grid and P channel MOS transistor comprises the first polysilicon individual layer separately, and this layer has the film thickness scope of 2000 dusts-6000 dust and comprise that impurity concentration is 1 * 10 ¹⁹Atom/cm ³Or higher boron or BF ₂

3, press the cmos semiconductor device of claim 1, wherein, the P type grid of N-channel MOS transistorized P type grid and P channel MOS transistor has a multilayer (polycide) structure separately, this structure comprises the lamination of first polysilicon and first refractory metal silicide, and first polysilicon has the film thickness of 1000 dusts-4000 dust and comprises that impurity concentration is 1 * 10 ¹⁹Atom/cm ³Or higher boron or BF ₂, first refractory metal silicide is selected from following material group: molybdenum silicide, tungsten silicide, titanium silicide and platinum silicide, and the film thickness scope is 500 dusts-2500 dusts.

4, by each cmos semiconductor device among the claim 1-3, wherein, resistor is the polysilicon that forms in the layer identical with first polysilicon that constitutes grid, and has the film thickness scope identical with first polysilicon.

5, by the cmos semiconductor device of claim 1, wherein, resistor is second polysilicon, and its film thickness scope is 500 dusts-2000 dusts.

6, press the cmos semiconductor device of claim 1, wherein, resistor is the film metal resistor that is formed by a kind of material that is selected from the following material group: Ni-Cr alloy, Cr-SiO alloy, molybdenum silicide and beta-iron silicide, and the film thickness scope is 100 dusts-300 dusts.

7, by the cmos semiconductor device of claim 1, wherein, comprise that the impure concentration of resistor packages of first or second polysilicon is 1 * 10 ¹⁴-9 * 10 ¹⁸Atom/cm ³Phosphorus or arsenic, and comprise a N transistor npn npn of low concentration, its film resistor is in the magnitude of a few k Ω/mouth-tens k Ω/mouth.

8, by the cmos semiconductor device of claim 1, wherein, comprise that the impure concentration of resistor packages of first or second polysilicon is 1 * 10 ¹⁹Atom/cm ³Or higher phosphorus or arsenic, and comprising the 2nd N transistor npn npn of higher concentration, its film resistor is in the magnitude of about 100 Ω/mouth-hundreds of Ω/mouth, and its temperature coefficient is in the magnitude of hundreds of ppm/ ℃-Yue 1000ppm/ ℃.

9, by the cmos semiconductor device of claim 1, wherein, comprise that the impure concentration of resistor packages of first or second polysilicon is 1 * 10 ¹⁴-9 * 10 ¹⁸Atom/cm ³Boron or BF ₂, and comprising a P transistor npn npn of low concentration, its film resistor is in the magnitude of a few k Ω/mouth-tens k Ω/mouth.

10, by the cmos semiconductor device of claim 1, wherein, comprise that the impure concentration of resistor packages of first or second polysilicon is 1 * 10 ¹⁹Atom/cm ³Or higher boron or BF ₂, and comprising the 2nd P transistor npn npn of higher concentration, its film resistor is in the magnitude of hundreds of Ω/mouth-Yue 1k Ω/mouth, and its temperature coefficient is in the magnitude of hundreds of ppm/ ℃-Yue 1000ppm/ ℃.

11, press the cmos semiconductor device of claim 1, wherein, N-channel MOS transistor and P channel MOS transistor comprise a MOS transistor with first structure of single drain electrode structure, this structure comprises the diffusion layer with high impurity concentration, and wherein source electrode and drain electrode are with the overlapping P type of planar fashion grid.

12, press the cmos semiconductor device of claim 1, wherein, N-channel MOS transistor and P channel MOS transistor comprise a MOS transistor with second structure, this structure comprises: a diffusion layer with low impurity concentration, wherein have only drain side with planar fashion overlapping P type grid or source side and drain side all with the overlapping P type of planar fashion grid; With a diffusion layer with high impurity concentration, wherein have only drain side not with planar fashion overlapping P type grid or source side and drain side all not with the overlapping P type of planar fashion grid.

13, press the cmos semiconductor device of claim 1, wherein, N-channel MOS transistor and P channel MOS transistor comprise a MOS transistor with the 3rd structure, this structure comprises: a diffusion layer with low impurity concentration, wherein have only drain side with planar fashion overlapping P type grid or source side and drain side all with the overlapping P type of planar fashion grid; Diffusion layer with high impurity concentration, wherein have only drain side not with planar fashion overlapping P type grid or source side and drain side all not with the overlapping P type of planar fashion grid; And a dielectric film, it is between diffusion layer with high impurity concentration and P type grid, and its film thickness is greater than gate insulating film.

14, press the cmos semiconductor device of claim 1, wherein, N-channel MOS transistor and P channel MOS transistor comprise a MOS transistor with the 4th structure, and this structure comprises: a diffusion layer with high impurity concentration, and wherein source electrode and drain electrode are all with the overlapping P type of planar fashion grid; With a diffusion layer with low impurity concentration, wherein have only drain side in further diffusion or source side and all further diffusions on the raceway groove side of drain side on the raceway groove side, thereby by the overlapping P type of planar fashion grid.

15, by the cmos semiconductor device of claim 1, wherein, in the N-channel MOS transistor, the raceway groove that threshold voltage strengthens is buried channel.

16, by the cmos semiconductor device of claim 1, wherein, in the P channel MOS transistor, the raceway groove that threshold voltage strengthens is a surface channel.

17, press the cmos semiconductor device of claim 1, wherein, low impurity concentration diffusion layer in the MOS transistor of the MOS transistor of the MOS transistor of second structure, the 3rd structure and the 4th structure uses arsenic or phosphorus as impurity in the N-channel MOS transistor, and impurity concentration is 1 * 10 ¹⁶-1 * 10 ¹⁸Atom/cm ³, and in the P channel MOS transistor, use boron or BF ₂As impurity, impurity concentration is 1 * 10 ¹⁶-1 * 10 ¹⁸Atom/cm ³High impurity concentration diffusion layer in the MOS transistor of the MOS transistor of the MOS transistor of the MOS transistor of first structure, second structure, the 3rd structure and the 4th structure uses arsenic or phosphorus as impurity in the N-channel MOS transistor, and impurity concentration is 1 * 10 ¹⁶-1 * 10 ¹⁸Atom/cm ³Or higher, and in the P channel MOS transistor, use boron or BF ₂As impurity, impurity concentration is 1 * 10 ¹⁶-1 * 10 ¹⁸Atom/cm ³Or it is higher.

18, a kind of method of making the cmos semiconductor device described in the claim 1,2,4 and 11 may further comprise the steps:

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

On first polysilicon film, form first dielectric film;

Optionally remove first dielectric film on the resistor;

19, a kind of method of making the cmos semiconductor device described in the claim 1 may further comprise the steps:

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

On first polysilicon film, form refractory metal silicide film;

On refractory metal silicide film, form first dielectric film;

On Semiconductor substrate, form the 4th dielectric film;

On the 4th dielectric film, form second polysilicon film;

Second polysilicon film is carried out composition, form resistor;

20, a kind of method of making the cmos semiconductor device described in the claim 1 may further comprise the steps:

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

On first polysilicon film, form high melting point metal film;

On refractory metal silicide film, form first dielectric film;

On Semiconductor substrate, form the 4th dielectric film;

On the 4th dielectric film, form second polysilicon film;

Second polysilicon film is carried out composition, form resistor;

21, a kind of method of making the cmos semiconductor device described in the claim 1 may further comprise the steps:

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

On first polysilicon film, form first dielectric film;

Deposit the 3rd dielectric film on Semiconductor substrate;

Optionally remove first dielectric film on the resistor;

22, a kind of method of making the cmos semiconductor device described in the claim 1 may further comprise the steps:

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

On first polysilicon film, form first dielectric film;

Optionally remove first dielectric film on the resistor area;

Deposit the 3rd dielectric film on Semiconductor substrate;

23, a kind of method of making the cmos semiconductor device described in the claim 1 may further comprise the steps:

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

On first polysilicon film, form first dielectric film;

Deposit the 3rd dielectric film on Semiconductor substrate;

On Semiconductor substrate, form second polysilicon film;

Second polysilicon film is carried out composition, form resistor;

24, a kind of method of making the cmos semiconductor device described in the claim 1 may further comprise the steps:

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

On first polysilicon film, form second dielectric film;

On Semiconductor substrate, form refractory metal silicide film;

Remove second dielectric film of composition;

Deposit the 3rd dielectric film on Semiconductor substrate;

Optionally remove first dielectric film on the resistor;

25, a kind of method of making the cmos semiconductor device described in the claim 1 may further comprise the steps:

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

On first polysilicon film, form second dielectric film;

On Semiconductor substrate, form refractory metal silicide film;

Remove second dielectric film of composition;

Optionally remove first dielectric film on the resistor area;

Deposit the 3rd dielectric film on Semiconductor substrate;

26, a kind of method of making the cmos semiconductor device described in the claim 1 may further comprise the steps:

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

On first polysilicon film, form second dielectric film;

On Semiconductor substrate, form high melting point metal film;

Remove second dielectric film of composition;

Deposit the 3rd dielectric film on Semiconductor substrate;

Optionally remove first dielectric film on the resistor;

27, a kind of method of making the cmos semiconductor device described in the claim 1 may further comprise the steps:

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

On first polysilicon film, form second dielectric film;

On Semiconductor substrate, form high melting point metal film;

Remove second dielectric film of composition;

Optionally remove first dielectric film on the resistor area;

Deposit the 3rd dielectric film on Semiconductor substrate;

28, a kind of method of making the cmos semiconductor device described in the claim 1 may further comprise the steps:

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

On first polysilicon film, form refractory metal silicide film;

On refractory metal silicide film, form first dielectric film;

Deposit the 3rd dielectric film on Semiconductor substrate;

On Semiconductor substrate, form second polysilicon film;

Second polysilicon film is carried out composition, to form resistor;

29, a kind of method of making the cmos semiconductor device described in the claim 1 may further comprise the steps:

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

On first polysilicon film, form high melting point metal film;

On refractory metal silicide film, form first dielectric film;

Deposit the 3rd dielectric film on Semiconductor substrate;

On Semiconductor substrate, form second polysilicon film;

Second polysilicon film is carried out composition, to form resistor;

30, a kind of method of making the cmos semiconductor device described in the claim 1 may further comprise the steps:

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

31, a kind of method of making the cmos semiconductor device described in the claim 1 may further comprise the steps:

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

32, a kind of method of making the cmos semiconductor device described in the claim 1 may further comprise the steps:

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

On Semiconductor substrate, form the 4th dielectric film;

On Semiconductor substrate, form second polysilicon film;

Second polysilicon film is carried out composition, form resistor;

33, a kind of method of making the cmos semiconductor device described in the claim 1 may further comprise the steps:

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

On Semiconductor substrate, form the 4th dielectric film;

On Semiconductor substrate, form second polysilicon film;

Second polysilicon film is carried out composition, in order to form resistor;

34, a kind of method of making the cmos semiconductor device described in the claim 1 may further comprise the steps:

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

On first polysilicon film, form second dielectric film;

On Semiconductor substrate, form refractory metal silicide film;

Remove second dielectric film of composition;

35, a kind of method of making the cmos semiconductor device described in the claim 1 may further comprise the steps:

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

On first polysilicon film, form second dielectric film;

On Semiconductor substrate, form refractory metal silicide film;

Remove second dielectric film of composition;

36, a kind of method of making the cmos semiconductor device described in the claim 1 may further comprise the steps:

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

On first polysilicon film, form second dielectric film;

On Semiconductor substrate, form high melting point metal film;

Remove second dielectric film of composition;

37, a kind of method of making the cmos semiconductor device described in the claim 1 may further comprise the steps:

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

On first polysilicon film, form second dielectric film;

On Semiconductor substrate, form high melting point metal film;

Remove second dielectric film of composition;

38, a kind of method of making the cmos semiconductor device described in the claim 1 may further comprise the steps:

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

On first polysilicon film, form refractory metal silicide film;

On Semiconductor substrate, form the 4th dielectric film;

On Semiconductor substrate, form second polysilicon film;

Second polysilicon film is carried out composition, form resistor;

39, a kind of method of making the cmos semiconductor device described in the claim 1 may further comprise the steps:

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

On first polysilicon film, form refractory metal silicide film;

On Semiconductor substrate, form the 4th dielectric film;

On Semiconductor substrate, form second polysilicon film;

Second polysilicon film is carried out composition, form resistor;

40, a kind of method of making the cmos semiconductor device described in the claim 1,3,5 and 12 may further comprise the steps:

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

On first polysilicon film, form high melting point metal film;

On Semiconductor substrate, form the 4th dielectric film;

On Semiconductor substrate, form second polysilicon film;

Second polysilicon film is carried out composition, form resistor;

41, a kind of method of making the cmos semiconductor device described in the claim 1 may further comprise the steps:

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

On first polysilicon film, form high melting point metal film;

On Semiconductor substrate, form the 4th dielectric film;

On Semiconductor substrate, form second polysilicon film;

Second polysilicon film is carried out composition, form resistor;

42, a kind of method of making the cmos semiconductor device described in the claim 1 may further comprise the steps:

On Semiconductor substrate, form element isolation zone;

On Semiconductor substrate, form gate insulating film;

On Semiconductor substrate, form first polysilicon film;

On first polysilicon film, form refractory metal silicide film;

On refractory metal silicide film, form first dielectric film;

On Semiconductor substrate, form the 4th dielectric film;

On Semiconductor substrate, form second polysilicon film;

Second polysilicon film is carried out composition, form resistor;

43, by the cmos semiconductor device of claim 1, wherein, Semiconductor substrate is the P type semiconductor substrate, and the zone of N-channel MOS transistor and P channel MOS transistor is defined by forming N type trap respectively.

44, press the cmos semiconductor device of arbitrary claim in the claim 1,2,3,11,12,13 and 14, wherein, Semiconductor substrate is the P type semiconductor substrate, and the zone of N-channel MOS transistor and P channel MOS transistor is defined by forming N type trap and P type trap respectively.

45, by the cmos semiconductor device of claim 1, wherein, Semiconductor substrate is the N type semiconductor substrate, and the zone of N-channel MOS transistor and P channel MOS transistor is defined by forming P type trap respectively.

46, by the cmos semiconductor device of claim 1, wherein, Semiconductor substrate is the N type semiconductor substrate, and the zone of N-channel MOS transistor and P channel MOS transistor is defined by forming N type trap and P type trap respectively.

47, press the manufacture method of the cmos semiconductor device of claim 18, wherein, Semiconductor substrate is the P type semiconductor substrate, and the zone of N-channel MOS transistor and P channel MOS transistor is defined by forming N type trap respectively.

48, press the manufacture method of the cmos semiconductor device of arbitrary claim among the claim 18-42, wherein, Semiconductor substrate is the P type semiconductor substrate, and the zone of N-channel MOS transistor and P channel MOS transistor is defined by forming N type trap and P type trap respectively.

49, press the manufacture method of the cmos semiconductor device of claim 18, wherein, Semiconductor substrate is the N type semiconductor substrate, and the zone of N-channel MOS transistor and P channel MOS transistor is defined by forming P type trap respectively.

50, press the manufacture method of the cmos semiconductor device of claim 18, wherein, Semiconductor substrate is the N type semiconductor substrate, and the zone of N-channel MOS transistor and P channel MOS transistor is defined by forming N type trap and P type trap respectively.

51, press the manufacture method of the cmos semiconductor device of claim 18, wherein, the step that forms element isolation zone on Semiconductor substrate realizes by the LOCOS method.

52, press the manufacture method of the cmos semiconductor device of claim 18, wherein, the step that forms element isolation zone on Semiconductor substrate realizes by shallow trench isolation method.

53, by the manufacture method of the cmos semiconductor device of claim 18, wherein, the step of mixing the impurity that is used for threshold value control realizes by ion injection method, and the impurity that is used for the transistorized threshold value control of N-channel MOS is arsenic or phosphorus.

54, by the cmos semiconductor device of claim 1, wherein, first polysilicon film forms by chemical vapor deposition (CVD) method.

55, by the cmos semiconductor device of claim 1, wherein, second polysilicon film forms by chemical vapor deposition method or sputtering method.

56, press the manufacture method of the cmos semiconductor device of claim 18, wherein, first polysilicon film forms by chemical vapor deposition method.

57, press the manufacture method of the cmos semiconductor device of claim 19, wherein, second polysilicon film forms by chemical vapor deposition method or sputtering method.

58, press the manufacture method of the cmos semiconductor device of claim 18, wherein, first p type island region of first polysilicon film forms by the following method: with boron or BF ₂Method for implanting as impurity; With boron as the pre-deposited method in electric furnace of impurity with drive into (drive-in) method; With the molecular layer doping method of boron as impurity.

59, press the manufacture method of the cmos semiconductor device of claim 19, wherein, the step that forms first p type island region of first polysilicon film realizes by chemical vapor deposition method, is used for deposit polysilicon and while doped with boron as impurity.

60, press the manufacture method of the cmos semiconductor device of claim 18, wherein, first dielectric film is the silicon oxide film that forms by chemical vapor deposition method or thermal oxidation process, and has the film thickness of 1000 -2000 .

61, press the manufacture method of the cmos semiconductor device of claim 18, wherein, first dielectric film is the silicon oxide film that forms by chemical vapor deposition method, and has the film thickness of 1000 -2000 .

62, press the manufacture method of the cmos semiconductor device of claim 21, wherein, the lower floor of first dielectric film is the silicon oxide film that forms by chemical vapor deposition method or thermal oxidation process; Its upper strata forms by chemical vapor deposition method; And total film thickness of first dielectric film is 1000 -3000 .

63, press the manufacture method of the cmos semiconductor device of claim 24, wherein, second dielectric film forms by chemical vapor deposition method, and has the film thickness of 1000 -4000 .

64, press the manufacture method of the cmos semiconductor device of claim 21, wherein, the 3rd dielectric film is the silicon oxide film that forms by chemical vapor deposition method, and has total film thickness of 2000 -6000 .

65, by the cmos semiconductor device of claim 1, wherein, refractory metal silicide film forms by chemical vapor deposition method or sputtering method.

66, press the manufacture method of the cmos semiconductor device of claim 19, wherein, refractory metal silicide film forms by chemical vapor deposition method or sputtering method.

67, press the manufacture method of the cmos semiconductor device of claim 20, wherein, refractory metal is cobalt (Co) or the titanium (Ti) that forms by sputtering method, and has the film thickness of 100 -500 .

68, a kind of semiconductor device, wherein, in a reference voltage circuit, the grid of an enhancement mode nmos pass transistor of grid and drain short circuit and drain electrode are connected to the grid and the source electrode of a depletion type nmos transistor of grid and source electrode short circuit, and connected node is as output node, in this circuit, the polarity of the grid of enhancement mode nmos pass transistor and depletion type nmos transistor is the P type.

69, a kind of semiconductor device, wherein, in a reference voltage circuit, the source electrode of an enhancement mode nmos pass transistor of grid and drain short circuit is connected to the drain electrode of a depletion type nmos transistor of grid and source electrode short circuit, and connected node is as output node, in this circuit, the polarity of the grid of enhancement mode nmos pass transistor and depletion type nmos transistor is the P type.

70, a kind of semiconductor device, wherein, in a reference voltage circuit, the grid of an enhancement mode nmos pass transistor of grid and drain short circuit and drain electrode are connected to the source electrode of a depletion type nmos transistor, the source electrode short circuit of the grid of depletion type nmos transistor and enhancement mode nmos pass transistor, and connected node is as output node, and in this circuit, the polarity of the grid of enhancement mode nmos pass transistor and depletion type nmos transistor is the P type.

71, a kind of semiconductor device, wherein, in a reference voltage circuit, the drain electrode of a depletion type nmos transistor of grid and source electrode short circuit is connected to first enhancement mode PMOS transistor drain and grid, and the transistorized source electrode of the first enhancement mode PMOS is connected to a power supply; The second enhancement mode PMOS transistor drain is connected to the grid and the drain electrode of the short circuit of an enhancement mode nmos pass transistor, and the transistorized source electrode of the second enhancement mode PMOS is connected to a power supply, and its grid is typically connected to the first enhancement mode PMOS transistor; And connected node is as output node, and in this circuit, the polarity of the grid of enhancement mode nmos pass transistor and depletion type nmos transistor is the P type.

72, a kind of semiconductor device, wherein, in a reference voltage circuit, the drain electrode of first depletion type nmos transistor of grid and source electrode short circuit is connected to the grid and the source electrode of second depletion type nmos transistor of grid and source electrode short circuit; The drain electrode of second depletion type nmos transistor is connected to a power supply; The source electrode of first depletion type nmos transistor is connected to an enhancement mode nmos pass transistor of grid and drain short circuit; And connected node is as output node, and in this circuit, the polarity of the grid of enhancement mode nmos pass transistor, first depletion type nmos transistor and second depletion type nmos transistor is the P type.

73, a kind of semiconductor device, wherein, in a reference voltage circuit, the grid of an enhancement mode nmos pass transistor of grid and drain short circuit and drain electrode are connected to the source electrode of first depletion type nmos transistor, and the grid of first depletion type nmos transistor is connected to the source electrode of enhancement mode nmos pass transistor; The drain electrode of first depletion type nmos transistor is connected to the grid and the source electrode of second depletion type nmos transistor of grid and source electrode short circuit; The drain electrode of second depletion type nmos transistor is connected to a power supply; The connected node of the source electrode of the drain electrode of enhancement mode nmos pass transistor and first depletion type nmos transistor is as output node, in this circuit, the polarity of the grid of enhancement mode nmos pass transistor, first depletion type nmos transistor and second depletion type nmos transistor is the P type.