CN1354513A - Radiating structure for semiconductor device - Google Patents
Radiating structure for semiconductor device Download PDFInfo
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- CN1354513A CN1354513A CN00132444A CN00132444A CN1354513A CN 1354513 A CN1354513 A CN 1354513A CN 00132444 A CN00132444 A CN 00132444A CN 00132444 A CN00132444 A CN 00132444A CN 1354513 A CN1354513 A CN 1354513A
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- radiator
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
A structure for heat sinking includes a heat-sinking body made of heat conductivity metal. The heat-sinking body has an exposed outer surface that covers the surface of encapsulation glue. There are multi continuous notches with incremental depth on the fringe of outer surface from inner to other. These notches slow up the fluidity of encapsulating resin so as to prevent resin from overflow produced on outer surface of the heat-sinking body. Also it increases path for moisture to enter to, thus the reliability of semiconductor chip is raised.
Description
The present invention relates to a kind of radiator structure, relate to a kind of radiator structure that is used for semiconductor device with the heat that semiconductor wafer was produced in effective loss semiconductor device especially.
Along with improving constantly of the performance of semiconductor device, the heat that semiconductor wafer (SemiconductorChip) is produced is many more, thereby the heat how effective loss semiconductor wafer is produced is into a big problem with the reliability (Reliabilty) of guaranteeing manufactured goods.For solving the heat dissipation problem of semiconductor device, traditionally, be used in to connect on the semiconductor device more and establish a fin (Heat Sink) or radiating block (Heat Block), or in semiconductor device, install a fin or radiating block, or pass through the modes such as surface of semiconductor device with cooling air or liquid (Cooled Air or Liquid).And the raising of radiating efficiency then must take into account the increase of area of dissipation and the shortening of heat dissipation path.Therefore, the structure that can effectively improve radiating efficiency should be a surface exposed packing colloid (Encapsulant orPackage Body) that goes out semiconductor device of the fin that makes installing in the semiconductor device or radiating block, so that the heat that semiconductor wafer produces can be by the direct loss of exposed surface of good fin of thermal diffusivity or radiating block to atmosphere or be external in the radiator structure on this exposed surface.
Yet, because fin or radiating block are made by dashing the mode of cutting (Stamping), the angle end at its edge tends to form the fillet phenomenon when being whittled into type dashing, so in mold pressing (Molding) manufacture process, easily overflow causes and produces glue (Flash) phenomenon of overflowing to fin or exposed heat surface mobile good potting resin (Encapsulating Resin or MoldingCompound) by the angle end of corners.The generation of the glue phenomenon of overflowing and can not make the exposed surface flatness (Planarity) of this fin or radiating block good and can't effectively engage with external radiator structure except that meeting reduces the area of dissipation of exposed surface.Though overflow to the potting resin on the exposed surface can be removed with processing modes such as sandblast, laser, yet the reprocessing of this kind physical property (Post-treatment) not only can increase the complexity of manufacturing cost and manufacture process, also undermines semiconductor device itself easily.
Aforementioned for solving with the problem that is produced on the structure, so propose a kind of semiconductor device of tool fin.As shown in Figure 6, this known semiconductor device has a fin 16, the end face of this fin 16 exposes outside the surface of packing colloid 17, and its edge is provided with a recess 16a for the potting resin filling wherein, to prevent that the potting resin overflow is to the end face of this fin 16 and form the glue phenomenon of overflowing.Yet, though the potting resin that enters among this recess 16a makes viscosity increased and reduces mobile because of the heat that is easy to absorb mould, but because of the bottom surface of recess 16a is flat condition and very brief, the effect that viscosity increases is not showing, and makes the still low and mobile still good potting resin of part viscosity still can overflow cause excessive glue to the end face of fin 16.Because structure shown in Figure 6 fails effectively to solve the generation of the glue that overflows, so propose another kind of known semiconductor device.This kind lays one by silver in the recess 16a of this fin 16, the semiconductor device of the coat of metal 31 that platinum or fellow constitute, as shown in Figure 7, the adherence between this coat of metal 31 and potting resin is lower than the adherence between fin 16 and potting resin, thereby, remove the glue that overflows and be easier to.Yet, in the recess 16a of fin 16, lay the complexity that this coat of metal 31 not only increases manufacturing cost and processing procedure again, and still fail effectively to solve excessive glue problem.
The purpose of this invention is to provide and a kind ofly can effectively solve the glue problem of overflowing, and can not increase the complexity of manufacturing cost and manufacture process, and provide than long path, the degree of difficulty that moisturizes and invade, because of the moisture invasion generation of delamination is arranged and reduce semiconductor device, so that the effectively outside radiator structure of loss of the heat that semiconductor wafer produced in the semiconductor device.
Take off in the present invention and other purpose for reaching, the radiator structure that is used for semiconductor device of the present invention is made of the good metal radiator of a thermal conductivity (Heat-dissipating Body); This radiator has an outer surface that exposes outside in the semiconductor device in order to the surface of the packing colloid that coats semiconductor wafer, then be formed with from inside to outside in the edge of this outer surface a plurality of continuously and the recess that increases progressively of the degree of depth.
At least be formed with two recesses that join on this outer surface edge, and each concave depth (outer surface that is radiator is to the distance between the recess bottom surface) is increased progressively from interior outward by this radiator outer surface, so that when inwardly flowing in this recess by the radiator edge, can flow into earlier the recess of degree of depth maximum, absorb the heat of encapsulating mould and increase viscosity and slow down flowability; After entering the inferior big recess of the degree of depth, potting resin can continue to absorb the heat of encapsulating mould, but because of concave depth diminishes, the flow path of potting resin also diminishes, and the effect that heat absorption back viscosity is increased becomes greatly, so can further slow down the flowability of potting resin.Thereby, wait potting resin stream to support when being positioned at the most inboard recess, the flowability of potting resin slowed down to potting resin can't overflow degree to the outer surface of radiator, so do not have the generation of excessive glue.For effectively reaching the purpose of the glue that prevents to overflow, the width sum total of these a plurality of recesses should be 0.6 to 1.5mm, and with 1.0 to 1.3mm more suitable, its depth capacity then should be 0.05 to 0.15mm, and more suitable with 0.10 to 0.13mm.In addition, wantonly two adjacent concave depth differences need not be identical.
This radiator structure should be directly bonding with semiconductor wafer, or separate with semiconductor wafer.
Fig. 1 is the front elevation of first embodiment of the invention;
Fig. 2 is the cutaway view that Fig. 1 cuts open along the 2-2 line;
Fig. 3 is that first embodiment of the invention is installed in the cutaway view in the semiconductor device;
Fig. 4 is that second embodiment of the invention is installed in the cutaway view in the semiconductor device;
Fig. 5 is that third embodiment of the invention is installed in the cutaway view in the semiconductor device;
Fig. 6 is a kind of cutaway view of known semiconductor device; And
Fig. 7 is the cutaway view of another kind of known semiconductor device.
As shown in Figures 1 and 2, the radiator structure of first embodiment of the invention is constituted with the made en plaque radiator 100 of the good metal of thermal conductivity (as copper, aluminium etc.) by one, make this radiator 100 have an outer surface 101 that exposes outside in the semiconductor device surface (its structure is specified in the back with conjunction with figs.) in order to the packing colloid that coats semiconductor wafer, and be formed with three degree of depth in the edge of this outer surface 101 by the first recess 102a, the second recess 102b, the 3rd recess 102c that the outer surface 101 of radiator 100 increases progressively from inside to outside, make this; Width and the W of the first recess 102a to the, three recess 102C are about 1.2mm, and its depth capacity D (distances of outer surface 101 to the 3rd recess 102c bottom surfaces) then is about 0.12mm.Because each concave depth is all little, so when this radiator 100 is cut the mode moulding to dash, the angle end of each recess angle end and outer surface 101 and the first recess 102a joint does not have excessive fillet and produces, and the effect of retardance overflow can be provided, to prevent the generation of excessive glue phenomenon.
Be illustrated in figure 3 as first embodiment of the invention and be installed in cutaway view in the semiconductor device.The semiconductor wafer 110 of this semiconductor device is bonded on the inner surface 103 of this radiator 100 with respect to its outer surface 101 with elargol 120, simultaneously, the lower surface 131 of lead foot 130 also adheres on the lateral margin of inner surface 103 of this radiator 100 with adhesive 140, so that semiconductor wafer 110 is radiator 100 good supporting with lead foot 130 for the position that gold thread 150 welds, thereby when the bonding wire operation of welding gold thread 150, can guarantee the quality of welding semiconductor wafer 110 to be connected to conductively on the upper surface 132 of this lead foot 130 by gold thread 150.After finishing the bonding wire operation, coat this semiconductor wafer 110 with potting resin, gold thread 150, lead foot 130 is near the part of semiconductor wafer 110, and the part of this radiator 100.After this potting resin curing molding is packing colloid 160, the outer surface 101 of this radiator 100 promptly can expose outside the surface of this packing colloid 160, so that the heat transferred that semiconductor wafer 110 produces is to radiator 100, again by the outer surface 101 direct loss that expose outside packing colloid 160 to atmosphere or another be external to heat sink (not shown) on this outer surface 101, and reach the purpose of efficiently radiates heat.
The outer surface 101 of this radiator 100 is when molding operation, directly amplexiform to the bottom surface (not shown) of the die cavity of encapsulating mould, therefore, when potting resin mould stream flows in the 3rd recess 102C of this radiator 100, can directly absorb the heat that reaches by the die cavity bottom surface and viscosity is uprised, and slow down flowability; When potting resin mould stream moves on and flows in the second recess 102b, potting resin can continue to absorb the heat of encapsulating mould, but because of the degree of depth of the second recess 102b less than the 3rd recess 102c, the effect that the flow path of potting resin is diminished and make potting resin heat absorption back viscosity increase becomes big, causes its flowability further to be slowed down; In like manner, the viscosity that enters the potting resin behind the first recess 102a can increase once again, mobile than it in the second recess 102b time for slow, the potting resin of reaching to the first recess 102a is fully slowed down because of flowability, and be not enough to overflow to the outer surface 101 of this radiator 100, so there is not the anxiety of the glue that overflows.In the mold pressing manufacture process, can not produce the glue phenomenon of overflowing on the outer surface 101 of radiator 100, except that the area of dissipation that can guarantee outer surface 101, also can keep the flatness of outer surface 101, engage with the heat sink of another external usefulness effectively.Simultaneously, do not have the generation of the glue phenomenon of overflowing, then need not after molding operation is finished, must bestow the reprocessing of the excessive glue of any removal, reduced manufacturing cost, and improved the qualification rate of manufactured goods the outer surface 101 that exposes.In addition, the first recess 102a, being provided with of the second recess 102b and the 3rd recess 102c can form a longer path, increases extraneous aqueous vapor and invades difficulty to the semiconductor device, take place because of the problem that the aqueous vapor invasion produces delamination and reduce semiconductor device, so can improve the manufactured goods reliability.
The person is installed in cutaway view in second half conductor means for second embodiment of the invention as shown in Figure 4.The radiator 100 of this second embodiment ' be different from first embodiment be in this radiator 100 ' edge system be formed with the support portion 104 of downward bending ', with utilize this support portion 104 ' make radiator 100 ' a stay at ball grid array (BGA) substrate 170 ' on; Thereby, when semiconductor wafer 110 ' with elargol 120 ' adhere to ball grid array base plate 170 ' on, and with gold thread 150 ' conduction connect this semiconductor wafer 110 ' with this ball grid array base plate 170 ' on after the conductor wire (not shown) laid, this radiator 100 ' be positioned at semiconductor wafer 110 ' the top and this semiconductor wafer 110 of its inner surface 103 ' can not touch ' reach gold thread 150 '.Thereby, with this semiconductor wafer 110 of packing colloid 160 ' coating ', gold thread 150 ', ball grid array base plate 170 ' upper surface and the part radiator 100 ' after, this radiator 100 ' this packing colloid 160 of outer surface 101 ' still can expose outside ' the surface, and radiator 100 ' the first recess 102a ', the second recess 102b ' and the 3rd recess 102c ' still can effectively prevent potting resin overflow glue to outer surface 101 ' on.
The person is installed in cutaway view in second half conductor means for the third embodiment of the present invention as shown in Figure 5.The radiator 100 of the 3rd embodiment " with its inner surface 103 " connects and places on the wafer holder 180 " bottom surface 181 ", to go up bonding semiconductor wafer 110 on " after going up; this semiconductor wafer 110 " heat that is produced must via wafer holder 180 " is passed to this radiator 100 ", again by directly outwards loss to atmosphere or on another external heat sink of radiator 100 " outer surface 101 " in this wafer holder 180 " end face 182 ".Same, in order to the flowability of curing molding for the potting resin mould stream that coats this semiconductor wafer 110 " packing colloid 160 ", when molding operation, can be radiator 100 " the formed first recess 102a in edge ", the second recess 102b " and the 3rd recess 102c " institute slows down, and unlikely overflow to radiator 100 " outer surface 101 " is gone up and produced the glue phenomenon of overflowing.
Notice, above-mentioned specific embodiment is only in order to further specify characteristics of the present invention and effect, but but not in order to limit practical range of the present invention, so under the spirit that does not break away from the present invention's announcement, the equivalence that any utilization technological means of the present invention is finished changes and modifies still to be contained by claim of the present invention.
Claims (19)
1. radiator structure that is used for semiconductor device, the metal radiator good by a thermal conductivity constituted, this radiator has an outer surface that exposes outside in the semiconductor device in order to the surface of the packing colloid that coats semiconductor wafer, then be formed with from inside to outside at the edge of this outer surface a plurality of continuously and the recess that increases progressively of the degree of depth.
2. radiator structure as claimed in claim 1, wherein, the edge of this outer surface has at least two recesses that are formed with different depth and join.
3. radiator structure as claimed in claim 2, wherein, the edge of this outer surface have three join and the degree of depth from the interior recess that increases progressively outward.
4. radiator structure as claimed in claim 1, wherein, this radiator is by copper, and aluminium or metalloid and alloy thereof are made.
5. radiator structure as claimed in claim 1, wherein, the support portion that the edge of this radiator is connected as a single entity in addition.
6. radiator structure as claimed in claim 1, wherein, the width summation of these a plurality of recesses is 0.6 to 1.5mm, the degree of depth then is 0.06 to 0.15mm.
7. radiator structure as claimed in claim 6, wherein, the width summation of these a plurality of recesses is preferably 1.0 to 1.3mm, and the degree of depth is preferably 0.10 to 0.13mm.
8. the semiconductor device of a tool radiator comprises:
Semiconductor wafer;
A plurality of lead foots are connected with this semiconductor wafer conduction by conducting element, and
The radiator that is connected with this semiconductor wafer, this radiator has one and exposes outside in order to coat this semiconductor wafer, the outer surface of packing colloid of the radiator of part and the lead foot of part, and the edge of this outer surface be formed with from inside to outside a plurality of continuously and the recess that increases progressively of the degree of depth.
9. semiconductor device as claimed in claim 8, wherein, the edge of this outer surface has at least two recesses that are formed with different depth and join.
10. semiconductor device as claimed in claim 9, wherein, the edge of this outer surface have three join and the degree of depth from the interior recess that increases progressively outward.
11. semiconductor device as claimed in claim 8, wherein, this radiator is by copper, and aluminium or metalloid and alloy thereof are made.
12. semiconductor device as claimed in claim 8, wherein, the width summation of these a plurality of recesses is 0.6 to 1.5mm, and the degree of depth then is 0.06 to 0.15mm.
13. as the semiconductor device of claim 12, wherein the width summation of these a plurality of recesses is preferably 1.0 to 1.3mm, and the degree of depth is preferably 0.10 to 0.13mm.
14. the BGA semiconductor device of a tool radiator comprises,
Semiconductor wafer;
One BGA substrate for this semiconductor wafer adhesion, this semiconductor wafer forms conductivity by conducting element with the BGA substrate and is connected; And
One connects the radiator that places on this BGA substrate, this radiator has one and exposes outside in order to coat this semiconductor wafer, the outer surface of the packing colloid of the radiator of the BGA substrate of part and part, the edge of this outer surface is formed with a plurality of continuous and recess that the degree of depth increases progressively and the support portions that are connected as a single entity from inside to outside, so that this radiator is positioned at the top of semiconductor wafer by the support of this support portion.
15. as the BGA semiconductor device of claim 14, wherein, the edge of this outer surface has at least two recesses that are formed with different depth and join.
16. as the BGA semiconductor device of claim 15, wherein, the edge of this outer surface have three join and the degree of depth from the interior recess that increases progressively outward.
17. as the BGA semiconductor device of claim 14, wherein, this radiator is by copper, aluminium or metalloid and common alloy are made.
18. as the BGA semiconductor device of claim 14, wherein, the width summation of these a plurality of recesses is 0.6 to 1.5mm, the degree of depth then is 0.06 to 0.15mm.
19. as the BGA semiconductor device of claim 18, wherein, the width summation of these a plurality of recesses is preferably 1.0 to 1.3mm, and the degree of depth is preferably 0.10 to 0.13mm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN001324446A CN1216421C (en) | 2000-11-17 | 2000-11-17 | Radiating structure for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN001324446A CN1216421C (en) | 2000-11-17 | 2000-11-17 | Radiating structure for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1354513A true CN1354513A (en) | 2002-06-19 |
| CN1216421C CN1216421C (en) | 2005-08-24 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN001324446A Expired - Lifetime CN1216421C (en) | 2000-11-17 | 2000-11-17 | Radiating structure for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1216421C (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7361590B2 (en) | 2005-01-20 | 2008-04-22 | Nissan Motor Co., Ltd. | Semiconductor device and manufacturing method thereof |
| CN101752327B (en) * | 2008-12-01 | 2011-11-16 | 矽品精密工业股份有限公司 | Semiconductor packaging piece with heat dissipation structure |
| CN102736299A (en) * | 2011-04-11 | 2012-10-17 | 株式会社日立显示器 | Manufacture method for display device |
| CN114582815A (en) * | 2022-05-05 | 2022-06-03 | 甬矽电子(宁波)股份有限公司 | Heat dissipation cover, packaging structure and manufacturing method of packaging structure |
-
2000
- 2000-11-17 CN CN001324446A patent/CN1216421C/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7361590B2 (en) | 2005-01-20 | 2008-04-22 | Nissan Motor Co., Ltd. | Semiconductor device and manufacturing method thereof |
| CN101752327B (en) * | 2008-12-01 | 2011-11-16 | 矽品精密工业股份有限公司 | Semiconductor packaging piece with heat dissipation structure |
| CN102736299A (en) * | 2011-04-11 | 2012-10-17 | 株式会社日立显示器 | Manufacture method for display device |
| CN102736299B (en) * | 2011-04-11 | 2015-06-24 | 株式会社日本显示器 | Manufacture method for display device |
| CN114582815A (en) * | 2022-05-05 | 2022-06-03 | 甬矽电子(宁波)股份有限公司 | Heat dissipation cover, packaging structure and manufacturing method of packaging structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1216421C (en) | 2005-08-24 |
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