CN1353523A - Switch network card tester and method - Google Patents
Switch network card tester and method Download PDFInfo
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- CN1353523A CN1353523A CN 00132884 CN00132884A CN1353523A CN 1353523 A CN1353523 A CN 1353523A CN 00132884 CN00132884 CN 00132884 CN 00132884 A CN00132884 A CN 00132884A CN 1353523 A CN1353523 A CN 1353523A
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Abstract
A tester for switching network board is composed of information cell transceiving detector for receiving the cell data initialized by a central processing system and forwarding it to the board to be tested, central processing system and at least one repeater circuit. After the said cells are switched by the board to be tested, they are input to the repeater circuit for retransmitting them to the unit to be tested until all channels are tested. Its advantages include simple structure, high efficiency, low cost and high correctness of result.
Description
The present invention relates to a kind of switch network card tester and method, especially for the functional test of the network board in the asynchronous transfer mode ATM broadband packet trade-to product.
Along with the continuous increase of transmission rate, exchange capacity, it is complicated day by day that the design of ATM broadband packet trade-to product becomes, thereby the production test of this class broadband trade-to product also is faced with increasingly serious challenge.
What complex circuit designs degree height, test were comparatively difficult in the broadband packet trade-to product is switching network veneer part.Fig. 1 is the composition schematic diagram of network board.
The interchange channel of network board always links to each other with the All other routes interface board high speed transceiver channel of switch by High speed rear panel in the broadband switching system.Under the certain situation of switch architecture size, exchange capacity is big more, and interchange channel quantity is just many more, and the backboard data transmission rate may be just high more.At present, because stencil channel is many, operating rate too high (hundreds of million is to last gigabit), mostly the industry production line is to adopt sub-frame testing equipment (HOT MOCKUP mode) to carry out to the functional test of web plate.This equipment mainly partly is made up of switch minimum system, special ATM tester, control terminal etc.The switch minimum system partly is made up of machine frame, tool palette (the intrinsic veneer of switch) and Board Under Test etc.Common method of testing is: control terminal carries out necessary configuration and initialization to switch system tool palette, Board Under Test, ATM instrumentation, provide test data by tester to the exchange service mouth, after switch the switch interchange channel, test data is sent the receiving unit of tester back to through the functional area, judge by tester whether current Channel Exchange is normal.By the different test data of control terminal configuration, allow it travel through testable passage, reach the test purpose of Channel Exchange function.
There is following shortcoming in above-mentioned existing measuring technology: 1) adopt sub-frame method of testing to require according to the exchange capacity of tested network board the test macro full configuration to be put, and then increase the production test operation complexity.2) the test process manual intervention is many, has reduced testing efficiency, the test request that is not suitable for producing in enormous quantities.3) adopted numerous tool palettes after, the fault location difficulty increases.4) space of raising single-board testing coverage rate is less, has the test leakage problem.5) existing ATM tester only provides the test port of some standards, is fit to the complete machine index test, and functional localization is poor.Price is very expensive in addition, and the batch testing cost is very high.
Purpose of the present invention is exactly in order to overcome the above problems, and a kind of switch network card tester and method are provided, and simple, efficient, test result is accurate, and cost is low.
For achieving the above object, the present invention proposes a kind of switch network card tester and a kind of network board method of testing.
Wherein testing apparatus comprises cell transmitting-receiving testing circuit, transmission, the receiving terminal of this cell transmitting-receiving testing circuit link to each other with reception, a sendaisle of Board Under Test by high-speed interface respectively, it is characterized in that: also be provided with central processing system and at least one repeat circuit; Described central processing system links to each other with cell transmitting-receiving testing circuit, and cell transmitting-receiving testing circuit receives and is sent to Board Under Test through the initialized cell data of central processing system and by high-speed interface; Repeat circuit also links to each other with high-speed interface with central processing system, and links to each other with Board Under Test by high-speed interface, and the cell Transmitting and Receiving End of each repeat circuit is corresponding with a transmission, the receive path of Board Under Test separately.
Method of testing may further comprise the steps:
1, central processing system initialization cell data wherein includes the channel number sign, is used to indicate Board Under Test to exchange;
2, cell transmitting-receiving testing circuit receives initialized data, and sends to a receive path of Board Under Test;
3, repeat circuit receives from Board Under Test and the cell data that exchanged through Board Under Test, and resends Board Under Test after adding new channel number sign on this cell data;
4, another repeat circuit receives from Board Under Test and the cell data that exchanged through Board Under Test once more, and resends Board Under Test once more after adding new channel number sign on this cell data;
5, repeat above-mentioned steps 4, up to the interchange channel that cell has been tested through all desires of Board Under Test;
6, when the sendaisle of the cell interchange channel that last desire is surveyed from Board Under Test is got back to test board, cell transmitting-receiving testing circuit receives this cell data, and compares detection.
Owing to adopted above scheme, increased the repeat circuit design, make data flow to dispose arbitrarily.Before the test, control terminal initialization repeat circuit route makes it to realize that test data stream can run through the passage that Board Under Test need be tested, and finishes the automatic test of interchange channel.Final interchange channel quality is judged by the transmitting-receiving testing circuit.Can realize test result accurately simply, efficiently like this, be difficult for omitting, because circuit is simple, so cost is low.
Fig. 1 is the network board schematic diagram.
Fig. 2 is the composition frame chart that utilizes test macro of the present invention.
Fig. 3 is that testing apparatus of the present invention is formed schematic diagram.
Fig. 4 is a cell transmitting-receiving testing circuit composition frame chart.
Fig. 5 is the repeat circuit theory diagram.
Fig. 6 is a test information cells data flow diagram in the test process.
Fig. 7 is the further refinement figure that testing apparatus of the present invention is formed schematic diagram.
Also the present invention is described in further detail in conjunction with the accompanying drawings below by specific embodiment.
See Fig. 2, this figure is the schematic diagram that utilizes test macro of the present invention to test, and " test board " promptly is testing apparatus of the present invention among the figure, is the part of this test macro most critical.Board Under Test and test board directly dock by connector, guarantee the integrality of interface high speed signal.Control terminal is tested Board Under Test automatically by control interface (network interface or serial ports) control test board.
The design of testing apparatus of the present invention (being the test board among Fig. 2) is formed as shown in Figure 3.It by central processing system 2 (for the ease of reading, and meet the custom of this professional skill field, be referred to as cpu system below again, for RAM, FIFO etc. also with), control interface, repeat circuit T0-Tn, cell transmitting-receiving testing circuit 1, high-speed interface etc. partly form.Transmission, the receiving terminal of cell transmitting-receiving testing circuit 1 link to each other with reception, a sendaisle of Board Under Test by high-speed interface respectively; Described cpu system 2 is by interface and control terminal communication, and links to each other with cell transmitting-receiving testing circuit 1, and 1 reception of cell transmitting-receiving testing circuit is sent to Board Under Test through cpu system 2 initialized cell datas and by high-speed interface; Repeat circuit T0-Tn also links to each other with high-speed interface with cpu system 2, and links to each other with Board Under Test by high-speed interface, each repeat circuit T0 or T1 or T2 ... or the cell Transmitting and Receiving End of Tn is corresponding with a transmission, the receive path of Board Under Test separately.(subscript n is a natural number)
Cpu system is the fundamental system that cpu bus externally is provided that chips such as a cpu chip and peripheral RAM, ROM, interface are formed.The CPU model can be the i386EX of INTEL or the MPC860 of MOTOROLA.
Cell transmitting-receiving, testing circuit are used for testing tested stencil channel function of exchange, can adopt the SPARTENXL Series FPGA (figure below dotted portion) of XILINX company and peripheral cell-buffering DPRAM (dual port RAM) to realize.Cell transmitting-receiving, testing circuit 1 design principle are as shown in Figure 4.It comprises that cell sends buffer memory, transmission logical circuit, cell reception buffer memory, receive logic circuit and detection module; Send logic and link to each other with high-speed interface with receive logic, correspond respectively to a receive path and a sendaisle on the Board Under Test, the two sends buffer memory by cell respectively again and links to each other with cpu system 2 with cell reception buffer memory; Detection module then receives buffer memory with cell transmission buffer memory, transmission logical circuit, cell respectively, the receive logic circuit is connected.Wherein detection module comprise relatively patrol add, cell transmitting counter, cell count pick up device, wrong cell counter and cyclic redundancy check (CRC) counter, their in parallel or series connection can simultaneously or be carried out multiple detection so successively.
The operation principle of above-mentioned cell transmitting-receiving, testing circuit 1 is as follows: the transmitting-receiving buffer memory is made up of dual port RAM.Cpu system 2 first initialization send buffer memory, are ready to cell data.Start the transmission logic then formative cell data is sent, start Compare Logic and cell simultaneously and send counting.Cell data is got back to receiving terminal after through interchange channel and forwarding logic circuit.Receive logic on one side deposits cell of data in the reception buffer memory, sends into comparison circuit and comparison circuit on one side and compares from the cell data that sends buffer memory and read, and receives cell count and wrong cell and counts.Also to carry out cell CRC check (cyclic redundancy check (CRC)) and crc error counting simultaneously in transmitting-receiving to data.In addition, cpu system 2 also can report control terminal analysis to the cell data that receives in the buffer memory.
The design principle of repeat circuit T0-Tn as shown in Figure 5.Repeat circuit partly is made up of asynchronous receiving-transmitting FIFO (being fifo registers), channel number flag register (being used for the cell route indication inserts), CRC16 verification, transmitting-receiving cell counter, receive logic circuit, transmission logical circuit etc., with the FPGA realization of XILINX.Receive logic circuit, transmission logical circuit, channel number flag register three all link to each other with cpu system 2; The receive logic circuit is corresponding with a sendaisle of Board Under Test, and it is corresponding with a receive path of Board Under Test to send logical circuit, and the output of channel number flag register links to each other with the transmission logical circuit.The count pick up device links to each other with the receive logic circuit, and transmitting counter links to each other with the transmission logical circuit, and asynchronous first-in first-out register FIFO links to each other with the output of receive logic circuit and the input of transmission logical circuit respectively, as the buffer storage between the two; The input of checking circuit links to each other with asynchronous first-in first-out register FIFO, and output links to each other with the transmission logical circuit.
Repeat circuit is by cpu system 2 controls.Packet-switched data Bao Jun contains gap marker or routing address.This circuit by cpu system 2 first initialization channel number signs, was inserted into during transmission in the format cell data that sends logic formation before work automatically.The crc value of real-time operation also inserts in the cell flow automatically in addition.Tested web plate can exchange to corresponding passage output according to gap marker after receiving cell data, sends the forwarding receive logic back to through high-speed interface.Asynchronous FIFO is used for buffered data, solves the offset issue of transmitting-receiving speed.More than design is finished the passway of test information cells data on Board Under Test by quick selection, realizes test fast.Send at cell and to count simultaneously, also count during reception, be convenient to CPU repeat circuit is debugged, also can judge when prepass work whether normal, the same with the counter effect in the detecting unit.
Receive and dispatch the parallel/serial and serial/parallel conversion that interface is mainly finished the High speed rear panel signal at a high speed, realize by the S2064A or the S2067A chip of AMCC company.
High speed circuit such as the repeat circuit among the present invention, cell transmitting-receiving, testing circuit also can be realized by CPLD, the VIRTEXE series programming device of XILINX company or the APEX series programming device of ALTERA company.
The application of repeat circuit T0-Tn brings great convenience to lane testing.According to the test needs, test board repeat circuit T0-Tn can be configured to following several test mode before the test: 1) any passage is carried out conversation test, for example the n Channel Exchange is to the n+i passage; 2) any a plurality of passages runs through test; 3) all passages are once finished test, as 0 passage to 1 passage, 1 passage to 2 passages, n passage to n+1 passage etc.Various test modes include following steps:
1) central processing system 2 initialization cell datas wherein include the channel number sign, are used to indicate Board Under Test to exchange; 2) cell transmitting-receiving testing circuit 1 receives initialized data, and sends to a receive path of Board Under Test; 3) repeat circuit T0 or T1 or T2 ... or Tn receives from Board Under Test and the cell data that exchanged through Board Under Test, and resends Board Under Test after adding new channel number sign on this cell data; 4) another repeat circuit T0 or T1 or T2 ... or Tn receives from Board Under Test and the cell data that exchanged through Board Under Test once more, and resends Board Under Test once more after adding new channel number sign on this cell data; 5) repeat above-mentioned steps 4, up to the interchange channel that cell has been tested through all desires of Board Under Test; 6) when the sendaisle of the cell interchange channel that last desire is surveyed from Board Under Test is got back to test board, cell transmitting-receiving testing circuit 1 receives this cell data, and compares detection.
If once finish all tests, can utilize repeat circuit (T0 or T1 or T2 ... or Tn) adds different channel number signs when transmitting at every turn, make test information cells can travel through all passages.Fig. 6 is a cell data flow diagram of once finishing all lane testings.Heavy line is a data flow, sends from the n+1 passage, gets back at last and works as prepass.Owing to adopted the repeat circuit design, made data flow to dispose arbitrarily.Before the test, control terminal initialization repeat circuit route makes it to realize that test data stream can run through the passage that Board Under Test need be tested, and finishes the automatic test of interchange channel.Final interchange channel quality is judged by the transmitting-receiving testing circuit.
The content that 1 pair of cell through exchange of cell transmitting-receiving testing circuit compares detection comprises: send cell at first and the comparison of the cell that finally receives, the cell transmission counts and the comparison of cell count pick up, the counting and the cyclic redundancy check (CRC) of wrong cell.
Not only in cell transmitting-receiving testing circuit 1, can detect cell, at repeat circuit T0 or T1 or T2 ... or add on the Tn test information cells data that new channel number sign is laid equal stress on and newly send in the process of Board Under Test, also can carry out verification, send counting and count pick up, only need in repeat circuit, to increase related circuit and get final product.
In sum, major advantage of the present invention is as follows:
1) owing to solved transmitting-receiving and the detection technique problem of high-speed information element data, realized the broadband The plate level functional test of trade-to product;
2) plate level functional test coverage enlarges, and has at utmost solved ICT or other tests The test leakage problem that means are left over and mistake survey problem have guaranteed test mass;
3) the measurand fault location is accurate, brings convenience to maintenance;
4) it is many to have broken through the intrinsic TCH test channel of measurand, test obstacle that data transmission rate is high, Realized high efficiency automatic test;
5) the testing equipment cost is low, forms simply convenient operation.
Claims (10)
1, a kind of switch network card tester, comprise cell transmitting-receiving testing circuit (1), transmission, the receiving terminal of this cell transmitting-receiving testing circuit (1) link to each other with reception, a sendaisle of Board Under Test by high-speed interface respectively, it is characterized in that: also be provided with central processing system (2) and at least one repeat circuit (T0-Tn); Described central processing system (2) links to each other with cell transmitting-receiving testing circuit (1), and cell transmitting-receiving testing circuit (1) receives and is sent to Board Under Test through the initialized cell data of central processing system (2) and by high-speed interface; Repeat circuit (T0-Tn) also links to each other with high-speed interface with central processing system (2), and link to each other each repeat circuit (T0 or T1 or T2 with Board Under Test by high-speed interface ... or Tn) cell Transmitting and Receiving End is corresponding with a transmission, the receive path of Board Under Test separately.
2, switch network card tester as claimed in claim 1 is characterized in that: described repeat circuit (T0-Tn) comprises the receive logic circuit, sends logical circuit and channel number flag register, and the three all links to each other with central processing system (2); The receive logic circuit is corresponding with a sendaisle of Board Under Test, and it is corresponding with a receive path of Board Under Test to send logical circuit, and the output of channel number flag register links to each other with the transmission logical circuit.
3, switch network card tester as claimed in claim 2 is characterized in that: described repeat circuit (T0-Tn) also comprises asynchronous first-in first-out register (FIFO), checking circuit and count pick up device and transmitting counter; The count pick up device links to each other with the receive logic circuit, transmitting counter links to each other with the transmission logical circuit, asynchronous first-in first-out register (FIFO) links to each other with the input that sends logical circuit with the output of receive logic circuit respectively, as the buffer storage between the two; The input of checking circuit links to each other with asynchronous first-in first-out register (FIFO), and output links to each other with the transmission logical circuit.
4, as claim 1 or 2 or 3 described switch network card testers, it is characterized in that: described cell transmitting-receiving testing circuit (1) comprises that cell sends buffer memory, transmission logical circuit, cell reception buffer memory, receive logic circuit and detection module; Send logic and link to each other with high-speed interface with receive logic, correspond respectively to a receive path and a sendaisle on the Board Under Test, the two sends buffer memory by cell respectively again and links to each other with central processing system (2) with cell reception buffer memory; Detection module then receives buffer memory with cell transmission buffer memory, transmission logical circuit, cell respectively, the receive logic circuit is connected.
5, switch network card tester as claimed in claim 4, it is characterized in that: the detection module in the described cell transmitting-receiving testing circuit (1) comprise relatively patrol add, cell transmitting counter, cell count pick up device, wrong cell counter and cyclic redundancy check (CRC) counter, their in parallel or series connection.
6, a kind of network board method of testing based on the described device of claim 1 is characterized in that may further comprise the steps:
1) central processing system (2) initialization cell data wherein includes the channel number sign, is used to indicate Board Under Test to exchange;
2) cell transmitting-receiving testing circuit (1) receives initialized data, and sends to a receive path of Board Under Test;
3) repeat circuit (T0 or T1 or a T2 ... or Tn) receives from Board Under Test and the cell data that exchanged through Board Under Test, and after adding new channel number sign on this cell data, resend Board Under Test;
4) another repeat circuit (T0 or T1 or T2 ... or Tn) receives from Board Under Test and the cell data that exchanged through Board Under Test once more, and after adding new channel number sign on this cell data, resend Board Under Test once more;
5) repeat above-mentioned steps 4), up to the interchange channel that cell has been tested through all desires of Board Under Test;
6) when the sendaisle of the cell interchange channel that last desire is surveyed from Board Under Test was got back to test board, cell transmitting-receiving testing circuit (1) received this cell data, and compares detection.
7, network board method of testing as claimed in claim 6 is characterized in that: utilize repeat circuit (T0 or T1 or T2 ... or Tn) adds different channel number signs when transmitting at every turn, make test information cells can travel through all passages, once finish test.
8, as claim 6 or 7 described network board method of testings, it is characterized in that: cell transmitting-receiving testing circuit (1) comprises the content that the cell through exchange compares detection: send cell at first and the comparison of the cell that finally receives, the cell transmission counts and the comparison of cell count pick up, the counting and the cyclic redundancy check (CRC) of wrong cell.
9, as claim 6 or 7 described network board method of testings, it is characterized in that: at repeat circuit (T0 or T1 or T2 ... or Tn) adds on the test information cells data that new channel number sign is laid equal stress on and newly send in the process of Board Under Test, also carry out verification, send counting and count pick up.
10, network board method of testing as claimed in claim 8, it is characterized in that: at repeat circuit (T0 or T1 or T2 ... or Tn) adds on the test information cells data that new channel number sign is laid equal stress on and newly send in the process of Board Under Test, also carry out verification, send counting and count pick up.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 00132884 CN1129270C (en) | 2000-11-07 | 2000-11-07 | Switch network card tester and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 00132884 CN1129270C (en) | 2000-11-07 | 2000-11-07 | Switch network card tester and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1353523A true CN1353523A (en) | 2002-06-12 |
| CN1129270C CN1129270C (en) | 2003-11-26 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 00132884 Expired - Fee Related CN1129270C (en) | 2000-11-07 | 2000-11-07 | Switch network card tester and method |
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| CN (1) | CN1129270C (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1330135C (en) * | 2004-07-01 | 2007-08-01 | 华为技术有限公司 | Detector |
| CN100338913C (en) * | 2002-11-18 | 2007-09-19 | 鸿富锦精密工业（深圳）有限公司 | Switch with traffic generation function |
| CN100380869C (en) * | 2004-08-26 | 2008-04-09 | 杭州华三通信技术有限公司 | Method for detecting exchanger single-port unretransmitting problem utilizing mode of deleting single-transmitting MAC address |
| CN100396024C (en) * | 2005-11-03 | 2008-06-18 | 华为技术有限公司 | Testing device and testing method for exchanging network board |
| CN100413276C (en) * | 2002-12-09 | 2008-08-20 | 华为技术有限公司 | High-speed cell flow receiving and transmitting test device and method |
| CN101320067B (en) * | 2008-07-18 | 2012-05-16 | 福建先创电子有限公司 | Automatic testing equipment and method of multi-channel selector |
| CN104714832A (en) * | 2013-12-14 | 2015-06-17 | 中国航空工业集团公司第六三一研究所 | Buffer management method used for airborne data network asynchronous data interaction area |
| CN113472600A (en) * | 2020-03-31 | 2021-10-01 | 烽火通信科技股份有限公司 | Multi-node server testing method and system |
-
2000
- 2000-11-07 CN CN 00132884 patent/CN1129270C/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100338913C (en) * | 2002-11-18 | 2007-09-19 | 鸿富锦精密工业（深圳）有限公司 | Switch with traffic generation function |
| CN100413276C (en) * | 2002-12-09 | 2008-08-20 | 华为技术有限公司 | High-speed cell flow receiving and transmitting test device and method |
| CN1330135C (en) * | 2004-07-01 | 2007-08-01 | 华为技术有限公司 | Detector |
| CN100380869C (en) * | 2004-08-26 | 2008-04-09 | 杭州华三通信技术有限公司 | Method for detecting exchanger single-port unretransmitting problem utilizing mode of deleting single-transmitting MAC address |
| CN100396024C (en) * | 2005-11-03 | 2008-06-18 | 华为技术有限公司 | Testing device and testing method for exchanging network board |
| CN101320067B (en) * | 2008-07-18 | 2012-05-16 | 福建先创电子有限公司 | Automatic testing equipment and method of multi-channel selector |
| CN104714832A (en) * | 2013-12-14 | 2015-06-17 | 中国航空工业集团公司第六三一研究所 | Buffer management method used for airborne data network asynchronous data interaction area |
| CN113472600A (en) * | 2020-03-31 | 2021-10-01 | 烽火通信科技股份有限公司 | Multi-node server testing method and system |
| CN113472600B (en) * | 2020-03-31 | 2022-09-02 | 烽火通信科技股份有限公司 | Multi-node server testing method and system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1129270C (en) | 2003-11-26 |
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