CN1344073A

CN1344073A - Clock signal regenerating and receiving device and clock signal regenerating and receiving method

Info

Publication number: CN1344073A
Application number: CN01133098A
Authority: CN
Inventors: 前野晶子; 藤原卓; 井户纯
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 2000-09-13
Filing date: 2001-09-13
Publication date: 2002-04-10
Also published as: JP4003386B2; GB2370733B; CN101729487B; CN101729487A; GB2370733A; JP2002094480A; GB0122038D0

Abstract

PROBLEM TO BE SOLVED: To provide a clock signal regeneration circuit of an OFDM receiving device for accurately generating a clock signal, having no frequency and phase errors. SOLUTION: The frequency component data of sub carriers, where an OFDM signal is subjected to discrete Fourier transformation are selected by selectors 30 and 40 and are stored in RAMs 6 and 7. The frequency component of the sub carrier signal at least one sub carrier before in the same symbol that is stored by the RAMs 6 and 7, and the frequency component of the newly obtained sub-carrier signal are subjected to complex multiplication by a complex multiplication circuit 11, before being supplied to a ROM 12. The ROM 12 reads the amount of variation between sub carriers, corresponding to the complex multiplication result, and supplies it to an accumulation addition circuit 15. The accumulation addition circuit 15 performs the accumulation addition of the amount of phase extending over one symbol time and supplies the result to an offset addition circuit 16. The offset addition circuit 16 adds a fixed offset value to the accumulation addition result before outputting. The oscillation frequency of a clock signal is controlled by a clock oscillation control circuit 60, according to the output of offset addition.

Description

Clock regenerating signal and receiving system, clock regenerating signal and method of reseptance

Technical field

The present invention relates to be used to receive clock regenerating signal device and clock signal regeneration method, receiving system and the receiving method of the modulation signal receiving system of modulating based on the OFDM mode.

Prior art

The modulator approach of a kind of so-called OFDM mode as digital signal transmission method (OFDM:Orthogonal Frequency Division Multiplexing is to call the OFDM mode in the following text) has been proposed in recent years.

This OFDM mode, it is a kind of subcarrier that a plurality of quadratures are set in transmission band, with amplitude and the phase place that data allocations is given each subcarrier, adopt the Ditital modulation method of phase shift keying (PSK:PhaseShift Keying) or quadrature amplitude modulation technology such as (QAM:Quadrature AmplitudeModulation).

This OFDM mode is owing to by a plurality of subcarrier countdowns, carry out the transmission arranged side by side of a plurality of subcarriers, thereby the transmission band that each subcarrier is assigned to is very narrow.

Though explain in words defeated speed and unhappy with regard to a subcarrier, because many its total speed of carrier number are followed several indifferences of modulation system (as modulation systems such as QPSK:Quadrature Phase Shift Keying (Quadrature Phase Shift Keying), QAM) in the past.

In addition, this OFDM mode owing to be that a plurality of subcarriers transmit side by side, has reduced the semaphore of a symbol (an OFDM symbol) that comprises in arbitrary unit interval, and the result causes the decline of symbol transmission speed.

But, on the transmission path that exists so-called multipath to disturb,, be hopeful to realize suppressing the modulation system that multipath disturbs owing to can shorten the time span of disturbing with the corresponding multipath of symbol time length.

Bigger ground wave digital signal transmission is favourable because above-mentioned feature, OFDM mode are for the multipath interference effect that caused by landform or building etc., and the surface wave Digital Transmission of Japan is also adopting this mode.

But, for correct demodulating ofdm modulation signal in the receiver of OFDM mode, must in demodulator circuit, realize various synchronously, and also must be synchronous with the clock signal realization of transmitter side as the clock signal of the benchmark of all processing in the demodulation process.

Here, do an explanation with regard to the renovation process of previously presented clock signal, this method is used so that the clock signal that receiver side takes place is synchronous with the clock signal of transmitter side.

Shown in Figure 9 is the block diagram of the time signal reproducing circuit of disclosed OFDM receiver in the Japan Patent " spy opens flat 10-308715 communique ".

Illustrated time signal reproducing circuit 115, by constituting with the lower part: implement differential ference spiral (between the carrier wave of present reception and the carrier wave that receives previously phase difference carry out demodulation) differential ference spiral loop 3, ROM (read-only memory) 12, gate circuit 14, accumulating operating circuit 15 (accumulation calculating circuit), averaging circuit 23, comparison circuit 18, control circuit 20, sign circuit for reversing 21, selector 22 and clock signal oscillation control circuit 60 (control circuit).

Differential ference spiral loop 3 comprises RAM (random access memory) 6,7 (memory circuit), sign circuit for reversing 10 and complex multiplication circuit 11.

The following describes the action of circuit.

With the subcarrier frequency signals (intermediate frequency (IF) signal) of the analog signal of a demodulation of main carrier frequency signal, in the OFDM receiver of band analog/digital (A/D) change-over circuit, be digitized processing.

The I channel data IR (hereinafter claiming IR) and the Q channel data QR (hereinafter claiming QR) of each symbol that is generated on the demodulator circuit of subcarrier frequency signals (baseband signal) by this digitized IF signal are imported into differential ference spiral circuit 3.

Differential ference spiral circuit 3 is according to IR and QR calculating real number compositional data RN and the imaginary number compositional data JN and the output of input.

And IR and QR are by the fast Fourier transform (FFT) circuit output of the enforcement discrete Fourier transform (DFT) that comprises the baseband signal demodulator circuit.

RAM6 in the differential ference

spiral circuit

3,7, the control signal c that exports according to control circuit 20 described later stores IR or QR with symbolic unit, and the data of each stored symbol (IR or QR) are only postponed a symbol time output.Sign circuit for reversing 10 is with the sign counter-rotating back output of the data of RAM7 output.

Complex multiplication circuit 11 in the differential ference spiral circuit 3 carries out following complex operation based on the dIR, the dQR that postpone because of RAM6 and RAM7 respectively to IR and the QR that is not delayed.

Operation result is still exported respectively with real number compositional data RN and imaginary number compositional data JN.In the following description, j represents imaginary number.

(IR+jQR)(dIR-jdQR)…(1)

This (1) formula is launched, can be got: real number compositional data RN=IRdIR+QRdQR, imaginary number compositional data JN=dIRQR-IRdQR.

ROM (Read Only Memory) 12 has the arctan function data, and output is with the real number compositional data RN of input and the phase place variation data PS (the phase place variation PS that obtains here is the phase place variation between IR, QR and dIR, the dQR) of imaginary number compositional data JN correspondence.

In addition, constitute computing circuit 13 by above-mentioned complex multiplication circuit 11 and ROM12 herein.

A symbol in the OFDM mode is made of a large amount of (hundreds of to thousands of) subcarrier frequency signals, in the subcarrier frequency signals of this symbol, many pilot signals of having distributed to is arranged.

So, gate circuit 14, control signal according to control circuit 20, from the phase place variation data PS of ROM12 output, only the one-tenth corresponding with the pilot signal that transmitter side inserts is sub-elected, supply with sign circuit for reversing 21 and selector 22 (below, will be called phase place variation data PPS) with the phase place variation data PS of the frequency correspondence of pilot signal.

Sign circuit for reversing 21 is supplied with selector 22 with the sign counter-rotating of the phase place variation data PPS of input.

Selector 22, by control signal control from control circuit 20, as the phase place variation data PPS that directly imported by gate circuit 14 is on the occasion of (positive frequency), then select these phase place variation data PPS, perhaps, PPS is negative value (a negative frequency) as these phase place variation data, then selects to supply with accumulating operating circuit 15 from the phase place variation data of sign circuit for reversing input.

Accumulating operating circuit 15 is before the phase place variation data PS of each symbol of input, by the control signal b initialization from control circuit 20.

Thereafter, the phase place variation data PPS that accumulation calculating is exported by selector 22, and the accumulation calculating value (amount of phase error) of this accumulation calculating gained is pressed each symbol export.

Averaging circuit 23, accumulating operating circuit 15 is exported by each symbol by the amount of phase error average back in a plurality of symbolic ranges through accumulation calculating of each symbol output, in this way, the amount of phase error PSO of the Gaussian noise in the amount of phase error (white noise) has been removed in output.

In this case, because gaussian noise takes place at random, its time mean value is zero (this occasion adopts addition on average to get final product).Therefore, if the amount of phase error of each symbol of containing gaussian noise is averaged, the contained gaussian noise of amount of phase error is vanishing, the mean value of the signal beyond the only remaining gaussian noise.

After comparison circuit 18 detects and is determined (locking (lock in)) from the clock signal frequency of the clock signal oscillation circuit of OFDM receiver output, notice control circuit 20.

So-called locking refers to here because each intersymbol differential ference spiral data is zero, and averaging circuit 23 is by the output of each symbol also situation of indifference (detecting this state).

Comparison circuit 18, the output valve amount of phase error PSO of the fiducial value SV of the output equivalence of the averaging circuit 23 when being zero with intersymbol differential ference spiral data and current averaging circuit 23 compares, and comparative result is exported to control circuit 20 by each symbol.

Control circuit 20 receives the comparative result of the comparison circuit 18 of each symbol, and gate circuit 14 and selector 22 are controlled, and makes them follow the timing of phase place variation data PS of each pilot signal corresponding.

Simultaneously, control circuit 20 is by carrying out control to accumulating operating circuit 15 output control signal b and to RAM6 and RAM7 output control signal c, divides into groups during making the input, output signal of above-mentioned accumulating operating circuit 15, RAM6 and RAM7 by each symbol.

Clock signal oscillation control circuit 60, according to the dateout PSO of averaging circuit 23, output is in order to the control signal CS of the clock-signal generator frequency of oscillation of control OFDM receiver.

In " spy opens flat 10-308715 communique " disclosed OFDM receiver, utilize above-mentioned time signal reproducing circuit, the clock signal that the clock signal oscillation circuit of OFDM receiver is produced is synchronous with the clock signal of transmitter side.

Summary of the invention [problem that invention will solve]

Carrying out demodulation as for the subcarrier signal to the OFDM receiver, is exactly to implement discrete Fourier transform (DFT) at fast Fourier transform circuit, and time-domain signal is transformed to frequency-region signal.

The zone of the spatial transform scope when regulation is carried out this conversion is called time window.When having frequency error, phase error in clock signal, this time window can be offset.

For example, only having phase error and do not have the occasion of frequency error in clock signal, because time window only is the regular hour skew for full symbol, then be that certain phase place is rotated for the subcarrier frequency composition of full symbol.

Here, as above-mentioned " spy opens flat 10-308715 communique " disclosed OFDM receiver, adopt the detected structure of phase place variation PPS of frequency content (being the subcarrier frequency signals on the frequency space after the FFT conversion) of pilot signal series of the subcarrier of the subcarrier at first correspondence is laid respectively at last symbol and current sign.

Here, the amount of phase error of so-called accompanying clock signal frequency error is meant when producing error on clock signal frequency the amount of phase error that shows on the subcarrier frequency signals phase place.At this moment, implement control with the result of calculation of this amount of phase error to clock signal frequency.

According to the phase place variation PPS that measures (between distinct symbols, phase difference between the subcarrier frequency signals on the same frequency) during regenerated clock signal, in the amount of phase error of measuring (the accumulation calculating value of phase place variation PPS during a symbol of the frequency content of corresponding a plurality of pilot signal series), the amount of phase error that comprises accompanying clock signal frequency error, but do not comprise the amount of phase error of accompanying clock signal phase error.

This be because, when comprising frequency error in the clock signal of regeneration in the above described manner, because the phase place rotation of change in time takes place in the subcarrier, thereby cause the subcarrier phase change between each symbol, but when having phase error in the clock signal, the phase place of subcarrier does not change between symbol, and also the phase place variation that just can not be used as between the symbol detects.

As a result, the problem of existence is that by the time signal reproducing circuit of putting down in writing in the above-mentioned communique, the impossible execution about the clock signal phase error Control also just can not be improved the performance that clock signal is introduced.

In the OFDM receiver, as long as there is frequency error in the clock signal, the orthogonality between each subcarrier has been destroyed, and will occur between the subcarrier interfering.Introduce performance owing to can not improve clock signal, in clock signal, leave frequency error, thereby make the bit error rate characteristic variation of regenerated signal.

In addition, can not detect the phase error of clock signal with disclosed clock regenerating signal technology in the above-mentioned communique.Therefore, only under the fully synchronous condition of clock signal frequency, when time window and significant character position are in full accord and, for example, when only with the signal of front skew being arranged in time, detect to export and difference just do not occur.

But, when time window is inconsistent with the significant character position, because actual effectively protection gap length shortens, will variation to the multipath of transmission path (or the multipath noise that causes of multipath) thus or the tolerance of frequency selective fading.For this reason, also require high-precision control is implemented in the position of time window.

With regard to the control of time window, have and a kind ofly extrapolate the method for significant character position at interval and with the correlation of the back-page data of its corresponding symbol from protection.But also there is such problem in this method, when transmission path postpones owing to reasons such as multipath form, because of the low accuracy of detection variation that causes phase error of correlation.

Therefore, people wish to realize to detect accurately always, the error of control time window and clock frequency, phase place.

The present invention is intended to solve above-mentioned problem, and providing not to have correct time signal reproducing circuit and the clock signal regeneration method that generates the OFDM receiving system of clock signal of frequency error and phase error ground.

[the solution circuit of problem]

The clock regenerating signal device relevant with the present invention is characterized in that adopting following various circuit: the demodulator circuit of the restituted signal of output after with the clock signal digitized processing of the signal defined frequency of the subcarrier band that obtains with main carrier frequency demodulating ofdm modulation signal; Make according to the above-mentioned restituted signal delay of this demodulator circuit output and the delay circuit that the restituted signal that postpones is exported; The phase place variation output circuit of the phase place variation output between the pilot signal that mark space phase of above-mentioned ofdm modulation signal is comprised based on above-mentioned restituted signal and these two kinds of signals of above-mentioned delay restituted signal; The control circuit of the frequency of above-mentioned clock signal being controlled based on the output that obtains with this phase place variation output circuit.

Its feature also is, comprises the accumulation calculating circuit that the output of phase place variation output circuit is carried out accumulation calculating.

Its feature also is, comprises the biasing adder operation circuit that the output of accumulation calculating circuit is setovered.

Its feature also is to have the significant character length of restituted signal and the symbol lengths decision circuit of protecting gap length to make a determination, and the structure that changes the amount of bias size according to the output of this symbol lengths decision circuit.

Its feature also is to have the structure that equalization is handled is made in the output of biasing counting circuit in a plurality of symbols of ofdm signal.

Its feature also is, comprises filter circuit for filtering is carried out in the output of biasing adder operation circuit.

Its feature also is to have the symbol lengths decision circuit that the significant character length and the protection gap length of restituted signal are decision making, and the structure that changes filter gain size according to the output of this symbol lengths decision circuit.

The receiving system relevant with the present invention possesses various circuit as described below: the clock signal of the signal defined frequency of the subcarrier band that obtains with main carrier frequency demodulating ofdm modulation signal is made a demodulator circuit of digitized processing; Based on the secondary demodulation circuit of the output that obtains with this demodulator circuit with the restituted signal output of each passage; The phase-correcting circuit of the phase compensation correction of the restituted signal that will produce with this secondary demodulation circuit; The output of this phase-correcting circuit is postponed and with the delay circuit of the restituted signal output that postpones; The phase place variation output circuit of the phase place variation output between the pilot signal that comprises during the symbol of restituted signal based on above-mentioned restituted signal and delay with above-mentioned ofdm modulation signal; The control circuit of above-mentioned clock signal frequency being controlled based on the output of this phase place variation output circuit.

Its feature also is, comprises the biasing adder operation circuit that the output of accumulating operating circuit is setovered.

Its feature also is to have the symbol lengths decision circuit that the significant character length and the protection gap length of restituted signal are decision making, and the structure that changes the amount of bias size according to the output of this symbol lengths decision circuit.

Its feature also is, has in a plurality of symbolic ranges of ofdm signal the structure to averaging of the output processing of biasing adder operation circuit.

Its feature also is to have the significant character length of restituted signal and the symbol lengths decision circuit of protecting gap length to make a determination, and the structure that changes filter gain size according to the output of this symbol lengths decision circuit.

The clock signal regeneration method relevant with the present invention is characterized in that comprising various steps as described below: the clock signal of exporting the signal defined frequency of the subcarrier band that obtains with main carrier frequency demodulating ofdm modulation signal is carried out the demodulation step of the restituted signal of digitized processing; Make the above-mentioned restituted signal that draws according to this demodulation step postpone and obtain to postpone the delay step of restituted signal; The phase place variation output step of the phase place variation output between the pilot signal that comprises during the symbol of restituted signal based on above-mentioned restituted signal and delay with above-mentioned ofdm modulation signal; The controlled step of the frequency of above-mentioned clock signal being controlled based on the output that obtains with this phase place variation output step.

The method of reseptance relevant with the present invention possesses various steps as described below: the clock signal of the signal defined frequency of the subcarrier band that obtains with main carrier frequency demodulating ofdm modulation signal is made a demodulation step of digitized processing; Based on the secondary demodulation step of the output that obtains with this demodulation step with the restituted signal output of each passage; The phase compensation correction step that the restituted signal that produces with this secondary demodulation step is carried out the phase compensation correction; The output that obtains with this phase compensation correction step is postponed and with the delay step of the restituted signal output that postpones; The phase place variation output step of the phase place variation output between the pilot signal that comprises during the symbol of restituted signal based on above-mentioned restituted signal and delay with above-mentioned ofdm modulation signal; The controlled step of the frequency of above-mentioned clock signal being controlled based on the output that obtains with this phase place variation output step.

[embodiment]

Embodiment 1 (OFDM receiver)

Fig. 1 is the block diagram of OFDM receiver of the employing time signal reproducing circuit (clock regenerating signal device) of the embodiment of the invention 1.

As shown in Figure 1, OFDM receiver 150 is made of following each several part: reception antenna 101, multiplying operational circuit 102, the main carrier oscillating circuit 103 in order to channel selection, band pass filter (BPF) 104, analog/digital (A/D) translation circuit 105, in order to subcarrier frequency signals demodulator circuit 120, clock signal oscillator 116 and the time signal reproducing circuit 130 of the subcarrier frequency signals of demodulating ofdm.

And clock signal oscillator 116 is included in its work in receiver in order to the device of regenerative modulator modulation with clock signal, as VCXO (voltage controlled crystal oscillator) etc.At this moment, the phase information of subcarrier frequency signals is used to try to achieve the phase place variation in the prosign.

And, this clock signal oscillator 116 by time signal reproducing circuit 130 output control signal control.

In addition, subcarrier frequency signals demodulator circuit 120 (its exercises are hereinafter described) is made of following each several part: multiplexer 106, digital control oscillating circuit 110, adder operation circuit 111, fast Fourier transform circuit (FFT) 112, correlation computing circuit 113 and carrier frequency error computing circuit 114.

Reception antenna 101 is in order to accept the radio signal (ofdm modulation signal) of OFDM modulation.The predetermined main carrier frequency signal of 102 pairs of main carrier oscillating circuits of multiplying operational circuit, 103 outputs and the radio signal of reception are done multiplying.

Band pass filter (BPF) 104 is selected intermediate frequency (IF) signal (demodulation a: demodulation step) that forms from the subcarrier band of multiplying operational circuit 102 output generations.A/D translation circuit 105 is done digitlization signal transformation with the IF analog signal that BPF104 selects.

In other words, in a demodulation, ofdm signal is carried out digitlization (action of carrying out so far is a demodulator circuit) with preset clock signal.

Multiplexer 106 will be through the IF data outputs (exporting the demodulating data of each passage) of digitized IF Signal Separation IF data that are the I passage and Q passage.Low pass filter (LPF) 107 is with unwanted radio-frequency component (for example signal of adjacency channel or the noise etc.) filtering that comprises in the I passage IF data.The unwanted radio-frequency component filtering that LPF 108 is contained with Q passage IF data.

Multiplying operational circuit 109 is done multiplying with the I passage IF data and the Q passage IF data of input with the subcarrier frequency signals of controlling through digital control oscillating circuit 110 and provide, and generates I passage demodulating data and Q passage demodulating data when getting rid of frequency error.

High speed Fourier transform circuit (FFT) 112 will be transformed to frequency content from the I passage demodulating data and the Q passage demodulating data as time signal of complex operation circuit 109 inputs, thus I passage demodulating data IR and the Q passage demodulating data QR after the generation enforcement discrete Fourier transform (DFT).

113 inputs of correlation computing circuit are as the I passage demodulating data and the Q passage demodulating data of time signal; protection interval when adopting according to described input data former state with demodulating data protection interval when the significant character phase postpones only, the correlation between the signal that calculating only is separated from each other in the significant character phase and with its output.

Carrier frequency error computing circuit 114 detects the biasing of each frequency output from the output of FFT 112, detects demodulating data IR after the discrete Fourier transform (DFT) and the frequency error between the QR, exports to adder operation circuit 111.

Adder operation circuit 111 is given digital control oscillating circuit 110 after the frequency error output addition with the output of the correlation of correlation computing circuit 113 and carrier frequency error computing circuit 114.

Protection interval on the ofdm signal, the additional signal that has with the significant character terminal point same content of a part nearby, the cycle during this protects interval with symbol occurs.

Because the signal of this protection interval has added the signal with the significant character terminal point same content of a part nearby, thereby makes this significant character and the correlation between signals of protecting interval become maximum.

Therefore,, just might determine the protection interval on this significant character, also just might determine the significant character phase simultaneously by finding significant character and the position of the correlation between signals of protecting interval for maximum.

In other words, by to the determining of significant character phase, just might be based on the length enforcement FFT conversion of this significant character phase.

In subcarrier frequency signals demodulator circuit 120, begin the FFT112 conversion of back segment as mentioned above at the time point of correlation maximum by complex multiplication operation circuit 109, therefore, can make the frequency error of the transform data IR of FFT112 output and QR become minimum (be secondary demodulation (secondary demodulation step) from what the A/D conversion was so far carried out, once be referred to as demodulator circuit) with the secondary demodulation circuit.

Time signal reproducing circuit 130 according to I passage demodulating data IR and Q passage demodulating data QR, generates the control signal CS in order to the frequency of oscillation of control clock signal oscillator 116.And control signal CS herein includes the information of the control signal that relates in the technology different from the past.

Clock signal oscillator 116, according to the control signal CS of clock signal oscillation circuit 130 output to A/D change-over circuit 105 and other circuit clock signals.

A/D change-over circuit 105 shown in Figure 1, subcarrier frequency signals demodulator circuit 120, time signal reproducing circuit 130 and clock signal oscillator 116 constitute the PLL circuit in order to the control clock signal frequency.(time signal reproducing circuit)

Fig. 2 is the block diagram of the time signal reproducing circuit 130 of the embodiment of the invention 1.

In addition, time signal reproducing circuit 130 shown in Figure 2 has added identical symbol in the part identical with 115 actions of time signal reproducing circuit in the past shown in Figure 9, and explanation is omitted.

In the selector 30, comprise the switch 31 of only from I passage demodulating data IR, choosing data (being called PIR) and the phase value (pilot signal of from the data of selecting through switch 31, transmitter side being stipulated on the ofdm signal corresponding to pilot signal, because known phase value that should regulation, so can judge to the degrees of offset of the phase place of receiver side regeneration) phase-correcting circuit 32 (this action step is called the phasing step) removed.

Similarly, in the selector 40, comprise the switch 41 of only from Q passage demodulating data QR, choosing data (being called PQR) and the phase-correcting circuit of from the data of selecting through switch 41, the phase value of transmitter side regulation being removed 42 corresponding to pilot signal.

What is called refers to corresponding to the phase value of the pilot signal of transmitter side regulation, for example, and the phase value of Japanese digital terrestrial broadcasting prescribed by standard.

According to Japanese digital terrestrial broadcasting standard, the amplitude of the subcarrier of corresponding pilot signal and phase place are provided with in accordance with regulations at transmitter side in advance, and make this setting also become Given information (phase information in the transmitter side regulation is called known phase) at receiver side.

Specifically for example, being defined as 0 or during π in the phase place of transmitter side pilot signal, will be that O or π prenotice away (time point of notice is stipulated in advance) in standard corresponding to the phase place of the subcarrier of the pilot signal that receives then for receiver side.

When the known phase of the subcarrier of corresponding this pilot signal was π, phase-correcting

circuit

32,42 was π (subtraction this moment) output according to the phasing of pilot signal just.

In the differential ference spiral circuit 3 of present embodiment, be implemented the data of the interior corresponding adjacent pilot frequencies signal of just prosign of differential ference spiral.In addition, the I passage demodulating data IR of RAM6,7 storage phase-correcting

circuits

32 and 42 outputs and Q passage demodulating data QR (effect of phase-correcting

circuit

32,42 is that the restituted signal phase place is implemented to proofread and correct).

At this moment, (data of corresponding pilot signal are called demodulating data PIR among the I passage demodulating data IR only to store the data of corresponding pilot signal among I passage demodulating data IR and the Q passage demodulating data QR, the data of the corresponding pilot signal of Q passage demodulating data QR are called demodulating data PQR), and will be by the delay demodulating data dIR and the dQR output (the delay demodulating data of the I passage demodulating data IR of corresponding pilot signal is called and postpones demodulating data PdIR, and the delay demodulating data of the Q passage demodulating data QR of corresponding pilot signal is called and postpones demodulating data PdQR) of the time delay of the origination interval of a suitable pilot signal.

In other words, RAM6,7 has played delay circuit, also is called the delay restituted signal through delay demodulating data PdIR, the PdQR of RAM6,7 outputs.

Sign circuit for reversing 10 is exported after the delay demodulating data dQR reindexing with RAM7 output, and only with the delay demodulating data PdQR output of corresponding pilot signal.

In a symbol (phase) of ofdm signal, comprise hundreds of to thousands of subcarrier frequency signals, comprising many pilot signals.The time that the interval is suitable with the origination interval of above-mentioned pilot signal, mean the time of being separated by between certain pilot signal and the adjacent pilot frequencies signal.

Complex multiplication operation circuit 11 follows delay demodulating data PdIR and PdQR through RAM6 and 7 pilot signals that postpone to do plural multiplying to the demodulating data PIR of not delayed pilot signal and PQR.

The complex multiplication operation result of complex multiplication operation circuit 11 is that the imaginary number composition PJN of the real number composition PRN of pilot signal and pilot signal is separated and exports.

ROM12 reads the real number compositional data PRN of the pilot signal of correspondence input and the data of imaginary number compositional data PJN, as the phase place variation data PS output of pilot signal from the arctan function data of storage.

Accumulating operating circuit 15 (accumulating operating circuit) is made accumulation calculating to the phase place variation data PS from the pilot signal of ROM12 output during a symbol.And biasing adder operation circuit 16 (biasing adder operation circuit) adds bias on the accumulation calculating data of the phase place variation data PS of the pilot signal of accumulating operating circuit 15 output.

Loop filter 50 (filter circuit) is with the noise filtering (filtering) among the phase place variation data PS2 of the pilot signal of biasing adder operation circuit output.

Clock oscillation control circuit 60 (control circuit), according to the data of loop filter 50 output (the phase place variation data PS2 after on the cumulative data PS1 of the phase place variation data PS of pilot signal, adding upper offset), export control signal CS in order to the frequency of oscillation of control clock signal oscillator 116.

Fig. 3 (a) and (b) are in order to explanation, when having frequency error in the clock signal that generates in the clock oscillator 116 of Fig. 1, the phase error that on the frequency content of the I passage demodulating data IR of the clock signal generating circuit 130 of input Fig. 2 and Q passage demodulating data QR, occurs.

The frequency content phase error of the frequency content of Fig. 3 (a) expression I passage demodulating data IR and Q passage demodulating data QR, Fig. 3 (b) expression pilot signal among I passage demodulating data IR and the Q passage demodulating data QR when there is frequency error in the clock signal.

In Fig. 3 (a), SPO is the pilot signal of low-limit frequency in the symbol, and SP1 and SP2 catch up with and state pilot signal SPO in prosign, but are the pilot signal of upper frequency, and SP3 then is the pilot signal of highest frequency in the above-mentioned pilot signal SPO prosign.

Among Fig. 3 (b), 91 is the phase theta of the pilot signal SPO of low-limit frequency ₀Phase theta with pilot signal SP1 ₁Between phase place variation (θ ₁-θ ₀).

92 is the phase theta of pilot signal SP1 ₁Phase theta with pilot signal SP2 ₂Between phase place variation (θ ₂-θ ₁), 93 is the phase theta of pilot signal SP2 ₂Phase theta with pilot signal SP3 ₃Between phase place variation (θ ₃-θ ₂).

In addition, 94 the phase place variation ∑ (θ that add up for the phase place variation 91 to 93 between the adjacent pilot frequencies signal in the prosign _f-θ _F-1).

The phase place that adds up variation 94, consistent with minimum pilot signal SPO in the prosign to the phase place variation of the highest pilot signal SR3.

Therefore, phase place variation 94, in prosign, the phase place variation of each frequency content of adjacent pilot frequencies signal is carried out the occasion of accumulation calculating during a symbol, equal the phase place variation between the low-limit frequency pilot signal and highest frequency pilot signal in the prosign.

Fig. 5 is the action flow chart of present embodiment 1.

The FFT112 of subcarrier frequency signals demodulator circuit 120 exports among the I passage demodulating data IR and Q passage demodulating data QR of (through demodulation step output), selects and export the number of sub certificate (step S1) of the pilot signal of stipulating corresponding to transmitter side by

selector

30 and 40.

The demodulating data PIR of the pilot signal of

selector

30 and 40 outputs sends RAM6 and RAM7 to.At this moment, the I passage demodulating data PIR of RAM6 storage pilot signal, the Q passage demodulating data PQR of RAM7 storage pilot signal.

Then, RAM6 and RAM7 send to I passage demodulating data PIR and the Q passage demodulating data PQR that the above-mentioned data that deposit in remain to corresponding next pilot signal always.

In other words, RAM6 and RAM7 only postpone to be equivalent to interlude in each pilot signal origination interval with I passage demodulating data PIR and the Q passage demodulating data PQR that deposits in, then as I passage demodulating data PdIR and Q passage demodulating data PdQR output (step S2: postpone step).

Simultaneously, the delay demodulating data PdQR of RAM7 output exports after sign circuit for reversing 10 conversion signs.

The demodulating data PIR of pilot signal, demodulating data PQR, the delay demodulating data PdQR that postpones demodulating data PdIR and reverse through sign are sent to complex operation circuit 11 and carry out complex operation.

In the operation result of complex multiplication operation circuit 11 (multiplication result), real number compositional data RN and imaginary number compositional data JN are by 11 outputs (step S3) of complex multiplication operation circuit.

ROM12 reads corresponding to the real number compositional data RN of complex multiplication operation circuit 11 outputs and the arctan function data of imaginary number compositional data JN, based on above-mentioned readout the phase place variation PS between adjacent (adjacent with this pilot signal in a plurality of pilot signals that comprise) pilot signal is carried out computing in prosign, then output.

Accumulating operating circuit 15 in identical symbol (in the prosign), is made accumulating operation with each the phase place variation data PS between the adjacent pilot frequencies signal of ROM12 output during a symbol.After finishing the accumulating operation of a symbol share, accumulation result is output, the value of initialization accumulation calculating then (step S5: the accumulating operation step).

Whenever finish the calculation process of a symbol share, accumulating operating circuit 15 offers biasing adder operation circuit 16 with accumulation result output.Biasing adder operation circuit 16 adds bias on accumulation result, output offset add operation data PS2 (step S6: biasing add operation step).

Biasing add operation data PS2 is transmitted to loop filter 50, with unwanted noise filtering, and output phase variation data PS3 (step S7: filter step).

Clock oscillation control circuit 60, accumulation result-phase place variation data the PS3 of the phase place variation of each pilot signal in the as above detected prosign, detect the frequency error and the phase error of clock signal intrinsic among the phase place variation data PS3, then based on the frequency error and the phase error of this clock signal, output is in order to control signal CS (the step S8: controlled step) of 116 frequency of oscillation of control clock signal oscillator.

In the present embodiment, as mentioned above,, these data of preserving of the phase place variation between the adjacent pilot frequencies signal in the prosign have been obtained as parameter by selecting to implement complex multiplication operation after the pilot signal.

In other words, by present embodiment, can calculate the phase place variation of the subcarrier frequency composition of the pilot signal in the corresponding prosign shown in Fig. 3 (b).

Thus,, also can detect the frequency error and the phase error of clock signal, thereby improve the introducing performance of clock signal even when the subcarrier phase between each symbol does not change.

In addition, the pilot signal SPO of the low-limit frequency in the prosign for example is the occasion of+3 π to the phase place variation 94 that adds up of the pilot signal SP3 of highest frequency, and also can consider above-mentioned phase place variation 94 not to be made accumulation calculating and the mode once calculated.

But, can be+2 π by the maximum phase variation that computing circuit 13 is once calculated, when the phase place variation is+3 π,, specious+π can be counted as, and correct phase place variation can not be obtained if once calculate the phase place variation.

In addition, because the pilot signal in the general symbol has a plurality of, phase place variation 91 to 93 between the adjacent pilot frequencies signal all can not be for more than 2 π, and still, in fact the situation that+2 π above (for example reaching+3 π) appear in the phase place variation 94 in the prosign should take in.

In this occasion, when the frequency of sampled clock signal or phase place comprised error, the phase place change in the FFT output had just produced (still, the phase place variation in this moment symbol depends on the size of frequency or phase error).

Structure to this present embodiment, if the phase place variation between the adjacent pilot frequencies signal 91 to 93 respectively is below+2 π, even the pilot signal SPO of the low-limit frequency in the prosign total phase place variation of the highest pilot signal SP3 extremely is more than+2 π,, the phase place variation 91～93 between the adjacent pilot frequencies signal just can correctly calculate the phase place variation 94 in the prosign by being added up during a symbol.

And then, the low-limit frequency pilot signal SPO in the prosign to the detection range of the phase place variation 94 of highest frequency pilot signal SP3 can expand to+more than 2 π.(about the add operation of bias)

In addition, in the present embodiment, also can consider as adding bias on the above-mentioned phase place variation SP that accumulation calculating obtains in prosign.

Fig. 4 has represented the significant character signal on the ofdm signal, protection blank signal and in order to the relation between the time window three who makes discrete Fourier transform (DFT).

In the ofdm signal, the time shaft of transmitter side is provided with the protection blank signal.When being provided with, keep the frequency interval of subcarrier constant, and consider the time of delay of the delay ripple of setting, manage to make the length of symbol long as best one can then.

As shown in Figure 4, the protection blank signal is to be provided with like this on the ofdm signal, and the data at significant character signal rear portion on the time shaft are duplicated, and is added to the front of this significant character.

At receiver side; the data of ignoring the protection compartment of establishing because of the intersymbol interference that causes of delay waveguide of supposition; in order to carry out the time window of OFDM demodulation, the data of time window scope are implemented discrete Fourier transform (DFT) by fast Fourier transform circuit with remaining data setting.

When not having frequency error, phase error in the clock signal that generates on the clock signal oscillator 116 shown in Figure 1, the time window skew of fast fourier transform can not appear.But when causing in the clock signal frequency of occurrences sum of errors phase error because of the detection error of the phase place variation in the symbol etc., time window just can the time of origin skew.

Time window skew can have following 1. and 2. two kinds of situations.

1. forward direction skew as on time shaft, time window scope comprised protection at interval data and the data at significant character rear portion are eliminated (that segment data that exceeds the time window scope is also just for included during the time window).

In other words, if time window moves forward on time shaft, can comprise protection data at interval in the time window scope, and the data at significant character rear portion are eliminated.But because protection is exactly that the data that append to the significant character rear portion of significant character front are duplicated part at interval, the orthogonality between the subcarrier that is transformed can be guaranteed.

At this moment, generally the destruction that all can cause the orthogonality between the subcarrier is exactly that the data that append to the significant character rear portion of significant character front are duplicated part owing to protecting at interval still, and the orthogonality between the subcarrier that is transformed is guaranteed of equal valuely.

2. back to skew on time shaft as above-mentioned time window; in the time window scope; because of the data of significant character front portion are eliminated (that segment data that exceeds the time window scope is also just for included during the time window), and comprised the additional protection interval data that duplicates part that adjacent next significant character data are arranged.

At this moment, the data of adjacent-symbol have replaced original data, cause the intersymbol interference of the signal after the discrete Fourier transform (DFT), thereby bring considerable influence for the error rate of regenerated signal.

Therefore, even leave frequency error and phase error in the clock signal,, can adopt time window is departed from original position and the method for the biasing that moves forward in order to allow the unlikely skew backward of time window.

Owing to have the skew of window if having time of frequency error and phase error in the clock signal, for establishing biasing, certain bias to be arranged for well on phase place to regenerated clock signal to time window.Have, this bias can be selected the arbitrary value (just when) of adaptive system requirement again

In the present embodiment,, obtain control signal CS in order to the frequency of oscillation of control clock oscillator 116 according to the result who on the phase place variation of accumulation calculating, adds bias.Add certain phase bias can for thus the clock signal oscillator clock signal that 116 vibrations produce.

Its result, setting comprises the offset of certain biasing to time window, when having frequency error and phase error in clock signal, can prevent that time window from intersymbol interference taking place, and improves the error rate of regenerated signal when adjacent-symbol scope bias internal.

By the above embodiments, can detect the frequency error of clock signal and the phase place variation that phase error causes, thereby improve the introducing performance of clock signal.

And though be+2 π by the maximum of the phase place variation between the adjacent pilot frequencies signal that once calculates, by accumulation calculating, the detection range of phase place variation can obtain enlarging in the symbol.

And owing to comprise a plurality of pilot signals in the symbol, the phase place variation in the symbol can be calculated by high accuracy, thereby can improve the introducing speed and the performance of clock signal.

Embodiment 2

In the above embodiments 1, the method and apparatus that adds the fixed bias value in the symbol of accumulation calculating on the phase place variation has been described.

Among the embodiment 2; purchased in the receiving system of ofdm signal of length (significant character is long) at the significant character that the OFDM that can change Japanese digital terrestrial broadcasting standard code transmits and protection length (protection is long at interval) transmission at interval; long at interval according to significant character length, protection, change the biasing change circuit that should add bias in (exporting) symbol on the phase place variation via the accumulation calculating circuit that the phase place variation in the prosign is carried out accumulation calculating.

For example, during the OFDM of Japanese ground-wave digital broadcasting standard code transmitted, the quantity that can divide for three steps changed the subcarrier in the significant character transmitted, and also can branch multistep change protection length at interval transmit.

There is phase error in the clock signal, can causes skew in the time window of discrete Fourier transform (DFT), to occur.For different transmission significant character (significant character that has been transmitted) length and protection gap length, even there is the phase error of identical size in the clock signal, the side-play amount of the time window that it caused also has difference with the ratio between the significant character length.

As described in the embodiment 1 of front, only move forward the position of regulation from its original position by the time window of will be on the time shaft discrete Fourier Tranform, even when the clock signal has frequency error and phase error, also can make intersymbol interference be difficult to generation.

Explanation in present embodiment 2 increases when significant character and protection are at interval longer and the mode of dwindling more in short-term at interval in significant character and protection (set and adapt to significant character is long and protection is long at interval discrete Fourier transform (DFT) time window in the side-play amount on the time shaft) can obtain the time window (optimum position of time window on time shaft) of and protection at interval long speech the best long with regard to each significant character in the side-play amount on the time shaft (shift amount) by making above-mentioned discrete Fourier transform (DFT) time window.

Fig. 6 is the block diagram of the time signal reproducing circuit of the embodiment of the invention 2.

In the time signal reproducing circuit 131 shown in Fig. 6, adopt identical mark in its part identical with time signal reproducing circuit 130 actions of time signal reproducing circuit in the past 115 shown in Figure 9 and embodiment 1 shown in Figure 2, explanation is omitted.

In addition, use the structure of OFDM receiver of the time signal reproducing circuit 131 of the embodiment of the invention 2, the structure shown in Figure 1 with embodiment 1 is identical, and time signal reproducing circuit 131 is equivalent to time signal reproducing circuit 130 parts among the embodiment 1.

The time signal reproducing circuit 131 of present embodiment shown in Figure 6, with the time signal reproducing circuit of the embodiment 1 of Fig. 2 relatively, have following difference.

The structure of the time signal reproducing circuit 130 on the embodiment 1 is to add certain bias on the phase place variation after the accumulation calculating; And the structure of the time signal reproducing circuit 131 of present embodiment 2 is, has by significant character length and the protection long decision circuit 17 in interval (the long decision circuit of symbol) to judge, then the change circuit 18 that the bias that adds is changed according to result of determination.

Below, its action is described.

The long decision circuit 17 of symbol is judged that significant character length and the protection on the ofdm signal of importing is long at interval, and result of determination is exported.

Circuit 18 is changed in biasing, changes the size of bias according to the result of determination of long decision circuit 17 outputs of symbol.The accumulating operation that biasing adder operation circuit 16, the bias that biasing change circuit 18 is provided are added in phase place variation in the symbol is as a result on the PS1, then with the accumulating operation of gained as a result PS2 export to loop filter 50.

The accumulation calculating that has added phase place variation in the symbol of bias is PS2 as a result, exports as phase place variation PS3 through the unwanted noise of loop filter 50 filterings (for example, the signal of adjacent channel) back.

As mentioned above; because the long at interval size of intending the bias that adds that changed of long and protection according to significant character; and can set the long and at interval long only time window of each protection position to each significant character; make that intersymbol interference is difficult to take place, and the error rate of regenerated signal is not exerted an influence.

In addition; because can adjust the gain of amplifying circuit arbitrarily according to significant character length, protection interval length and differential modulation parts, synchronous modulation parts; the sum of errors control signal of clock signal can be adjusted in certain relation, and the introducing of clock signal can not be related with modulating part and symbol length.

And then, owing to improved the introducing performance of clock signal, can suppress the error ratio characteristic of regenerated signal to be improved because of interfering the impairment that causes between subcarrier.

In addition, by the value of being biased on the phase place of clock signal, the time window that makes discrete Fourier transform (DFT) from original position to the certain position of reach, even make when clock signal band frequency error and phase error, also be difficult to cause intersymbol interference, and the error rate of regenerated signal do not exerted an influence.

Embodiment 3

The structure of embodiment 3 can be made equalization and handle in several symbols (a plurality of symbol) scope to the accumulation calculating result who adds the phase place variation behind the bias of explanation among the embodiment 2, then the result is offered loop filter.

Fig. 7 is the block diagram of the time signal reproducing circuit of the embodiment of the invention 3.

Have, in the time signal reproducing circuit 132 shown in Figure 7, all adopt identical mark for the part identical with time signal reproducing circuit 130 actions of time signal reproducing circuit in the past 115 shown in Figure 9 and embodiment 1 shown in Figure 2, explanation is omitted.

In addition, adopt the structure of OFDM receiver of the time signal reproducing circuit 132 of present embodiment 3, the structure shown in Figure 1 with embodiment 1 is identical, and time signal reproducing circuit 132 is equivalent to time signal reproducing circuit 130 parts among the embodiment 1.

Among Fig. 7 19 is averaging circuit, with the accumulation calculating that added the phase place variation in the prosign of bias of above-mentioned biasing adder operation circuit 16 outputs PS2 as a result, makes equalization at least in the scope more than several symbols and handles.

The accumulation calculating result of the phase place variation by averaging circuit 19 equalizations is provided for loop filter 50.

Below, its action is described.

Above-mentioned phase place variation PS comprises the error of calculation or the Gaussian noise that take place when this phase place variation PS calculates.

Comprise in the phase place variation under the situation of the error of calculation,, also can include the error of calculation among the accumulation calculating result of accumulating operating circuit 15 outputs on accumulating operating circuit 105, adding the error of calculation of described phase place variation.

The accumulation calculating result of phase place variation who comprises a symbol of this error of calculation is transfused to average circuit 19 and makes equalization at least handle in several symbolic ranges.

So, handle by the equalization in several symbolic ranges and to remove the error of calculation or Gaussian noise, will not contain then that the phase place variation offers loop filter 50 in (perhaps comprising its degree unlikely error that action is exerted an influence) symbol of error.

As above-mentioned, adopt in several symbolic ranges the accumulation calculating result is done the equalization processing, to remove the structure of the error of calculation or Gaussian noise, can improve the introducing performance of clock signal.

Embodiment 4

Comprise (loop) filter gain change circuit (filter gain change circuit) among the embodiment 4; the function of this circuit is; as the OFDM transmission of Japanese digital terrestrial broadcasting standard code; the quantity of the subcarrier in the significant character can changed in the receiving system of the ofdm signal that transmits again, (the phase place variation in the prosign of accumulating operating circuit 15 accumulating operations) accumulation calculating value PS1 carried out the gain of the loop filter 50 of filtering according to the length or the protection length change at interval of significant character.

Fig. 8 is the block diagram of the time signal reproducing circuit of embodiment 4.

Have, in time signal reproducing circuit shown in Figure 8 133, its part identical with time signal reproducing circuit 130 actions of time signal reproducing circuit in the past 115 shown in Figure 9 and embodiment 1 shown in Figure 2 adopts identical mark again, and explanation is omitted.

In addition, adopt the structure of 0FDM receiver of the time signal reproducing circuit 133 of present embodiment 4, the structure shown in Figure 1 with embodiment 1 is identical, and time signal reproducing circuit 133 is equivalent to time signal reproducing circuit 130 parts among the embodiment 1.

Among Fig. 8 51 changes circuit in order to the filter gain that length or protection length at interval according to significant character change the gain of loop filter 50.

Below, its action is described.

The long decision circuit 17 of symbol is decision making to length of the significant character in the ofdm signal of input and protection interval length, and result of determination is exported.

According to result of determination, the filter gain of filter gain change circuit 51 change loop filters 50.Phase place variation in the prosign that accumulating operating circuit 15 provides is exported as the phase place incremental data through the unwanted noise of loop filter 50 filterings (for example, the signal of adjacent channel) back by the gain of setting with filter gain change circuit 51.

For example, according to Japanese ground-wave digital broadcasting standard, in the OFDM transmission, the number of sub that significant character comprised should have three kinds of different patterns in accordance with regulations.

The length of significant character is different different because of pattern, promptly uses the clock regenerating signal ofdm signal that the same phase error is arranged, and the phase place variation between each pattern in the prosign also can be different.

For example, long at the significant character of regulation is in 4 times the mode 3 of pattern 1, phase place variation in the prosign just is greater than the phase place variation in the prosign in the pattern 1 (this is because significant character is longer, has caused the cause of the phase place change increase of significant character phase).

So, the relation of control signal relative time clock signal errors can be different different because of pattern, and this has caused the introducing performance of clock signal uncertain.

Therefore; by and the protection at interval long gain that change loop filter long according to significant character; just can adjust the control signal of the sum of errors clock signal of the clock signal on all patterns with certain relation, make the introducing of clock signal can not be subjected to the different influence of pattern.

[effect of invention]

The present invention owing to have above-mentioned structure, can be achieved as follows effect.

The clock regenerating signal device relevant with the present invention is characterized in that having adopted following institute The various circuit of stating: use the subcarrier that obtains based on main carrier frequency demodulating ofdm modulation signal The clock signal of band signal defined frequency is carried out digitized processing, and with digitized solution The demodulator circuit of tonal signal output; Above-mentioned restituted signal according to this demodulation method output is prolonged Late and with the delay circuit of the restituted signal output that postpones; Based on above-mentioned restituted signal and above-mentioned Comprise during the symbol of these two signals of Delay Demodulation signal with above-mentioned ofdm modulation signal Pilot signal between the phase place variation output circuit of phase place variation output; Based on usefulness The output that this phase place variation output circuit obtains is controlled the frequency of above-mentioned clock signal Control circuit. Thereby, can improve the introducing performance of clock signal.

Be further characterized in that the output that has phase place variation output circuit carries out accumulation calculating Accumulating operating circuit; Thus, although the phase between the adjacent pilot frequencies signal that can once calculate The maximum of position variation is+2 π, yet can make phase place change in the symbol by accumulation calculating The detection range of amount enlarges.

Be further characterized in that the biasing that the output that has at accumulating operating circuit adds upper offset adds The method computing circuit; Thus, can be the suitableeest according to the long setting of each significant character length and protection interval The time window that closes makes intersymbol interference be difficult to take place, and can not give the bit error rate of regenerated signal Bring impact.

Be further characterized in that the significant character with judgement restituted signal is long and protection interval length The symbol lengths decision circuit can become according to the output of this symbol lengths decision circuit owing to have The structure of more biasing size can arrange each significant character length and protection interval long optimum Time window.

Be further characterized in that and have in a plurality of symbolic ranges of ofdm signal biasing addition fortune The structure of to handle averagely is made in the output of calculating circuit; Thus, can remove Gaussian noise, carry The introducing performance of high clock signal.

Be further characterized in that the filtered electrical that has the output filtering of biasing adder operation circuit The impact of intersymbol interference can be got rid of in the road.

Be further characterized in that the significant character with judgement restituted signal is long and protection interval length The symbol lengths decision circuit, and according to the output of this symbol lengths decision circuit change wave filter The structure of gain; Thus, can on whole significant character length, transfer within the specific limits The output of domain path filter can realize the stable of clock signal introducing performance.

The receiving system relevant with the present invention possesses various circuit as described below: use based on The signal defined frequency of the subcarrier band that main carrier frequency demodulating ofdm modulation signal obtains Clock signal carry out a demodulator circuit of digitized processing; Based on this demodulation electricity The output that rood arrives is with the secondary demodulation circuit of the restituted signal output of each passage; Should to using The restituted signal that the secondary demodulation circuit produces carries out the phase-correcting circuit of phasing; To use The output delay that this phase-correcting circuit obtains and the deferred telegram that the restituted signal that postpones is exported The road; Based on above-mentioned restituted signal and these two signals of Delay Demodulation signal above-mentioned OFDM is modulated The phase place of the phase place variation output between the pilot signal that comprises during the symbol of signal The variation output circuit; Based on the output of this phase place variation output circuit to above-mentioned clock The control circuit that the frequency of signal is controlled. Therefore, can obtain to have improved clock signal Introduce the receiving system of performance.

Be further characterized in that the output that has phase place variation output circuit carries out accumulating operation Accumulating operating circuit; Although the phase place variation between the adjacent pilot frequencies signal of once calculating Maximum is+2 π, but can enlarge detecting of phase place variation in the symbol by accumulation calculating Scope.

Be further characterized in that and have the biasing addition fortune that adds upper offset in the output of summation circuit Calculate circuit; Thus, can be optimal according to the long setting of each significant character length and protection interval Time window makes intersymbol interference be difficult to take place, and brings can for the bit error rate of regenerated signal Impact.

Be further characterized in that the significant character with judgement restituted signal is long and protection interval length The symbol lengths decision circuit, having can be inclined to one side according to the output change of this symbol lengths decision circuit Put the structure of size; Thus, can arrange long to each significant character and the protection interval is long closes most Suitable time window.

Be further characterized in that the significant character with judgement restituted signal is long and protection interval length The symbol lengths decision circuit has the output change filtering according to this symbol lengths decision circuit The structure of device gain size; Thus, can adjust within the specific limits for all effectively according with The output of number long loop filter realizes that clock signal introduces the stable of performance.

The clock signal regeneration method relevant with the present invention is characterized in that having adopted following institute The various steps of stating: use the subcarrier that obtains based on main carrier frequency demodulating ofdm modulation signal The clock signal of band signal defined frequency is carried out digitized processing, and with digitized solution The demodulation step of tonal signal output; The above-mentioned restituted signal that obtains by this demodulation step is prolonged Late and obtain the delay circuit of delayed Delay Demodulation signal; Based on above-mentioned restituted signal with Comprise during the symbol of these two signals of Delay Demodulation signal with above-mentioned ofdm modulation signal Pilot signal between the phase place variation output step of phase place variation output; Based on usefulness The output that this phase place variation output step obtains is controlled the frequency of above-mentioned clock signal The control step. Thus, can improve the introducing performance of clock signal.

The method of reseptance relevant with the present invention possesses various steps as described below: use based on The signal defined frequency of the subcarrier band that main carrier frequency demodulating ofdm modulation signal obtains Clock signal carry out a demodulation step of digitized processing; Based on once separating pacing with this The rapid output that obtains is with the secondary demodulation step of the restituted signal output of each passage; Will be with being somebody's turn to do The phasing step of the phasing of the restituted signal that the secondary demodulation step obtains; Will be with being somebody's turn to do The output delay that the phasing step obtains and the delay step that the restituted signal that postpones is exported Suddenly; Based on above-mentioned restituted signal and these two signals of Delay Demodulation signal above-mentioned OFDM is modulated The phase place of the phase place variation output between the pilot signal that comprises during the symbol of signal Variation output step; Based on exporting the output of step acquisition with this phase place variation to above-mentioned The control step that the frequency of clock signal is controlled. Thus, can realize making clock signal The introducing performance, the method for reseptance of raising.

[brief description of drawings]

The block diagram of the OFDM receiver of the time signal reproducing circuit of [Fig. 1] employing embodiment of the invention 1.

The time signal reproducing circuit of [Fig. 2] embodiment of the invention 1 block diagram.

[Fig. 3] is illustrated in the time signal reproducing circuit of the embodiment of the invention 1, when there is frequency error in the clock signal, and the phase error that in the subcarrier frequency composition of fast Fourier transform circuit (translation circuit) output, occurs.

The schematic diagram of the operating principle of [Fig. 4] embodiment of the invention 1.

The flow chart of the action of [Fig. 5] expression embodiment of the invention 1.

The time signal reproducing circuit of [Fig. 6] embodiment of the invention 2 block diagram.

The time signal reproducing circuit of [Fig. 7] embodiment of the invention 3 block diagram.

The time signal reproducing circuit of [Fig. 8] embodiment of the invention 4 block diagram.

The block diagram of [Fig. 9] receiving system in the past.[mark explanation]

3 differential ference spiral circuit; 6,7 RAM (memory circuit); 10 sign circuit for reversing; 11 complex multiplication circuit; 12 ROM; 13,70,71 computing circuits; 40 selectors; 31,41 switches; 32,42 phase-correcting circuits; 15 accumulating operating circuits (accumulating operation calculation means); 16 biasing adder operation circuits (biasing add operation means); The long decision circuit of 17 symbols (the long decision means of symbol); 18 biasing change circuit (biasing change means); 19 average circuits (average means); 51 filter gains change circuit (filter gain change means); 105 A/D change-over circuits; 112 fast Fourier transform circuits; 115,130～133 time signal reproducing circuits; 116 clock signal oscillators; 120 subcarrier frequency signals demodulator circuits.

Claims

1. clock regenerating signal device is characterized in that comprising:

Use the clock signal of the signal defined frequency of the subcarrier band that obtains based on main carrier frequency demodulating ofdm modulation signal to carry out digitized processing, and with the demodulator circuit of digitized restituted signal output;

Make above-mentioned restituted signal delay that obtains by described demodulator circuit and the delay circuit that delayed delay restituted signal is exported;

The phase place variation output circuit of the phase place variation output between the pilot signal that comprises during the symbol with described ofdm modulation signal based on described restituted signal and these two signals of described delay restituted signal;

The control circuit of the frequency of described clock signal being controlled based on the output of described phase place variation output circuit.

2. the clock regenerating signal device of claim 1 is characterized in that: have make the accumulation calculating circuit of accumulation calculating via the output of described phase place variation output circuit.

3. the clock regenerating signal device of claim 2 is characterized in that: have make the biasing adder operation circuit of bias treatment via the output of described accumulation calculating circuit.

4. the clock regenerating signal device of claim 3; it is characterized in that: have the long decision circuit of symbol long to the restituted signal significant character and that protection interval progress row is judged, and have structure according to the output change bias size of the long decision circuit of described symbol.

5. the clock regenerating signal device of claim 3 is characterized in that: have the structure that equalization is handled is made in the output of described biasing adder operation circuit in a plurality of symbolic ranges of ofdm signal.

6. the clock regenerating signal device of claim 3 is characterized in that: have filter circuit for filtering is carried out in the output of described biasing adder operation circuit.

7. receiving system, it possesses following circuit:

Use the clock signal of the signal defined frequency of the subcarrier band that obtains based on main carrier frequency demodulating ofdm modulation signal to carry out a demodulator circuit of digitized processing;

Based on the secondary demodulation circuit of the output that obtains with a described demodulator circuit with the restituted signal output of each passage;

The phase-correcting circuit of the phasing of the restituted signal that will obtain with described secondary demodulation circuit;

The output delay that will obtain with described phase-correcting circuit and with the delay circuit of the restituted signal output that postpones;

The phase place variation output circuit of the phase place variation output between the pilot signal that comprises during the symbol with above-mentioned ofdm modulation signal based on described restituted signal and these two signals of described delay restituted signal;

Based on the control circuit of the frequency of described clock signal being controlled with the output of described phase place variation output circuit acquisition.

8. the receiving circuit of claim 7 is characterized in that: have make the accumulation calculating circuit of accumulation calculating via the output of described phase place variation output circuit.

9. the receiving circuit of claim 8 is characterized in that: have make the biasing adder operation circuit of bias treatment via the output of described accumulation calculating circuit.

10. the receiving circuit of claim 9 is characterized in that: have the long decision circuit of symbol long to the restituted signal significant character and that protection interval progress row is judged, and have the structure according to the output change bias size of the long decision circuit of described symbol.

11. the receiving circuit of claim 9 is characterized in that: have the structure that equalization is handled is made in the output of described biasing adder operation circuit in a plurality of symbolic ranges of ofdm signal.

12. the receiving circuit of claim 9 is characterized in that: have filter circuit for filtering is carried out in the output of described biasing adder operation circuit.

13. a clock signal regeneration method, described method comprises:

Use the clock signal of the signal defined frequency of the subcarrier band that obtains based on main carrier frequency demodulating ofdm modulation signal to carry out digitized processing, and with the demodulation step of digitized restituted signal output;

Make above-mentioned restituted signal delay that obtains by described demodulation step and the delay step that delayed delay restituted signal is exported;

The phase place variation output step of the phase place variation output between the pilot signal that comprises during the symbol with described ofdm modulation signal based on described restituted signal and these two signals of described delay restituted signal;

Based on the controlled step of the frequency of described clock signal being controlled with the output of described phase place variation output step acquisition.

14. a method of reseptance, it possesses following controlled step:

Use the clock signal of the signal defined frequency of the subcarrier band that obtains based on main carrier frequency demodulating ofdm modulation signal to carry out a demodulation step of digitized processing;

Based on the secondary demodulation step of the output that obtains with a described demodulation step with the restituted signal output of each passage;

The phasing step of the phasing of the restituted signal that will obtain with described secondary demodulation step;

The output delay that will obtain with described phasing step and with the delay step of the restituted signal output that postpones;

The phase place variation output step of the phase place variation output between the pilot signal that comprises during the symbol with above-mentioned ofdm modulation signal based on described restituted signal and these two signals of described delay restituted signal;