CN1343957A - Screen overlapping system and method - Google Patents
Screen overlapping system and method Download PDFInfo
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- CN1343957A CN1343957A CN 01137134 CN01137134A CN1343957A CN 1343957 A CN1343957 A CN 1343957A CN 01137134 CN01137134 CN 01137134 CN 01137134 A CN01137134 A CN 01137134A CN 1343957 A CN1343957 A CN 1343957A
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Abstract
To provide the overlay function by hardware by addition to a general graphic controller. This overlay data processor has an address search circuit, an internal video memory, and an overlay data processing circuit. The address search circuit always monitors an object address at the time of the read operation of the graphic controller and the internal video memory stores image data to be overlaid. When a read address specified by the graphic controller enters an address area to be overlaid, the image data from the internal video memory are transferred to the graphic controller instead of image data from an ordinary video memory.
Description
The present invention is that denomination of invention is " screen overlapping system and a method ", and application number is " 96118514.7 ", and the applying date divides an application for " on November 27th, 1996 ".
The present invention relates to a screen overlay (stack) system and method, they are mainly used in computer system; Specifically, be the screen overlapping system and the method for use overlapped memories (RAM).
Recently,, the requirement of computer system is constantly increased, require to provide and can handle the peripheral circuit that visual graphics controller and performance are improved along with multimedia expansion.Today, in order on a screen, to show active images and the still image that obtains from a plurality of sources simultaneously, the overlapping and display technique of image, promptly overlap technique becomes particularly important.
Main traditional overlap technique is 1) the image display signal system and 2 that output is switched at a high speed is provided) system of shared storage.Yet there is following point in these two systems.
1) provides the image display signal system that output is switched at a high speed
Now, with reference to Fig. 3 this system is made an explanation.In Fig. 3, shown a graphics controller 31, it is connected on the system bus 30, and comprehensive control of screen display is provided; A video memory 33, display data on the screen is stored in wherein under the control of graphics controller 31; An overlapped data processor 34, store and handle be stored in video memory 33 in the different video data of data; And a commutation circuit 32, between from the picture intelligence 35 of graphics controller 31 and picture intelligence 36, switch from overlapped data processor 34.
But as mentioned above, this system needs two independently visual output circuits usually: a graphics controller circuit and an overlapped data processor circuit.And, because it is image display signal is a simulating signal, more complicated when the design of required circuit of processing signals and integrated circuit board just is digital signal than image display signal.In addition, because these two circuit have adopted redundant analog structure, therefore manufacturing expense also increases.If before image display signal is converted to simulating signal, switch, just must make the asynchronous shows signal phase mutually synchronization of coming from two unlike signal sources.
2) shared-memory system
Now, in conjunction with Fig. 4 this system is made an explanation.This system comprises: a graphics controller 42, it with connect with the identical system bus 41 of the system bus 31 of Fig. 3, comprehensive control of screen display is provided; A video memory 46, display data on the screen is stored in wherein under the control of graphics controller; And an overlapped data processor 47, store and handle be stored in video memory 46 in the different video data of data.Also need an arbitration functions that is used for the memory access arbitration, so that graphics controller 42 and overlapped data processor 47 can the same video memory 46 of alternate access.Use arbitration functions can solve the problem that same video memory 46 is visited simultaneously.
According to this system, graphics controller 42 must possess the arbitration functions that is used for accessing video storer 46.The graphics controller that only has arbitration functions could use in native system.And since the graphics controller that this arbitration functions is arranged on market, sold seldom, and its manufacturing cost is also quite expensive, so use the selection of this graphics controller just to be very limited in computer system.And in shared-memory system, when using the data of superimposed images, in fact the data of the raw image in address have been covered by the data of the identical superimposed images in address.So when pictorial data was become again original image data, original image data must write the same address of video memory again, this handles the time that needs cost extra.
An object of the present invention is to increase an overlapping function for the generic graphic controller, solve the problem of traditional overlapping system by using hardware.
More particularly, according to the present invention, the superposing circuit that provides, this circuit (1) is owing to use digital circuit execution graph image data is handled, thereby simplicity of design and low cost of manufacture; (2) owing to carrying out the phase mutually synchronization, so need not to use the communication of fast clock signal to two different shows signal; And (3) can use the generic graphic controller of extensively selling on market.
In order to realize the present invention, introduce an improved recently overlapped data processor.The characteristic element of this overlapped data processor comprises: addressing circuit, interior video storer and an overlapped data controller.
Addressing circuit is the destination address of monitoring graphics controller read operation always, is stored in the interior video storer and be used for overlapping pictorial data.Read the address when dropping in the address area of overlapping target by the graphics controller appointment when one, the overlapped data controller is controlled a data buffer that is connected with graphics controller and is transmitted the next pictorial data of video memory internally to graphics controller, rather than from the next pictorial data of video memory commonly used.
By above-mentioned processing, the pictorial data of expectation obtains overlapping in the screen position of expectation.
The present invention is described with reference to the accompanying drawings, wherein:
Fig. 1 is a figure of describing to realize computer system of the present invention.
Fig. 2 is a block scheme of describing to realize inside computer system logical circuit of the present invention.
Fig. 3 is a block scheme of describing traditional image display signal output high speed switched system.
Fig. 4 is a block scheme of describing traditional shared-memory system.
Fig. 5 is a block scheme of describing to realize peripheral pattern circuit of the present invention.
Fig. 6 is a more detailed block diagram of describing to realize an overlapped data processor of the present invention.
Fig. 7 is the process flow diagram that carries out the superimposed image data processing with the present invention.
Fig. 8 obtains the process flow diagram of pictorial data processing procedure with the present invention from showing A/D converter.
Fig. 9 is a process flow diagram of obtaining the processing procedure of pictorial data with the present invention by system bus.
By following theme order, one embodiment of the invention are described herein.
A. personal computer system (Fig. 1)
B. personal computer system's hardware configuration (Fig. 2)
C. the peripheral circuit of graphics controller (Fig. 5)
The inner structure of overlapped data processor D. of the present invention (Fig. 6)
E. processing procedure of the present invention (Fig. 7 to 9)
Reason for convenience, the setting of system of the present invention and processing procedure will with one recently on market popular notebook computer describe.But use of the present invention is not limited in notebook computer, can also be applied to the computer system of multiple other type, as desk-top and console mode computer system.
A. personal computer system (Fig. 1)
Fig. 1 is a synoptic diagram of describing to implement complete computer of the present invention.The main body of computer system can be a portable PC as shown in the figure, or the PC of desk-top or other type, or a workstation.As a standard, computer system 10 comprises: a keyboard 12, use as character input device; A display panels 13 uses as character and graphical output device; A CD-ROM drive 14 is as a high capacity storage medium equipment; A loudspeaker, as the speech etc. output device; And a video frequency pick-up head 15 that adds recently, use as image input device.Because the details of keyboard 12 and display panels 13 and structure of the present invention directly do not concern, so do not show in Fig. 1.
B. personal computer system's hardware configuration (Fig. 2)
Fig. 2 is the module diagram of logical circuit, and this logical circuit is normally on the motherboard (surface plate) of Fig. 1 notebook computer 10 inside.This computer system has a plurality of buses to link to each other with the equipment with different disposal speed, also has a circuit that is called bridge, and it carries out the protocol conversion between bus, so that the intercommunication of a plurality of bus.As specific bus structure, shown a CPU local bus 212 that directly links to each other among Fig. 2 with CPU 202; The pci bus 213 and 216 that communicates with the peripheral hardware of relative high speed; Reach the isa bus 221, pcmcia bus 219 and the IDE bus 217 that communicate with the peripheral hardware of relative low speed.
And then, in Fig. 2, shown a main bridge joint/Memory Controller 204, be used to connect cpu bus 212 and pci bus 213; A PCI-ISA bus bridge circuit 215 is used to connect pci bus 213 and isa bus 221; With a PCI-PCMCIA bus bridge circuit 214, be used to connect pci bus 213 and pcmcia bus 219.
Each bus links to each other with a plurality of peripheral hardwares that mate with corresponding bus processing speed respectively.For example, the CPU local bus 212 that speed is the highest is directly communicated by letter with CPU 202.Pci bus 213 is communicated by letter with high speed graphic/display controller 222.Isa bus 221 is with keyboard controller 229, Audio Controller 230 and communicate by letter as the super I/O controller 231 of general purpose I/O (input and output) controller.
Main bridge joint/Memory Controller 204 not only possesses the bus bridge function, and also has the storer control function, and it is connected by a memory data impact damper 205 with primary memory RAM 207 with BIOS ROM 206.
Figure/the display controller 222 that links to each other with pci bus 213 has a screen display video memory 223 as element.Graphics/video controller 222 uses a digital signal to communicate by letter with the LCD panel by impact damper 224, will pass through the analog video input digitization of AFE (analog front end) (AFE) 225 inputs from external unit, and obtain numerical data.
C. the peripheral circuit of graphics controller (Fig. 5)
Fig. 5 describes the synoptic diagram that the present invention is provided with.Setting among Fig. 5 is corresponding to the background among above-mentioned Fig. 3 and Fig. 4.As primary clustering, in Fig. 5, shown a graphics controller 502 (corresponding to 222 among Fig. 2) that links to each other with system bus 501 (213 in the corresponding diagram 2); A video memory 505 (223 among Fig. 2), pictorial data is stored in wherein; An overlapped data processor 503; With a data impact damper 504.One of difference of setting shown in the present invention and Fig. 3 and Fig. 4 is that this figure peripheral circuit includes data buffer 504 between video memory 505 and graphics controller 502.Another is not both overlapped data processor 503 and directly links to each other with system bus 501, and promptly the CPU of computer system can directly visit overlapped data processor 503.Overlapped data processor 503 links to each other with the output control signal of impact damper 504 by a gate control signal 512, and utilizes gate control signal 512 to activate or stop from the data of video memory 505 and export.
More particularly, when the superimposed data processor 503 of the output of gate control signal 512 activated, impact damper 504 outputed to data bus 510 to the data from video memory 505.When the superimposed data processor 503 of the output of gate control signal 512 stoped, impact damper 504 did not just output to data bus 510 to the data from video memory 505.
Overlapped data processor 503 itself comprises video memory, and the back will be described to, and through the data bus 511 and the data bus 510 of communicating by letter with graphics controller 502 pictorial data is sent to graphics controller 502.
Receive after the pictorial data of video memory 505 and overlapped data processor 503, graphics controller 502 they are handled and by display signal line 508 with result data deliver to one with display device that computer system 10 is connected on (not shown), finally on display device, show a superimposed image.
The inner structure of overlapped data processor D. of the present invention (Fig. 6)
In Fig. 6, shown detailed inner structure as the overlapped data processor 503 of one of characteristic element of the present invention among Fig. 5.
The main element of an overlapped data processor 600 (corresponding to 503 among Fig. 5) comprises that an overlapped data controller 607 is controlled whole overlapped data processor 600; A Memory Controller 610 links to each other with overlapped data controller 607, controls interior video storer 604; A system bus interface circuit 609 is used as an interface with system bus 601; An addressing circuit 606 monitors the destination address that reads and writes data, and data are to be sent to video memory 604 through address/control line 613 from the graphic chips 602 as graphics controller; A digital display interface circuit 608, for overlapping data processor 600 is obtained digital displaying signal from show A/D (D/A) converter 605, A/D (D/A) converter 605 can be a digital signal with the analog signal conversion of coming from external video equipment; And a format converter 611, for multiple video data form is changed, for example RGB and YUV.Overlapped data processor 600 can be designed as and comprises data buffer 603.Internal storage 612 can design outside overlapped data processor 600.
The processing of being done now with reference to overlapped data processor 600 among Fig. 7 to 9 couple of Fig. 6 is described.
E. processing procedure of the present invention (Fig. 7 to 9)
Fig. 7 is when two pictorial data are superimposed, the process flow diagram that the present invention dealt with.At first, in square frame 71, specify in the used address realm of overlapped data in the video memory zone.In square frame 72, addressing circuit 606 monitors an address all the time, next step graphic chips 602 will read the data in this address from video memory 604 (505 the corresponding diagram 5), addressing circuit also judges whether the address read is dropped in the address realm into the overlapped data appointment.If the address of reading is in the address area of overlapped data, program proceeds to square frame 73.If the address of reading is outside address realm, program is returned square frame 72, continues to monitor the address of reading there.At square frame 73, because graphic chips 602 will be read as the address area of overlapping appointment, the inner overlapped data controller 607 control data impact dampers 603 of overlapped data processor 600 usefulness.
In fact overlapped data controller 607 stops the output of data buffer 603 (504 in the corresponding diagram 5) by control line 621.Then program proceeds to square frame 74.Overlapped data processor 600 usefulness internal storage controllers 610 read in the storer 612 internally wants overlapping pictorial data.Overlapped data controller 607 is exported the overlapped data that storer 612 internally reads by data line 613 and 614.As a result, graphic chips 602 is read overlapped data in the storer 612 internally, rather than the data in the video memory 604.Overlapped data is delivered to a display device by graphic chips 602 and is shown on screen.Program turns back to square frame 72 afterwards, and said process repeats, and the pictorial data of expectation is overlapping in the desired region of display device.
The process flow diagram of the processing procedure that Fig. 8 is an overlapped data processor 600 when external video equipment is obtained pictorial data.At square frame 81, specify a data form, after changing, the data that obtain from external video equipment will use this form.At square frame 82, digital visual interface circuit 608 is delivered to format converter 611 to the video data that receives from video a/d converter 605.At square frame 83, receive video data after, format converter 611 is converted to the data with specified format in the square frame 81 to the video datas of obtaining.Then, the video data of specific data form is written into internal storage 612 under the control of Memory Controller 610.
The process flow diagram of the processing procedure that Fig. 9 is an overlapped data processor 600 when system bus 601 is obtained pictorial data.Specify a data layout that after conversion, uses (square frame 91).System bus interface circuit 609 receives passes through system bus 601 from main equipment, as processor, mails to the pictorial data of overlapped data processor 600, and pictorial data is delivered to format converter 611 (square frame 92).Format converter 611 is converted to the data with specific data form to the pictorial data of receiving.Pictorial data through conversion is written into video memory 612 (square frame 93) under the control of Memory Controller 610.By the above-mentioned processing procedure of being carried out by overlapped data processor 600, from a main equipment, as processor, the pictorial data of coming is admitted to video memory.
As conclusion, following content with of the present invention be provided with relevant.
(1) image processing facility, it can overlapping a plurality of images, and comprising: (a) image processing controller is used for carrying out image processing and control; (b) video memory, it links to each other with the image processing controller, is used for the storage of pictorial data; Reach (c) overlapping processor, it links to each other with the image processing controller, and has an inner superimposed image storer, when image processing controller during from predetermined address range reading of data of video memory, it will be stored in the pictorial data in the superimposed image storer rather than be stored in pictorial data in the video memory, output to the image processing controller.
(2) image processing facility of mentioning in (1) also comprises: (d) data impact damper, it connects visual processing controller and video memory, when image processing controller during from the predetermined address range reading of data of video memory, the pictorial data output in the data buffer is prevented from.
(3) picture overlapping processors, it is connected with a video memory with a graphics controller and cooperates, and carries out picture overlapping, and it comprises: (a) addressing circuit, when graphics controller from video memory during reading of data, the address that will read in the monitoring video storer; (b) overlapped memories, it is independent of video memory, stores a superimposed image; And (c) circuit, when addressing circuit measures the presumptive address that data read, will be sent to graphics controller corresponding to the data of presumptive address in the data of presumptive address in the overlapped memories rather than the video memory.
(4) the picture overlapping processor of mentioning in (3) also comprises: (d) buffer circuit, and it links to each other with video memory, and the control of video storer is to the data output of graphics controller.
(5) the picture overlapping processor of mentioning in (3) also comprises: (e) system bus interface circuit, be used for and the system bus swap data, and it allows the CPU of computer system directly to visit overlapped memories.
(6) the picture overlapping processor of mentioning in (3) also comprises: (f) format converter is used to carry out the format conversion of pictorial data.
(7) the picture overlapping processor of quoting in (3) also comprises: (g) visual interface is used for obtaining pictorial data from an external unit.
(8) computer systems comprise a picture overlapping processor that is connected with video memory and cooperates and carry out picture overlapping with graphics controller, and system comprises: (a) processor; (b) primary memory; (c) system bus is used to connect external unit; (d) graphics controller links to each other with system bus; (e) video memory links to each other with graphics controller; Reach (f) overlapping processor, link to each other with system bus, overlapping processor comprises, (i) addressing circuit, when graphics controller during from the video memory reading of data, the address of the data that will read in the monitoring video storer, (ii) overlapped memories, it is independent of video memory, store a superimposed image, and (iii) circuit, when addressing circuit measures the presumptive address that data read, will be sent to graphics controller corresponding to the data of presumptive address in the data of presumptive address in the overlapped memories rather than the video memory.
(9) picture overlapping methods, comprise a graphics controller to one, video memory that links to each other with graphics controller links to each other, adopts the computer system of the picture overlapping processor of overlapped memories and superimposed image with one with graphics controller and video memory, comprise: the step that (a) reads an address, in video memory, when graphics controller from video memory during reading of data, the data in this address will be read out; (b) step of compare address will read address and the presumptive address comparison that the address step obtains; And (c) when determining that address and presumptive address in the comparison step of address mates, carry out a step, the data corresponding to presumptive address in the data of presumptive address rather than the video memory in the overlapped memories are sent to graphics controller.
As mentioned above, according to configuration of the present invention,, solved the problem of traditional overlapping system by the overlapping function that uses hardware on the generic graphic controller, to increase.
Claims (4)
1. image processing facility, it can overlapping a plurality of images, comprising:
An image processing controller is used for carrying out image processing and control; And
Video memory, it links to each other with described image processing controller, is used for the storage of pictorial data, it is characterized in that also comprising:
An overlapping processor, it links to each other with described image processing controller, and has an inner superimposed image storer, when described presentation manager controller during from predetermined address range reading of data of described video memory, it will be stored in the pictorial data in the described superimposed image storer rather than the pictorial data that is stored in the described visual reservoir outputs to described image processing controller; And
Be used for controlling the device of output of the pictorial data of described video memory.
2. image processing facility as claimed in claim 1, it is characterized in that described control device is a data impact damper, it connects between described image processing controller and the described video memory, when described image processing controller during from the described predetermined address range reading of data of described video memory, the pictorial data output in the data buffer is prevented from.
3. a computer system comprises a picture overlapping processor that is connected with video memory and cooperates and carry out picture overlapping with graphics controller, also comprises:
A processor;
Primary memory;
A system bus is used to connect external unit;
A graphics controller links to each other with described system bus;
Video memory links to each other with described graphics controller, it is characterized in that also comprising:
Be used for controlling the device of output of the data of described video storage; And
An overlapping processor links to each other with described system bus,
Described overlapping processor comprises,
An addressing circuit, when described graphics controller when described video memory reads described data, monitor the address of the data that will read in the described video memory,
Overlapped memories, it is independent of described video memory, stores a superimposed image, and
A circuit when described addressing circuit measures the presumptive address that data read, will be sent to described graphics controller corresponding to the data of presumptive address described in the described overlapped memories rather than in the data of the described presumptive address of described video memory.
4. picture overlapping method, comprise a graphics controller to one, video memory that links to each other with described graphics controller links to each other, adopts the computer system of the picture overlapping processor of overlapped memories and superimposed image with one with described graphics controller and described video memory, is characterized as:
(a) read the step of an address, in described video memory, when described graphics controller reads described data from described video memory, the data in this address will be read out;
(b) step of more described address reads address that the address step obtains and a presumptive address relatively with described; And
(c) when determining described address in the comparison step of described address and described presumptive address coupling, carry out a step, the data corresponding to presumptive address described in the data of described presumptive address rather than the described video memory in the described overlapped memories are sent to described graphics controller.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP308668/1995 | 1995-11-28 | ||
| JP30866895A JP3245032B2 (en) | 1995-11-28 | 1995-11-28 | Image overlay apparatus and method |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN96118514A Division CN1091284C (en) | 1995-11-28 | 1996-11-27 | Screen overlay system and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1343957A true CN1343957A (en) | 2002-04-10 |
| CN1189840C CN1189840C (en) | 2005-02-16 |
Family
ID=17983853
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN96118514A Expired - Lifetime CN1091284C (en) | 1995-11-28 | 1996-11-27 | Screen overlay system and method |
| CNB01137134XA Expired - Lifetime CN1189840C (en) | 1995-11-28 | 1996-11-27 | Screen overlapping system and method |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN96118514A Expired - Lifetime CN1091284C (en) | 1995-11-28 | 1996-11-27 | Screen overlay system and method |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP3245032B2 (en) |
| CN (2) | CN1091284C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100365701C (en) * | 2005-09-29 | 2008-01-30 | 广东威创日新电子有限公司 | Multilayer real time image overlapping controller |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60245032A (en) * | 1984-05-18 | 1985-12-04 | Fujitsu Ltd | Video display device |
| JP3536312B2 (en) * | 1992-06-10 | 2004-06-07 | セイコーエプソン株式会社 | Video processing device and computer system |
-
1995
- 1995-11-28 JP JP30866895A patent/JP3245032B2/en not_active Expired - Fee Related
-
1996
- 1996-11-27 CN CN96118514A patent/CN1091284C/en not_active Expired - Lifetime
- 1996-11-27 CN CNB01137134XA patent/CN1189840C/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100365701C (en) * | 2005-09-29 | 2008-01-30 | 广东威创日新电子有限公司 | Multilayer real time image overlapping controller |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3245032B2 (en) | 2002-01-07 |
| JPH09160736A (en) | 1997-06-20 |
| CN1189840C (en) | 2005-02-16 |
| CN1157974A (en) | 1997-08-27 |
| CN1091284C (en) | 2002-09-18 |
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