CN1333334C - Method for implementing five-level tolerant flowing structure in integer unit of microprocessor - Google Patents

Abstract

The present invention discloses a method for implementing a five-level fault-tolerant stream line structure of an integer unit of a microprocessor. The stream line structure is composed of a command fetching component, a decoding component, an execution component, a memory access component and a register writing component and is communicated with a stream line controller and a backboard register, wherein a processing component for correcting and detecting errors is connected between the output of the decoding component and the memory access component and used for completing the error detection and the error correction of source operand and building corresponding control information. Under the control of the steam line controller and the backboard register, each command is completed through five levels of treatment. When the error correction processing component finds out a unit error, the unit error is corrected and sent into the register writing component, and the corrected data are returned into the backboard register by the register writing component. Then, a stream line is executed newly from the positions of the current error command indicated by PC and the next command indicated by nPC. When an error correcting and detecting module finds out multiple bits errors, a trap is generated directly, and the stream line stops and enters into a trap processing program.

Description

The implementation method of five-level tolerant flowing structure in the integer unit of microprocessor

Technical field

The invention belongs to field of computer technology, relate to design and the manufacturing of a kind of SPARC V8 compatible type space computer microprocessor LSFT32, particularly the implementation method of the five-level tolerant flowing structure that is adopted in the integer unit of LSFT32 microprocessor (IU).

Background technology

Since IBM Corporation in 1975 takes the lead in proposing the thought of reduced instruction set, be accompanied by the continuous development of microelectronics and computer technology, Reduced Instruction Set Computing (reduced instruction setcomputer is called for short RISC) has become the main product in current computer field.The topmost characteristics of RISC be exactly all operations carried out of microprocessor all towards register, its major advantage is:

(1) instruction has made full use of on the high-speed chip that VLSI technology brought frequency range and carries out data and transmit from the register to the operation registers, has promoted the execution speed of instruction greatly.

(2) owing to simplified the instruction control logic, thereby further dwindled the chip area of the control assembly that hardwire logic constitutes, made and to realize more register on the chip.

SPARC (Scalable Processor ARChitecture) is a kind of performance along with the improvement of technology can become than the processor architecture that improves.It has followed the design philosophy of RISC towards register manipulation fully, has defined a jumbo register file in system, and comprising can only be by the system register of system visit, and is used for the work register of operation usually.SPARC adopts the mode of " register window " that registers group is managed.System forms several windows with work register, sets up loop configuration, utilizes the overlapping register window technology to come the running of faster procedure.

Adopt the control mode of streamline to make the great majority instruction all can in the monocycle, finish in the RISC system.In the LSFT32 microprocessor, support the five-stage pipeline structure, comprise the finger stage of getting, decoding stage, execute phase, memory phase and write-back section.If can guarantee the correctness of data in the register, under the situation that relevant issues and conditional branch instruction do not occur, each beat all can have an instruction complete outflow streamline (removing multi-cycle instructions such as LODE/STORE).

At the fault-tolerant problem of register file, present processing mode mainly comprises following two kinds:

1. increase EDAC in decoding section and handle, and then data are sent into the execution section.The advantage of this mode is simple, the easily realization of control, but because EDAC has increased the time overhead of decoding section, has limited the frequency of processor, greatly reduces the risc processor performance.

2. adopt two pipeline parallel method operations, when the result is relatively more consistent, normally enters the write-back section, otherwise restart streamline, for example the S/390G5 microprocessor of IBM from the instruction that makes mistakes.This mode can detect all types of hardware and software mistakes that occur in the register, but has increased the expense of chip area greatly.Thereby this mode is only applicable in the not high microprocessor of performance requirement.

Summary of the invention

At the shortcomings and deficiencies that above-mentioned prior art exists, the object of the present invention is to provide a kind of five-level tolerant flowing structure sparc architecture microprocessor, that carry out efficient height, structural integrity that is widely used in.

The technical scheme that realizes the foregoing invention purpose is such:

The implementation method of five-level tolerant flowing structure in a kind of integer unit of microprocessor, it is characterized in that, this flowing structure is made up of instruction fetching component, decoding unit, execution unit, memory access parts and register write parts, all parts of above-mentioned flowing structure link to each other successively, and are connected with streamline control register and backboard register; Wherein also be connected with an error correction and detection processing element between the output of decoding unit and the memory access parts, be used to finish the Error Checking and Correcting of source operand, and set up corresponding control information, every instruction is finished dealing with through Pyatyi under the control of streamline control register and backboard register; Concrete processing procedure comprises the following steps:

1) instruction that obtains the current program counter indication at instruction fetching component is sent to decoding unit and is deciphered;

2) decoding unit is sent to execution unit with the source operand in the backboard register, and presets the part trap flag according to the coded format of instruction and the address of content acquisition source operand and destination operand;

3) execution unit add accordingly/subtract/take advantage of/remove arithmetical operation and with/or/the NOT logic computing, if computing is when being the multicycle, streamline enters the maintenance waiting status; From multiplier, divider arithmetic element, obtain destination operand at the memory access parts, and preset the part trap flag;

4) finish corresponding trap at the register write parts and handle, and data are write in the backboard register;

5) when decoding unit was sent to execution unit with the source operand in the backboard register, these data were sent to the error correction and detection module simultaneously and handle; Find that when the error correction and detection module unit staggers the time, then correct, and be sent to the register write parts that the data after will being corrected by the register write parts are written back in the backboard register; Afterwards, streamline begins to re-execute from next bar instruction place of current the make mistakes instruction and the programmable counter indication of programmable counter indication, makes mistakes and reloads streamline and only take 3 clock period to finishing instruction from detecting instruction; If it is the multidigit mistake that the error correction and detection module is found, in the memory access stage, not only the destination operand that will generate the execute phase is labeled as misdata, and preset trap flag, also simultaneously a follow-up instruction is removed, reduce the work of execution unit, reduce the microprocessor power consumption, streamline stops afterwards, enters trap handler.

Five-level tolerant flowing structure of the present invention has increased parallel fault-tolerant processing, promptly increases parallel error correction and detection processing element in the EX section, when the source operand with the DE section is sent to the computing of EX section, also these data is sent to the error correction and detection processing element and handles.Find that when the error correction and detection processing element unit staggers the time, then correct, and abolish the subsequent instructions of current execution command that the data of back after the WR section will be corrected are written back in the storer.Afterwards, streamline begins to re-execute from next bar instruction place of current the make mistakes instruction and the programmable counter indication of programmable counter indication, if the error correction and detection module finds it is the multidigit mistake, then directly produces trap, and streamline stops, and enters trap handler.

Five-level tolerant flowing structure of the present invention has the following advantages:

(1) the thought design fault-tolerant architecture of parallel processing is adopted in this invention, has reduced the time overhead that EDAC brought, and has improved the execution efficient of streamline greatly;

(2) single bit error is corrected in the EDAC method support adopted of this invention automatically, and can detect 2 to 8 bit-errors, has improved the error correction efficient to data in the register file;

(3) less relatively for realizing fault-tolerant error correction and detection processing (EDAC) parts and the correspondent control circuits scale that increases in this invention, the expense of having saved chip area is easy to design and realizes;

(4) mode of the related pipeline parallel method fault-tolerant processing of this invention is widely used in the microprocessor of sparc architecture, and extends in the microprocessor of other risc architecture and use, and is effectively for the fault-tolerant ability that improves streamline;

(5) the SPARC V8 compatible type space computer microprocessor LSFT32 that utilizes this invention and realized has good fault-tolerant ability, can realize the correct processing for the register file mistake.

Description of drawings

Fig. 1 is a five-level tolerant flowing line traffic control structure;

Fig. 2 is that the five-level tolerant flowing line is carried out spacetime diagram;

Fig. 3 is the pipeline state when instructing normal the execution;

Fig. 4 is the pipeline state when producing normal trap;

Pipeline state when Fig. 5 is detection/correction register file single bit error;

Fig. 6 is the pipeline state of backboard register when correctable error occurring and producing trap.

For a more clear understanding of the present invention, the present invention is described in further detail below in conjunction with accompanying drawing.

Embodiment

In SPARC V8 compatible type microprocessor LSFT32, adopt five-level tolerant flowing structure to realize the processing of instruction, the hardware circuit of its steering logic as shown in Figure 1, this flowing structure is made up of instruction fetching component, decoding unit, execution unit, memory access parts and register write parts, all parts of above-mentioned flowing structure link to each other successively, and are connected with streamline control register and backboard register; Wherein also be connected with an error correction and detection processing element between the output of decoding unit and the memory access parts, be used to finish the Error Checking and Correcting of source operand, and set up corresponding control information, every instruction is finished dealing with through Pyatyi under the control of streamline control register and backboard register; Under the situation that data are correct in register, each beat is finished the execution of an one-cycle instruction, and its time-space relationship as shown in Figure 2; Occurring under the situation of correctable error, three beats are promptly finished restarting of streamline.

The principle of work of its five-level tolerant flowing structure is: under normal circumstances, the instruction that the Pyatyi flowing structure is obtained current program counter (Pc) indication in the FE section is sent to the DE section and is deciphered; Obtain the address of source operand and destination operand according to coded format of instructing and content in the DE section, source operand in the register file is sent to EX, and preset the part trap flag, if the LODE instruction then needs the beat of grade more, could from storer, obtain data; Arithmetical operations such as adding accordingly/subtract in the EX section/take advantage of/remove and with/or/logical operation such as non-, if when computing is the multicycle, streamline enters the maintenance waiting status; From arithmetic elements such as multiplier, divider, obtain destination operand in the ME section, and preset the part trap flag; Finish corresponding trap in the WR section and handle, and data are write in the register file, if two beats of STORE instruction needs could be with in the writing data into memory unit.

Referring to Fig. 3, Fig. 3 is instruction state during normal execution the in streamline, and each beat can have an instruction (removing multi-cycle instructions such as LOAD/STORE) complete operation, the outflow streamline.After streamline started, complete through 5 beat INST1, and then the 6th, the 7th, the 8th beat finished INST2, INST3, INST4 respectively.If LOAD/STORE instruction then needs two beats just can finish, a beat is used for calculated address, another beat is used to read/write data, and this moment, streamline kept (HOLD) to wait for.

Referring to Fig. 4, Fig. 4 is the state that produces trap in streamline when instructing INST2 to carry out, and carries out in the EX section at the 4th beat INST2 to cause trap.At the 5th beat, INST1 finishes the operation of ME section and flows out streamline, and INST2 then carries out trap in the ME section and presets.At the 6th beat, in the WR section, handle the caused trap of INST2, simultaneously the subsequent instructions INST3 in the streamline, INST4, INST5 are emptied (FLUSH).At the 7th beat, streamline stops, and enters trap handler.

Referring to Fig. 5, Fig. 5 is that instruction INST2 finds the pipeline state that operand unit's mistake is corrected in the EX section.The 4th beat carries out the bug check (CHECK) of source operand when INST2 carries out in the EX section, correct the unit mistake; The 5th beat writes in the specified register in destination operand address through the source operand of revising one in the ME section, finishes the correction of data, and subsequent instructions INST3 is removed; The 6th beat, in the WR section, the data of preserving in the destination operand register are written back in the register file, the source operand that to make mistakes is updated to correct value, simultaneously the current instruction that makes mistakes of programmable counter (Pc) indication and next bar instruction (nPc) of programmable counter (Pc) indication are sent in the streamline, restarted to carry out.If what carry out before the present instruction is a jump instruction, the transfer address that then redirect produced is next bar instruction of the present instruction of programmable counter (Pc) indication, so present instruction and its next bar instruction all must be sent into streamline again, could guarantee that streamline normally advances.The 7th beat, the subsequent instructions INST3 of INST2 enters streamline.

Referring to Fig. 6, to be instruction INST2 find the mistake that can not revise and pipeline state when causing trap in the EX section to Fig. 6.The 4th beat carries out the bug check of source operand when INST2 carries out in the EX section, find to have the mistake that can not revise; The 5th beat, the destination operand that in the ME section EX section is generated is labeled as misdata, and presets trap flag, simultaneously subsequent instructions INST3 is removed; The 6th beat handled the caused trap of INST2 in the WR section, simultaneously the subsequent instructions INST3 in the streamline, INST4, INST5 are emptied (FLUSH).At the 7th beat, streamline stops, and enters trap handler.

Claims (1)

1. the implementation method of five-level tolerant flowing structure in the integer unit of a microprocessor, it is characterized in that, this flowing structure is made up of instruction fetching component, decoding unit, execution unit, memory access parts and register write parts, all parts of above-mentioned flowing structure link to each other successively, and are connected with streamline control register and backboard register; Wherein also be connected with an error correction and detection processing element between the output of decoding unit and the memory access parts, be used to finish the Error Checking and Correcting of source operand, and set up corresponding control information, every instruction is finished dealing with through Pyatyi under the control of streamline control register and backboard register; Concrete processing procedure comprises the following steps:

1) instruction that obtains the current program counter indication at instruction fetching component is sent to decoding unit and is deciphered;

2) decoding unit is sent to execution unit with the source operand in the backboard register, and presets the part trap flag according to the coded format of instruction and the address of content acquisition source operand and destination operand;

3) execution unit add accordingly/subtract/take advantage of/remove arithmetical operation and with/or/the NOT logic computing, if computing is when being the multicycle, streamline enters the maintenance waiting status; From multiplier, divider arithmetic element, obtain destination operand at the memory access parts, and preset the part trap flag;

4) finish corresponding trap at the register write parts and handle, and data are write in the backboard register;

5) when decoding unit was sent to execution unit with the source operand in the backboard register, these data were sent to the error correction and detection module simultaneously and handle; Find that when the error correction and detection module unit staggers the time, then correct, and be sent to the register write parts that the data after will being corrected by the register write parts are written back in the backboard register; Afterwards, streamline begins to re-execute from next bar instruction place of current the make mistakes instruction and the programmable counter indication of programmable counter indication, makes mistakes and reloads streamline and only take 3 clock period to finishing instruction from detecting instruction; If it is the multidigit mistake that the error correction and detection module is found, in the memory access stage, not only the destination operand that will generate the execute phase is labeled as misdata, and preset trap flag, also simultaneously a follow-up instruction is removed, reduce the work of execution unit, reduce the microprocessor power consumption, streamline stops afterwards, enters trap handler.