CN1324359C - Planar displaying device and producing method thereof - Google Patents
Planar displaying device and producing method thereof Download PDFInfo
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- CN1324359C CN1324359C CNB031382495A CN03138249A CN1324359C CN 1324359 C CN1324359 C CN 1324359C CN B031382495 A CNB031382495 A CN B031382495A CN 03138249 A CN03138249 A CN 03138249A CN 1324359 C CN1324359 C CN 1324359C
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Abstract
The present invention provides a plane display and a manufacturing method thereof, which uses four etching procedures for defining a second metal layer, a doped semiconductor layer and a semiconductor layer. A first etching procedure is that a first photoresist layer is used as a masking mould for defining the second metal layer, which is wet etching operation; the second etching procedures is that the first photoresist layer is partially changed into a second photoresist layer with channel patterns by ashing operation in the etching time, and the doped semiconductor layer and the semiconductor layer are simultaneously etched, which is oxygen containing dry etching operation; the third etching procedure is that the second photoresist layer is used as the masking mould for etching the second metal layer, which is the wet etching operation; the fourth etching procedure is that the second photoresist layer is used as the doped semiconductor layer etched by the masking mould in order to define a source pole and a drain pole. The edge of the second metal layer is inward contracted by two times of the wet etching operation, and the edge of the doped semiconductor layer is inward contracted to be same as the edge of the second metal layer after the first wet etching operation by one time of the oxygen containing dry etching operation Thus, the distance between the edge of the second metal layer and the edge of the doped semiconductor layer can be reduced.
Description
Technical field
The present invention relates to a kind of flat-panel screens (flat panel display) and manufacture method thereof, the particularly a kind of flat-panel screens and manufacture method thereof that can reduce stray capacitance.
Background technology
LCD (liquid crystal display, LCD) be a kind of flat-panel screens that is widely used most at present, have features such as low power consumption, slim light weight and low voltage drive, its displaying principle is to utilize the material behavior of liquid crystal molecule, the ordered state of liquid crystal molecule is changed, cause liquid crystal material to produce various photoelectric effect.Generally speaking, in LCD, liquid crystal layer is clipped between two transparency carriers (for example glass substrate), and wherein its top of a transparency carrier disposes driving element, for example thin film transistor (TFT) (thin film transistors, TFTs).In the viewing area of LCD, the array of pixel region (pixel area) is defined by horizontally extending sweep trace and vertically extending data line.Each pixel region has a thin film transistor (TFT) and a pixel electrode.
The method of tradition formation active array base plate is as described below.On the substrate that forms grid, after forming gate insulator, amorphous silicon layer, n+ doped silicon layer and second metal level (M2) in regular turn, define second metal level by the first photoresist layer wet etching, roughly to define the pattern of data line, can shrink back in the first photoresist layer in the edge of second metal level that has defined.Afterwards, continuing with the first photoresist layer is mask, and dry ecthing n+ doped silicon layer and amorphous silicon layer make it have the pattern of the first photoresist layer.Then, utilize ashing (Ashing) that the first photoresist layer attenuate formed the second photoresist layer, utilize the second photoresist layer to be mask, wet etching second metal level once more makes once more in the edge of second metal level and contracts.Then, continuing with the second photoresist layer is mask, and etching n+ doped silicon layer is to define source electrode and drain electrode.
In above-mentioned etch process, second metal level makes in its edge by twice wet etching process and contracts, yet the edge of the amorphous silicon layer still pattern with the first photoresist layer is identical, and its edge contracts in not.Therefore, the pixel electrode of follow-up formation still can't improve its aperture opening ratio because of contracting in the edge of second metal level, because have the problem of stray capacitance between pixel electrode and amorphous silicon layer and the n+ doped silicon layer.
Summary of the invention
In view of this, fundamental purpose of the present invention is for providing a kind of flat-panel screens that can reduce the problem of stray capacitance between pixel electrode and amorphous silicon layer and the n+ doped silicon layer.
In addition, another object of the present invention is to provide the manufacture method of the less flat-panel screens of the distance at edge of a kind of edge of second metal level and n+ doped silicon layer.
To achieve the above object, the invention provides a kind of manufacture method of flat-panel screens, its method is as described below.On the substrate that forms the gate electrode that defines by first conductive layer, form the semiconductor layer and second conductive layer of gate insulator, semiconductor layer, doping in regular turn.Afterwards, formation has the first photoresist layer of first pattern on second conductive layer, and be mask with the first photoresist layer, second conductive layer is carried out wet etching, make in the edge of patterning second conductive layer after definition for the first time and contract to the first photoresist layer, and with the edge of the first photoresist layer one first distance of being separated by.Then, semiconductor layer and semiconductor layer with oxygen containing etchant agent dry ecthing doping, this moment, the first photoresist layer also can be become the second photoresist layer with channel region pattern by the part ashing, after etching was intact, the semiconductor layer of doping was roughly identical with the second photoresist layer with the pattern of semiconductor layer.Afterwards, and be mask with the second photoresist layer, wet etching second conductive layer contracts its edge in once more, and with the edge of semiconductor layer that mixes and the semiconductor layer second distance of being separated by, in second conductive layer, define source electrode and drain electrode simultaneously.Continuation is a mask with the second photoresist layer, and the semiconductor layer that dry ecthing is mixed makes the semiconductor layer of doping comprise an one source pole and a drain electrode.
In the manufacture method of above-mentioned flat-panel screens, wherein first distance is roughly 1 micron; Second distance very arrives less than 1.5 microns roughly less than 2 microns.In addition, in the semiconductor layer that mixes with oxygen containing etchant agent dry ecthing and the step of semiconductor layer, the flow of oxygen is roughly between 100sccm and 1000sccm.
The present invention also provides a kind of flat-panel screens, wherein, comprises that first conductive layer of gate electrode is located on the glass substrate, and first insulation course is located on first conductive layer and the substrate.From bottom to top be the semiconductor layer and second conductive layer of semiconductor layer, doping in regular turn on first insulation course, wherein the semiconductor layer of Can Zaing comprises source electrode and drain electrode, and second conductive layer comprises source electrode, drain electrode and data line.Contract in the edge of this data line to the edge of the semiconductor layer of semiconductor layer and doping, and between the interval roughly less than 2 microns, preferably less than 1.5 microns.
The present invention provides a kind of flat-panel screens in addition, and wherein first conductive layer is located on the substrate, and first conductive layer comprises the one scan line.And first insulation course is located on first conductive layer and the substrate, and semiconductor layer is located on first insulation course, and the semiconductor layer of doping is located on the semiconductor layer.In addition, second conductive layer is located on the semiconductor layer of doping, and second conductive layer comprises a data line, wherein, contract in the edge of this data line to the edge of the semiconductor layer of semiconductor layer and doping, and the distance of being separated by is roughly less than 2 microns, preferably less than 1.5 microns.Moreover second insulation course is arranged on the data line and first insulation course, and pixel electrode is arranged on second insulation course, and is controlled by sweep trace and data line.
Description of drawings
For above and other objects of the present invention, feature and advantage can be become apparent, cited below particularlyly go out preferred embodiment, and conjunction with figs., be described in detail below, among the figure:
Fig. 1 is the top view of flat-panel screens of the present invention, and its II-II sectional view is shown in Fig. 2 E; And
Fig. 2 A to Fig. 2 E shows the sectional view of the manufacturing process of flat-panel screens of the present invention.
Description of reference numerals in the accompanying drawing is as follows:
100～substrate, 102～grid
102 '～gate line 104,114～insulation course
106,106a～semiconductor layer
108, the semiconductor layer of 108a, 108b～doping
110,110a, 110b～second metal level
112,112a～patterned photoresist layer
The distance at the edge of the D～edge of second metal level and the semiconductor layer of doping
110S～source electrode 110D～drain electrode
108S～source electrode 108D～drain electrode
116～opening, 118～pixel electrode
DL～data line
Distance between A～pixel electrode and the data line
Embodiment
Fig. 1 is the top view of flat-panel screens of the present invention; Fig. 2 A to Fig. 2 E represents the manufacture method flow process sectional view of a kind of flat-panel screens of the present invention, and wherein, the II-II sectional view of Fig. 1 is shown in Fig. 2 E.
Please earlier with reference to Fig. 2 A, at first provide a substrate 100, its material can be glass or quartz, and forms the first metal layer on substrate 100.Then carry out a photoengraving carving technology, the first metal layer definition is formed a grid 102 and a gate line 102 ' (as shown in Figure 1).
Then, on grid 102 and gate line 102 ', cover the semiconductor layer 108 and second metal level 110 of a layer insulating 104, semiconductor layer 106, doping in regular turn.Afterwards, on second metal level 110, form a patterned photoresist layer 112 with dual pattern.Wherein, insulation course 104 can be silicon nitride layer, silicon oxide layer or other similar this character person, and semiconductor layer 106 can be amorphous silicon layer, and the semiconductor layer 108 of doping can be the amorphous silicon layer of Doped n-type adulterant.
Then please refer to Fig. 2 B, is mask with patterned photoresist layer 112, and second metal level 110 is carried out wet etching, has the second metal level 110a of first pattern with formation.Wherein the edge of the second metal level 110a retreats in the patterned photoresist layer 112, and the distance at the edge of itself and patterned photoresist layer 112 is denoted as W, and is approximately about 1 micron (μ m).
Continuation is a mask with patterned photoresist layer 112, and semiconductor layer 106 and the semiconductor layer 108 that mixes are carried out dry ecthing, and employed dry ecthing is formed and contained aerobic (O
2), and with O
2Flow control about 100～1000sccm.Owing in this dry etching process, add O
2So patterned photoresist layer 112 can carry out cineration technics simultaneously in etching, and size is reduced.Anticipate promptly, this patterned photoresist layer 112 is a dynamic mask layer in this dry etching process.Behind etch process thus, patterned photoresist layer 112 can dwindle into the patterned photoresist layer 112a with channel region pattern as shown in the figure, and formation has the semiconductor layer 106a of first pattern and the semiconductor layer 108a of doping, its edge is defined by patterned photoresist layer 112a, meaning is that 108a is also littler than 110a with the distance of photoresist with 106a, and the distance of 108a and the 106a and the second metal level 110a is d
1, shown in Fig. 2 C.
Then please refer to Fig. 2 D, the second metal level 110a is carried out wet etching, its edge is contracted toward in again, the distance at the edge of the semiconductor layer 108a of itself and semiconductor layer 106a and doping increases to D by previous d1, and D is less than about 2 microns, even less than 1.5 microns.In addition, and in this wet etch step, further define the second metal level 110b with source electrode 110S and drain electrode 110D.
Then, be mask with patterned photoresist layer 112a with second pattern, the semiconductor layer 108a that dry ecthing is mixed is further to define the semiconductor layer 108b of the doping with source electrode 108S and drain electrode 108D.
Then please refer to Fig. 2 E, this figure is the II-II tangential profile figure of Fig. 1.After removing patterned photoresist layer 112a, cover a layer insulating 114 on the whole substrate that has formed thin film transistor (TFT), and in insulation course 114, form the surface that opening 116 exposes drain electrode 110D.On insulation course 114, form the pixel electrode 118 that electrically contacts with drain electrode 110D afterwards.Wherein, the material of insulation course 114 can be organic material, monox, silicon nitride or other similar this character person.
Fig. 1 is the top view corresponding to Fig. 2 E, because the distance D at the edge of the semiconductor layer 108b that mixes and the edge of the second metal level 110b is contracted to below 2 microns, can reduce the stray capacitance between the semiconductor layer 108a of pixel electrode 118 and semiconductor layer, doping.Therefore, the distance A between pixel electrode 118 and the data line DL can shorten again, uses the raising aperture opening ratio.
In sum, semiconductor layer and semiconductor layer that the present invention defines second metal level (M2), mixes by four road etching work procedures are to form source electrode, drain electrode and data line.First road is a wet etching, and by being mask with the first photoresist layer 112, wet etching defines second metal level.Second road is oxygen containing dry ecthing, carry out the cineration technics of the first photoresist layer 112 by the composition that contains aerobic, make the size of the first photoresist layer 112 dwindle into the second photoresist layer 112a with channel region pattern, and the semiconductor layer and the semiconductor layer of etching doping.The 3rd road is a wet etching, and by being mask with the second photoresist layer 112a, wet etching second metal level except the edge that makes second metal level contracts toward in again, and defines source electrode and drain electrode once more.The 4th road is dry ecthing, and by being mask with the second photoresist layer 112a, the semiconductor layer that etching is mixed is so that the semiconductor layer that mixes defines source electrode and drain electrode.The second above-mentioned metal level makes in its edge by twice wet etching process and contracts, the semiconductor layer that mixes then by once contain the oxygen dry etching process make its edge contract toward in to first time wet etching after the edge of second metal level close.Therefore, can dwindle the distance D at the edge of the edge of semiconductor layer 108b of doping and the second metal level 110b.
Though the present invention with preferred embodiment openly as above; but it is not in order to limit the present invention; those skilled in the art are under the situation that does not break away from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when with appended being as the criterion that claim was defined.
Claims (11)
1. flat-panel screens comprises:
One substrate;
One first conductive layer is located on this substrate, and this first conductive layer comprises a gate electrode;
One first insulation course is located on this first conductive layer and this substrate;
Semi-conductor layer is located on this first insulation course;
One semiconductor layer that mixes is located on this semiconductor layer, and wherein the semiconductor layer of this doping comprises an one source pole and a drain electrode; And
One second conductive layer is located on the semiconductor layer of this doping, and wherein this second conductive layer comprises one source pole electrode, a drain electrode and a data line,
Wherein, contract in the edge of this data line to the edge of the semiconductor layer of this semiconductor layer and this doping, and the distance of being separated by, this distance is less than 2 microns.
2. flat-panel screens as claimed in claim 1, wherein this distance is less than 1.5 microns.
3. flat-panel screens as claimed in claim 1 also comprises:
One second insulation course is arranged on this source electrode, drain electrode and this first insulation course; And
One pixel electrode is arranged on this second insulation course, and this pixel electrode is electrically connected with this drain electrode.
4. flat-panel screens comprises:
One substrate;
One first conductive layer is located on this substrate, and this first conductive layer comprises the one scan line;
One first insulation course is located on this first conductive layer and this substrate;
Semi-conductor layer is located on this first insulation course;
One semiconductor layer that mixes is located on this semiconductor layer;
One second conductive layer is located on the semiconductor layer of this doping, and this second conductive layer comprises a data line, wherein, contract in the edge of this data line to the edge of the semiconductor layer of this semiconductor layer and this doping, and the distance of being separated by, this distance is less than 2 microns;
One second insulation course is arranged on this data line and this first insulation course; And
One pixel electrode is arranged on this second insulation course, and is controlled by this sweep trace and this data line.
5. flat-panel screens as claimed in claim 4, wherein this distance is less than 1.5 microns.
6. the manufacture method of a flat-panel screens as claimed in claim 1 comprises:
One substrate is provided;
Form one first conductive layer on this substrate, this first conductive layer comprises a gate electrode;
Cover one first insulation course on this first conductive layer and this substrate;
Cover semi-conductor layer on this first insulation course;
Cover a semiconductor layer that mixes on this semiconductor layer;
Cover one second conductive layer on the semiconductor layer of this doping;
Formation has one first photoresist layer of one first pattern on this second conductive layer;
With this first photoresist layer is mask, this second conductive layer is carried out wet etching, make in the edge of this patterning second conductive layer after definition for the first time and contract to this first photoresist layer, and with the edge of this first photoresist layer one first distance of being separated by;
Use the oxygen containing etchant agent, semiconductor layer and this semiconductor layer that dry ecthing should be mixed, this first photoresist layer of part ashing becomes one second photoresist layer simultaneously, makes the pattern of the semiconductor layer of this doping and this semiconductor layer close with this second conductive layer;
With this second photoresist layer is mask, this patterning second conductive layer of wet etching, its edge is contracted in once more, and with the edge of the semiconductor layer of this doping and this semiconductor layer second distance of being separated by, and make this second conductive layer comprise an one source pole electrode and a drain electrode; And
With this second photoresist layer is mask, and the semiconductor layer that dry ecthing should be mixed makes the semiconductor layer of this doping comprise an one source pole and a drain electrode.
7. the manufacture method of flat-panel screens as claimed in claim 6, wherein this first distance is 1 micron.
8. the manufacture method of flat-panel screens as claimed in claim 6, wherein this second distance is less than 2 microns.
9. the manufacture method of flat-panel screens as claimed in claim 6, wherein this second distance is less than 1.5 microns.
10. the manufacture method of flat-panel screens as claimed in claim 6, wherein in the step of the semiconductor layer that should mix with oxygen containing etchant agent dry ecthing and this semiconductor layer, the flow of oxygen is between 100sccm and 1000sccm.
11. the manufacture method of flat-panel screens as claimed in claim 6 also comprises:
Cover one second insulation course on this source electrode, drain electrode and this first insulation course;
In this second insulation course, form the surface that an opening exposes this drain electrode; And
On this second insulation course, form a pixel electrode, and this pixel electrode is electrically connected with this drain electrode via this opening.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031382495A CN1324359C (en) | 2003-05-28 | 2003-05-28 | Planar displaying device and producing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031382495A CN1324359C (en) | 2003-05-28 | 2003-05-28 | Planar displaying device and producing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1553267A CN1553267A (en) | 2004-12-08 |
| CN1324359C true CN1324359C (en) | 2007-07-04 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031382495A Expired - Lifetime CN1324359C (en) | 2003-05-28 | 2003-05-28 | Planar displaying device and producing method thereof |
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| CN (1) | CN1324359C (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100449715C (en) * | 2006-01-23 | 2009-01-07 | 友达光电股份有限公司 | Thin film transistor and manufacturing method thereof |
| CN100456139C (en) * | 2006-04-20 | 2009-01-28 | 友达光电股份有限公司 | Method of mfg. lower substrate of LCD device by using three masks |
| CN102455591A (en) * | 2010-10-14 | 2012-05-16 | 京东方科技集团股份有限公司 | Manufacturing method for thin film pattern and array substrate |
| CN108198751B (en) * | 2017-12-27 | 2020-08-04 | 深圳市华星光电技术有限公司 | Method for stripping photoresist layer |
| CN117377903A (en) * | 2021-11-30 | 2024-01-09 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method thereof and display device |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03116737A (en) * | 1989-09-28 | 1991-05-17 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| US5153754A (en) * | 1989-06-30 | 1992-10-06 | General Electric Company | Multi-layer address lines for amorphous silicon liquid crystal display devices |
| JPH05275695A (en) * | 1991-12-24 | 1993-10-22 | Osaka Gas Co Ltd | Thin film transistor and manufacture thereof |
| US5872370A (en) * | 1995-08-28 | 1999-02-16 | Ois Optical Imaging Systems, Inc. | TFT with reduced channel length and parasitic capacitance |
| CN1254948A (en) * | 1998-11-19 | 2000-05-31 | 三星电子株式会社 | Thin-film transistor array panel and its making method |
| CN1267837A (en) * | 1999-03-16 | 2000-09-27 | 松下电器产业株式会社 | Producing process for active element array substrate |
| US6323917B1 (en) * | 1998-05-28 | 2001-11-27 | Fujitsu Limited | Thin film transistor for a liquid crystal display device and a fabrication process thereof |
| US6337284B1 (en) * | 1999-05-27 | 2002-01-08 | Lg. Philips Lcd Co., Ltd. | Liquid crystal display device and method of manufacturing the same |
-
2003
- 2003-05-28 CN CNB031382495A patent/CN1324359C/en not_active Expired - Lifetime
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5153754A (en) * | 1989-06-30 | 1992-10-06 | General Electric Company | Multi-layer address lines for amorphous silicon liquid crystal display devices |
| JPH03116737A (en) * | 1989-09-28 | 1991-05-17 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH05275695A (en) * | 1991-12-24 | 1993-10-22 | Osaka Gas Co Ltd | Thin film transistor and manufacture thereof |
| US5872370A (en) * | 1995-08-28 | 1999-02-16 | Ois Optical Imaging Systems, Inc. | TFT with reduced channel length and parasitic capacitance |
| US6323917B1 (en) * | 1998-05-28 | 2001-11-27 | Fujitsu Limited | Thin film transistor for a liquid crystal display device and a fabrication process thereof |
| CN1254948A (en) * | 1998-11-19 | 2000-05-31 | 三星电子株式会社 | Thin-film transistor array panel and its making method |
| CN1267837A (en) * | 1999-03-16 | 2000-09-27 | 松下电器产业株式会社 | Producing process for active element array substrate |
| US6337284B1 (en) * | 1999-05-27 | 2002-01-08 | Lg. Philips Lcd Co., Ltd. | Liquid crystal display device and method of manufacturing the same |
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| CN1553267A (en) | 2004-12-08 |
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