CN1321444C - 布线图形埋入检查方法、半导体器件制造方法及检查装置 - Google Patents
布线图形埋入检查方法、半导体器件制造方法及检查装置 Download PDFInfo
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- CN1321444C CN1321444C CNB2004100006108A CN200410000610A CN1321444C CN 1321444 C CN1321444 C CN 1321444C CN B2004100006108 A CNB2004100006108 A CN B2004100006108A CN 200410000610 A CN200410000610 A CN 200410000610A CN 1321444 C CN1321444 C CN 1321444C
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Measurement Of Length, Angles, Or The Like Using Electric Or Magnetic Means (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (15)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP005883/2003 | 2003-01-14 | ||
JP2003005883A JP3961427B2 (ja) | 2003-01-14 | 2003-01-14 | 配線パターンの埋め込み検査方法、半導体装置の製造方法および検査装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1518087A CN1518087A (zh) | 2004-08-04 |
CN1321444C true CN1321444C (zh) | 2007-06-13 |
Family
ID=32896432
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2004100006108A Expired - Fee Related CN1321444C (zh) | 2003-01-14 | 2004-01-13 | 布线图形埋入检查方法、半导体器件制造方法及检查装置 |
Country Status (3)
Country | Link |
---|---|
US (2) | US7047154B2 (zh) |
JP (1) | JP3961427B2 (zh) |
CN (1) | CN1321444C (zh) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3961427B2 (ja) * | 2003-01-14 | 2007-08-22 | 株式会社東芝 | 配線パターンの埋め込み検査方法、半導体装置の製造方法および検査装置 |
US7034563B1 (en) * | 2005-01-26 | 2006-04-25 | Ahbee 2, L.P., A California Limited Partnership | Apparatus for measuring of thin dielectric layer properties on semiconductor wafers with contact self aligning electrodes |
JP5424675B2 (ja) * | 2008-03-18 | 2014-02-26 | キヤノン株式会社 | 半導体装置の製造方法及び半導体装置 |
JP2010149146A (ja) * | 2008-12-25 | 2010-07-08 | Hitachi High-Technologies Corp | レーザ加工装置 |
US8080463B2 (en) * | 2009-01-23 | 2011-12-20 | Kabushiki Kaisha Toshiba | Semiconductor device manufacturing method and silicon oxide film forming method |
KR101253916B1 (ko) * | 2009-02-03 | 2013-04-16 | 큐셉트 테크놀로지스 인크. | 비 진동 접촉 전위차 센서를 이용한 패터닝된 웨이퍼 검사 시스템 |
JP2013036941A (ja) * | 2011-08-10 | 2013-02-21 | Yamaha Corp | 磁気センサの検査装置及び検査方法 |
CN103346117B (zh) * | 2013-06-13 | 2015-10-14 | 华进半导体封装先导技术研发中心有限公司 | 基于涡流技术的tsv晶圆背面减薄控制方法及*** |
US10061415B2 (en) * | 2016-06-30 | 2018-08-28 | Synaptics Incorporated | Input device receiver with delta-sigma modulator |
CN109975398B (zh) * | 2017-12-27 | 2022-10-21 | 核动力运行研究所 | 一种传热管涡流检测探头磁通量线圈布线检测方法 |
JP7220625B2 (ja) * | 2019-06-05 | 2023-02-10 | 東京エレクトロン株式会社 | 基板検査方法、基板検査システム及び制御装置 |
CN112908225B (zh) * | 2021-01-22 | 2022-08-16 | 合肥维信诺科技有限公司 | 显示面板的检测方法 |
EP4053495B1 (en) * | 2021-03-03 | 2024-07-17 | ABB Schweiz AG | Tilt and curvature measurements of metal sheets in a rolling mill |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1183640A (zh) * | 1996-11-21 | 1998-06-03 | 日本电气株式会社 | 半导体器件及其测试方法 |
CN1202002A (zh) * | 1997-06-06 | 1998-12-16 | 日本电气株式会社 | 半导体器件的检测图形及方法 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2559512B2 (ja) | 1990-01-17 | 1996-12-04 | 富士通株式会社 | 金属膜の膜厚測定方法 |
US5416411A (en) * | 1993-01-08 | 1995-05-16 | Lockheed Fort Worth Company | System and method for measuring the thickness of a ferromagnetic layer |
JP2570130B2 (ja) | 1993-09-02 | 1997-01-08 | 日本電気株式会社 | 膜厚測定用パターンおよび膜厚測定方法 |
JP2967755B2 (ja) * | 1997-04-17 | 1999-10-25 | 日本電気株式会社 | 半導体装置の製造方法 |
JP2001156138A (ja) | 1999-11-25 | 2001-06-08 | Nec Corp | 埋め込み成膜のモニタパターンおよび埋め込み成膜のモニタ方法 |
JP4015352B2 (ja) | 2000-02-22 | 2007-11-28 | 株式会社日立製作所 | 荷電粒子ビームを用いた検査方法 |
JP4874465B2 (ja) | 2000-03-28 | 2012-02-15 | 株式会社東芝 | 渦電流損失測定センサ |
US6649516B2 (en) * | 2001-06-05 | 2003-11-18 | Kabushiki Kaisha Toshiba | Method for manufacturing a composite member from a porous substrate by selectively infiltrating conductive material into the substrate to form via and wiring regions |
US6906423B1 (en) * | 2001-06-05 | 2005-06-14 | Kabushiki Kaisha Toshiba | Mask used for exposing a porous substrate |
US6651325B2 (en) * | 2002-02-19 | 2003-11-25 | Industrial Technologies Research Institute | Method for forming cantilever beam probe card and probe card formed |
IL153894A (en) * | 2003-01-12 | 2010-05-31 | Nova Measuring Instr Ltd | Method and system for measuring the thickness of thin conductive layers |
JP3961427B2 (ja) * | 2003-01-14 | 2007-08-22 | 株式会社東芝 | 配線パターンの埋め込み検査方法、半導体装置の製造方法および検査装置 |
-
2003
- 2003-01-14 JP JP2003005883A patent/JP3961427B2/ja not_active Expired - Fee Related
-
2004
- 2004-01-12 US US10/754,609 patent/US7047154B2/en not_active Expired - Lifetime
- 2004-01-13 CN CNB2004100006108A patent/CN1321444C/zh not_active Expired - Fee Related
-
2006
- 2006-03-24 US US11/387,822 patent/US7640138B2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1183640A (zh) * | 1996-11-21 | 1998-06-03 | 日本电气株式会社 | 半导体器件及其测试方法 |
CN1202002A (zh) * | 1997-06-06 | 1998-12-16 | 日本电气株式会社 | 半导体器件的检测图形及方法 |
Also Published As
Publication number | Publication date |
---|---|
US20040196031A1 (en) | 2004-10-07 |
JP2004221249A (ja) | 2004-08-05 |
US7047154B2 (en) | 2006-05-16 |
JP3961427B2 (ja) | 2007-08-22 |
US20060167650A1 (en) | 2006-07-27 |
CN1518087A (zh) | 2004-08-04 |
US7640138B2 (en) | 2009-12-29 |
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Effective date of registration: 20170807 Address after: Tokyo, Japan Patentee after: TOSHIBA MEMORY Corp. Address before: Tokyo, Japan Patentee before: Toshiba Corp. |
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Address after: Tokyo, Japan Patentee after: TOSHIBA MEMORY Corp. Address before: Tokyo, Japan Patentee before: Japanese businessman Panjaya Co.,Ltd. Address after: Tokyo, Japan Patentee after: Kaixia Co.,Ltd. Address before: Tokyo, Japan Patentee before: TOSHIBA MEMORY Corp. |
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Effective date of registration: 20211229 Address after: Tokyo, Japan Patentee after: Japanese businessman Panjaya Co.,Ltd. Address before: Tokyo, Japan Patentee before: TOSHIBA MEMORY Corp. |
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