CN1320814C - Solid-state imaging device, digital camera, and digital video camera - Google Patents

Abstract

A solid photographing apparatus is provided. After releasing signals of the photodiode in each cell, the photodiode accumulates the signals. After the accumulation, each signal is read from the photodiode. On the semiconductor substrate, each cell includes a photodiode, a reading gate for reading signals from the photodiodes, and a detection section for detecting the signals have been read out. The reading gate reads signals in the photo-diode. The detecting section detects the read-out signals. The solid photographing apparatus has a circuit, which applies a first pulse signal used for releasing signals from the photo-diode on one horizontal line, to the corresponding cells, during a first horizontal line scanning period for several horizontal lines, and which applies a second pulse signal used for releasing signals from the photo-diode on one horizontal line, to the corresponding cells, during a second horizontal line scanning period for several horizontal lines.

Description

Solid camera head, digital camera and digital camera

Invention field

The present invention relates to solid camera head, digital camera and digital camera.

Background technology

Figure 23 is the figure of circuit structure of the cmos image sensor of the existing example of expression.This imageing sensor is controlled by control part (CPU or DSP) C.The camera watch region of this imageing sensor be 1 unit (pixel portions) by 4 transistors (Ta, Tb, Tc, Td) and photodiode (PD) constitute this unit two-dimensional arrangement.The bottom of camera watch region is the load transistor TL that uses of source of configuration output circuit in the horizontal direction.In addition, the configuration of the top of camera watch region comprises the column type AD translation circuit 2 of the 10bit of de-noising circuit.

Signal from each unit 1 is input to AD translation circuit 2, presses 10bit and line output by horizontal shifting register 3 orders as the signal of horizontal direction after the AD conversion.In the AD translation circuit 2, the level according to the triangular wave (RAMP) of circuit 4 takes place from RAMP uses comparator, is the digital signal of 10bit 0～1023 grade (level) with the signal transformation of each unit.

In addition, for making unit 1, AD translation circuit 2, RAMP that circuit 4, horizontal shifting register 3, vertical transfer register (ES) 5, vertical transfer register (RO) 6, pulse selector 72 actions, configuration timing generating circuit 8 and bias generation circuit 9 take place.Connect control part C on the timing generating circuit 8.

In each unit 1, discharge the middle signal of storing of horizontal each photodiode (PD) that vertical transfer register (ES) 5 is selected.Set by the EDATA from the C of external control portion input the memory time of each unit 1, the horizontal line number between the horizontal line that horizontal line that corresponding vertical transfer register (RO) 6 is selected and vertical transfer register (ES) 5 are selected.Vertical transfer register (ES) 5 selected horizontal line before vertical transfer register (RO) 6 is selected.The horizontal line that the relative vertical transfer register of horizontal line (RO) 6 that vertical transfer register (ES) 5 is selected is selected leaves certain line number.Therefore, control each photodiode (PD) canned data amount.After memory time, in each unit 1, read the signal of the horizontal photodiode (PD) of vertical transfer register (RO) 6 selections.

Timing generating circuit 8 is read before the signal of photodiode (PD) storage, for amplifying gate voltage with transistor T b, the voltage that is test section (DN) is set at reference voltage (reset level), connect (ON) Φ RESET pulse, test section (DN) is set at reset level through pulse selector 72.At this moment, to vertical signal line (VLIN) output reset level, the capacitor stores reset level of the de-noising in AD translation circuit 2.

Then, timing generating circuit 8 will be read transistor T d through pulse selector 72 and connect (ON) by connecting (ON) Φ READ pulse, read the signal charge of storage in the photodiode (PD) in test section (DN).Then, timing generating circuit 8 be during 1 horizontal effective scanning in during vertical effective scanning in 1 horizontal line of selection, by with Φ ADRES pulse-on (ON), connect (ON) corresponding row selecting transistor Ta through pulse selector 72, make the source follower circuit action that constitutes with transistor T L with transistor T b and load by amplifying again.Thus, read " signal level+reset level " in vertical signal line, AD translation circuit 2 is removed reset level from " signal level+reset level " in de-noising action, AD figure signal only, 10bit output.

Action is during this imageing sensor under the 30HzVGA mode, from control part to the Φ CK pulse of the Φ HP pulse of the Φ VR pulse of timing generating circuit 8 input 30Hz, 15.7H, 24MHz and memory time control data ESDATA.Timing generating circuit 8 usefulness buffer circuits are the Φ VR pulse and the Φ HP pulse of shaping input again, outputs to vertical transfer register (RO) 6 as Φ VRI pulse and Φ HPI pulse.Vertical transfer register (RO) 6 is removed register output and is made as the LO level during the LO of Φ VRI pulse.Vertical transfer register (RO) 6 is pressed the action of Φ HPI pulse sequence, selects (HI) horizontal line.

Figure 24 is the circuit diagram of pulse selector 72.When pulse selector 72 is HI at the output ROn from vertical transfer register (RO) 6, Φ READ, Φ ADRES, Φ RESET are exported as Φ READn, Φ ADRESn, Φ RESETn respectively.When selecting ROn+1 by vertical transfer register (RO) 6 in during the horizontal effective scanning then, export Φ READn+1, Φ ADRESn+1, Φ RESETn+1 equally.

In addition, when pulse selector 72 is HI at the output ESn from vertical transfer register (ES) 5, Φ READn, Φ RESETn are exported.When selecting ESn+1 by vertical transfer register (ES) 5 in during the horizontal effective scanning then, export Φ READn+1, Φ RESETn+1 equally.

Figure 25 is the figure of the action of the above-mentioned cmos image sensor of expression.At first, each photodiode (PD) is pressed the order cooperation number of scanning lines 525 discharge signals (PD discharge) of horizontal line No.1～480.Then, before next frame, read the signal (PD reads) of each photodiode (PD) storage by the order cooperation number of scanning lines 525 of horizontal line No.1～480.The signal of reading from each photodiode (PD) outputs to vertical signal line, by 2 conversion of AD translation circuit, exports DATA (0:9) as the numeral output of 10bit from imageing sensor by per 1 horizontal line.

Among Figure 25, represent the variation of the memory time of photodiodes by memory time 1,2,3.As can be seen from Figure 25, in arbitrary memory time 1,2,3, each of the successive offset of horizontal line No.1～480 memory time.Therefore, during subject that photography is moved on the horizontal direction, dynamically produce by the order of horizontal line No.1～480 and to depart from.For example, when from the car that moves, photographing upright post, there is pillar to be in the improper situation of the state of oblique inclination.When especially photography has the physical culture scene etc. of action, because the oblique tendency of subject, the problem that the simultaneity of animation worsens appears.

In addition, open the spy and disclose the solid-state image sensor that can carry out electronic shutter action in the 2001-111900 communique.In addition, the spy opens the method that discloses in amplifying-type solid-state imaging device the image of realizing satisfying simultaneity in the 2000-023044 communique.

Brief summary of the invention

The solid-state image sensor of a form of the present invention is following solid-state image sensor: from two-dimensional arrangement on semiconductor substrate photodiode, after being used for discharging signal from the above-mentioned photodiode of each unit of reading grid and being used to detect the test section of the signal of reading of this photodiode read output signal, with above-mentioned each photodiode storage signal, after its memory time, from above-mentioned each photodiode read output signal, comprise following circuit: first pulse signal that a plurality of horizontal lines ground carries out being used to discharge the signal of 1 horizontal above-mentioned each photodiode in the 1st horizontal scan period is applied to the action of corresponding above-mentioned each unit, and second pulse signal that a plurality of horizontal lines ground will be used to read the signal of 1 horizontal above-mentioned each photodiode with carrying out simultaneously in the 2nd horizontal scan period is applied to the action of above-mentioned each unit of correspondence simultaneously.

The solid-state image sensor of another form of the present invention is following solid-state image sensor: from two-dimensional arrangement on semiconductor substrate photodiode, after being used for discharging signal from the above-mentioned photodiode of each unit of reading grid and being used to detect the test section of the signal of reading of this photodiode read output signal, with above-mentioned each photodiode storage signal, after its memory time, at above-mentioned test section behind above-mentioned each photodiode read output signal, from above-mentioned test section output signal, comprise following circuit: first pulse signal that a plurality of horizontal scanning lines carry out being used to discharge the signal of 1 horizontal above-mentioned each photodiode in the 1st horizontal scan period is applied to the action of corresponding above-mentioned each unit, and second pulse signal that a plurality of horizontal lines ground carries out being used to read the signal of 1 horizontal above-mentioned each photodiode in the 2nd horizontal scan period is applied to the action of above-mentioned each unit of correspondence simultaneously, and the action that the 3rd pulse signal that each of each horizontal scan period carries out being used to export the signal of 1 horizontal above-mentioned test section is applied to corresponding above-mentioned each unit.

The digital camera of another form of the present invention uses above-mentioned solid camera head.

The digital camera of a form more of the present invention uses above-mentioned solid camera head.

Description of drawings

Fig. 1 is the block diagram of structure of the digital camera of the expression solid camera head that is suitable for first embodiment;

Fig. 2 is the figure of circuit structure of the cmos image sensor of expression first embodiment;

Fig. 3 is the circuit diagram of the pulse selector of first embodiment;

Fig. 4 is the action timing diagram of the pixel portions of first embodiment " MODE1 ";

Fig. 5 is the action timing diagram of the pixel portions of first embodiment " MODE2 ";

Fig. 6 is first timing diagram of action of the cmos image sensor of expression first embodiment;

Fig. 7 A～7E is the sectional view and the electromotive force action diagram of pixel of memory time 2 of action of the cmos image sensor of expression first embodiment;

Fig. 8 is the setting flow chart in proper order of expression first embodiment " MODE1 " and " MODE2 ";

Fig. 9 is second timing diagram of action of the cmos image sensor of expression first embodiment;

Figure 10 is the figure of circuit structure of the countermeasure of expression first embodiment;

Figure 11 is the block diagram of structure of the digital camera of the expression solid camera head that is suitable for first embodiment;

Figure 12 is the figure of circuit structure of the cmos image sensor of expression second embodiment;

Figure 13 is the circuit diagram of the pulse selector of second embodiment;

Figure 14 is the action timing diagram of the pixel portions of second embodiment " MODE1 ";

Figure 15 is vertical transfer register (ES), (RO) of second embodiment, the timing diagram of (ADR);

Figure 16 is the action timing diagram of the pixel portions of second embodiment " MODE1 ";

Figure 17 is the vertical transfer register (ES) of second embodiment, the timing diagram of (RO);

Figure 18 is the timing diagram of action of the cmos image sensor of expression second embodiment;

Figure 19 is the setting flow chart in proper order of expression second embodiment " MODE1 " and " MODE2 ";

The timing diagram of KTC noise countermeasure when Figure 20 is the low-light (level) of expression second embodiment;

Figure 21 is the figure of circuit structure of cmos image sensor of 330,000 pixels that form on semiconductor substrate of expression the 3rd embodiment;

Figure 22 is the timing diagram of action of the cmos image sensor of expression the 3rd embodiment;

Figure 23 is the figure of circuit structure of the cmos image sensor of the original example of expression;

Figure 24 is the circuit diagram of the pulse selector of original example;

Figure 25 is the timing diagram of action of the cmos image sensor of the original example of expression.

Embodiment

Below with reference to description of drawings embodiment.

Fig. 1 is the block diagram of structure of the digital camera of the expression solid camera head that is suitable for first embodiment.Digital camera 100 comprises microcomputer 101, connects picture signal handling part 102, DV transformation component 103 and the DV band portion 104 of regularly taking place on microcomputer 101.Connect DV on the DV transformation component 103 and be with 104 and LCD monitor 105.In addition, configuration this solid camera head (transducer) S on the optical axis of lens 106, solid camera head S go up to connect picture signal handling part 102 regularly take place.In addition, microphone 107 connects DV transformation component 103 through sound signal processing 108.In addition, comprise power supply unit 109 on the digital camera 100.

Picture signal handling part 102, DV transformation component 103 and DV band portion 104 regularly take place in microcomputer 101 controls.Transducer S outputs to timing with this picture signal picture signal handling part 102 takes place according to the picture of the signal picked-up that comes self-timing generation picture signal handling part 102 through lens 106 incidents.In addition, microphone 107 sound imports output to sound signal processing portion 108 with its voice signal.The picture signal of picture signal handling part 102 processing and the voice signal of voice signal handling part 108 processing regularly taking place output to DV transformation component 103, carries out the DV conversion.When the picture signal that DV transformation component 103 carries out the DV conversion is delivered to DV band portion 104 records, be transformed to analog signal and output to LCD monitor 105.Under the reproduction mode, the signal of DV band portion 104 records is transformed to analog signal and is outputed to LCD monitor 105 by the DV transformation component.

Fig. 2 is the figure of circuit structure of cmos image sensor (solid camera head) S of 330,000 pixels that form on semiconductor substrate of the expression first embodiment of the present invention.Among Fig. 2, the part identical with Figure 23 adds same-sign.This imageing sensor is controlled by control part (CPU or DSP) C.The camera watch region of this imageing sensor be 1 unit by 4 transistors (Ta, Tb, Tc, Td) and photodiode (PD) constitute this unit two-dimensional arrangement.The bottom of camera watch region is the load transistor TL that uses of source of configuration output circuit in the horizontal direction.In addition, the column type AD translation circuit 2 of the 10bit that comprises de-noising circuit is arranged at the top of camera watch region.

Signal from each unit 1 is input to AD translation circuit 2, presses 10bit and line output by horizontal shifting register 3 orders as the signal of horizontal direction after the AD conversion.In the AD translation circuit 2, the level according to the triangular wave (RAMP) of circuit 4 takes place from RAMP uses comparator, is the digital signal of 10bit 0～1023 grade (level) with the signal transformation of each unit 1.

In addition, for making each unit 1, AD translation circuit 2, RAMP that circuit 4, horizontal shifting register 3, vertical transfer register (ES) 5, vertical transfer register (RO) 6, pulse selector 7 actions, configuration timing generating circuit 8 and bias generation circuit 9 take place.Connect above-mentioned control part C on the timing generating circuit 8.

In each unit 1, discharge the middle signal of storing of horizontal each photodiode (PD) that vertical transfer register (ES) 5 is selected.Set by the EDATA from control part C input the memory time of each unit 1, the horizontal line number between the horizontal line that horizontal line that corresponding vertical transfer register (RO) 6 is selected and vertical transfer register (ES) 5 are selected.Vertical transfer register (ES) 5 selected horizontal line before vertical transfer register (RO) 6 is selected.The horizontal line that the relative vertical transfer register of horizontal line (RO) 6 that vertical transfer register (ES) 5 is selected is selected leaves certain line number.Therefore, control the semaphore of each photodiode (PD) storage.After memory time, in each unit 1, read the signal of the horizontal photodiode (PD) of vertical transfer register (RO) 6 selections.

Timing generating circuit 8 is read before the signal of photodiode (PD) storage, for amplifying gate voltage with transistor T b, the voltage that is test section (DN) is set at reference voltage (reset level), connect (ON) Φ RESET pulse, test section (DN) is set at reset level through pulse selector 7.At this moment, to vertical signal line (VLIN) output reset level, the capacitor stores reset level of the de-noising in AD translation circuit 2.

Then, timing generating circuit 8 will be read transistor T d through pulse selector 7 and connect (ON) by connecting (ON) Φ READ pulse, read the signal charge of storage in the photodiode (PD) in test section (DN).Then, timing generating circuit 8 be during 1 horizontal flyback sweep in during vertical effective scanning in 1 horizontal line of selection, by with Φ ADRES pulse-on (ON), connect (ON) corresponding row selecting transistor Ta through pulse selector 7, make the source follower circuit action that constitutes with transistor T L with transistor T b and load by amplifying again.Thus, go up at vertical signal line (VLIN) and to read " signal level+reset level " from test section (DN), AD translation circuit 2 is removed reset level from " signal level+reset level " in the de-noising action, AD figure signal only, 10bit output.

Action is during this imageing sensor under the 30HzVGA mode, from control part C to the Φ CK pulse of the Φ HP pulse of the Φ VR pulse of timing generating circuit 8 input 30Hz, 15.7Hz, 24MHz and memory time control data ESDATA.Timing generating circuit 8 usefulness buffer circuits are the Φ VR pulse and the Φ HP pulse of shaping input again, outputs to vertical transfer register (RO) 6 as Φ VRI pulse and Φ HPI pulse.Vertical transfer register (RO) 6 is removed register output and is made as the LO level during the LO of Φ VRI pulse.Vertical transfer register (RO) 6 is pressed the action of Φ HPI pulse sequence, selects (HI) horizontal line.

Among this first embodiment,, switch synchronously, the RAMP waveform is switched to positive waveform and negative wave with the action of " MODE1 " and " MODE2 " of imageing sensor for the improvement of the simultaneity of animation and the improvement of image quality.

Fig. 3 is the circuit diagram of pulse selector 7.When pulse selector 7 is HI at the output ROn from vertical transfer register (RO) 6, Φ ADRES, Φ RESET are exported as Φ ADRESn, Φ RESETn respectively.When selecting ROn+1 by vertical transfer register (RO) 6 in during the horizontal effective scanning then, export Φ ADRESn+1, Φ RESETn+1 equally.

In addition, when pulse selector 7 is HI in the Φ VREAD pulse from timing generating circuit 8 inputs, during vertical effective scanning, select whole horizontal lines, simultaneously to whole pixel output Φ RESETn ... with Φ READn ... pulse.Therefore, all can implement the discharge of PD and reading of PD simultaneously in the pixel.

Fig. 4 is the oscillogram of driving timing of the action of expression " MODE1 ".At this moment, imageing sensor is by 1 field 30Hz action, and juxtaposed horizontal line number is 480 lines on the vertical direction.

At first, pulse selector 7 begins signal for the photodiode (PD) of discharging whole unit 1 during vertical flyback, whole Φ READ1～Φ READ480 is made as HI simultaneously.At this moment, (give up in power supply (VDD), removing?) signal read in the test section (DN), whole Φ READ1～Φ READ480 is made as HI.Afterwards, carry out light-to-current inversion and storage signal electric charge by photodiode (PD).Then, after finishing during the vertical flyback, read simultaneously before the signal charge of the photodiode (PD) of storage in whole unit 1, the invalid signals for the leakage current of removing test section (DN) etc. is made as HI with whole Φ READ1～Φ READ480.Then, whole Φ READ1～Φ READ480 are made as HI, and all the signal charge while of the photodiode (PD) of storage reads at test section (DN) simultaneously in the unit 1.

Afterwards, be used to export the signal of 1 horizontal signal in per 1 the horizontal line retrace interval during the vertical effective scanning from test section (DN) output.For example, during the signal of reading horizontal line No.1, pulse selector 7 is made as HI with Φ ADRES1.Thus, read " signal level+reset level " on the vertical signal line (VLIN).Subsequently, by pulse selector 7 Φ RESET1 is made as HI and reset detection portion (DN), vertical signal line (VLIN) is gone up the output reset level, and AD translation circuit 2 is got except that reset level from " signal level+reset level " by the difference action of de-noising circuit, only output signal.

Fig. 5 is the oscillogram of driving timing of the action of expression " MODE2 ".This moment, imageing sensor was also by 1 field 30Hz action.

At first, Φ READ1, Φ RESET1 are made as HI, the signal of the photodiode (PD) of discharge water horizontal line No.1 during the horizontal flyback sweep of pulse selector 7 in during vertical effective scanning.Should action to horizontal line No.1～480 reiterations.Afterwards, by photodiode (PD) light-to-current inversion and storage signal electric charge.And, read the signal charge of photodiode (PD) in during next vertical effective scanning.

For example, during the signal of reading horizontal line No.1, Φ ADRES1, Φ RESET1 are made as HI and go up the output reset level at vertical signal line (VLIN) by pulse selector 7.Then, by pulse selector 7 Φ READ1 is made as HI and reads " signal level+reset level " on vertical signal line (VLIN).Then, AD translation circuit 2 is got except that reset level from " signal level+reset level " by de-noising circuit, only AD figure signal and export from imageing sensor.

Fig. 6 is the timing diagram of action of the cmos image sensor of this first embodiment of expression.Among Fig. 6, represent the variation of the memory time of photodiodes by memory time 1,2,3.Among this first embodiment, number of scanning lines is set at 2 times original 1050 lines.That is, during the vertical flyback being is 480 lines (480H) during 570 lines (570H), the vertical effective scanning.

As can be seen from Figure 6, under " MODE1 ", the storage time started of whole horizontal line No.1～480 is identical, and all the PD discharge is read by identical timing action with PD in horizontal line No.1～480.The output of the signal of reading in the test section (DN) is carried out during vertical effective scanning in order.But the PD discharging operation is not with overlapping to the output action of vertical signal line (VLIN).

In memory time 1, the signal charge of whole photodiodes (PD) storage is read in all photodiode (PD) storages in the whole period of 1 frame (1050H) (or 1 field) simultaneously at test section (DN).In the frame (or field) then, the signal charge from horizontal line No.1 to horizontal line No.480 reads into vertical signal line (VLIN) during about 1/2 vertical effective scanning during vertical in order.

In memory time 2 then, express situation by about 2 times of input light input signals of memory time 1.In this memory time 2,2 Φ READ of interior generation pulse during the vertical flyback, enforcement 1PD reads action and 2PD reads action.In order in test section (DN) signal charge of photodiode (PD) light-to-current inversion and storage to be read, generation Φ READ pulse is also implemented 1PD and is read action in during the vertical flyback.Then, for reading the signal that photodiode (PD) is stored again, generation Φ READ pulse is also implemented 2PD and is read action when finishing during the vertical flyback.2 times the light input signal of memory time can be transformed to signal charge and output in this action.

In addition, with the situation of representing that the light input signal amount is many memory time 3.In this memory time 3, produce 2 Φ READ pulse in during 1/2 vertical flyback, implement that 1PD reads action and 2PD reads action, with the about 2 times signal charge that obtains photodiode (PD) memory time 2 equally.In the frame (or field) then, the signal charge from horizontal line No.1 to horizontal line No.480 reads into vertical signal line (VLIN) during about 1/2 vertical effective scanning during vertical.

By this action, can be from 1H to 1 image duration (or 1 field during) continuous control memory time.In addition, by Φ READ pulse is produced 2 times, can obtain the saturated semaphore more than 2 times of photodiode (PD) in 1 image duration (or 1 field during).In addition, by be made as during the vertical effective scanning 1/2 frame (or field) (1/2V) during, the leakage current of test section can be reduced to 1/2.Therefore, S/N can be improved more than 2 times.In the present embodiment, although produce Φ READ read pulse more than 2 times, if the saturated aspect of test section has affluence also can produce more than 3 times.Compare with the memory time of reading action from the PD discharging operation to PD memory time, can extend to read from 1PD and move 2PD and read memory time of action.In this action, the saturated inequality of PD portion when not producing 1PD and reading, but addition 2PD read output signal.When 2PD reads, when PD portion is saturated, when reading, 1PD, can not go wrong because PD portion is saturated yet.In addition, in can being set at memory time during whole period of 1 frame or the vertical flyback arbitrarily during.

Fig. 7 A is the sectional view and the electromotive force action diagram of photodiode (PD) of action of the memory time 2 of key diagram 6.Form photodiode (PD) and test section (DN) and leakage (VDD) on the silicon substrate that p trap or p substrate constitute with the low leakage type of n type of p type shielded surfaces.Signal reads grid (Φ READ) and resetting gate (Φ REEST) is formed by polysilicon.Test section (DN) is connected in the AMP transistor (Tb) of output usefulness.Fig. 7 B represents to read potential energy diagram before near 1PD.Be electric charge with converting optical signals in the photodiode (PD), store saturated signal charge Q1 basically near photodiode (PD).Fig. 7 C represents to read potential energy diagram afterwards near 1PD.In test section (DN) from photodiode (PD) read output signal charge Q 1.The voltage that applies of read pulse Φ READ is read by the dark Vh of electromotive force than photodiode (PD).The electromotive force of photodiode is owing to the surface with P type shielded from light electric diode (PD) portion, and is therefore dark unlike the electromotive force that forms by certain certain read-out voltage.Fig. 7 D represents to read potential energy diagram before near 2PD.Be electric charge with converting optical signals once more in the photodiode (PD), storage is basically near the saturated signal charge Q2 of photodiode (PD).Potential energy diagram after Fig. 7 E represents to read near 2PD.The signal charge (Q1+Q2) that the signal charge Q1 addition of storage obtains signal charge Q2 that reads from photodiode (PD) and the test section (DN) is stored in the test section (DN).That is, can obtain roughly 2 times the signal charge of photodiode (PD).Equally, also can obtain roughly 2 times the signal charge of photodiode (PD) in memory time 3.

Among first embodiment, since original 1/2 with being made as between the vertical signal line reading duration, so imageing sensor is output as the signal of 2 times the 24MHz of original 12MHz.In addition, therefore 1/2 between the signal period of output during the vertical effective scanning of boil down to for outputing to common VGA monitor, need externally to carry out velocity transformation in the frame memory.

Among this first embodiment, " MODE1 " and " MODE2 " changeable use." MODE1 " can improve simultaneity.But, because the deviation of per 1 pixel that the KTC noise shown in Figure 20 (back explanation) causes makes to produce granular noise, image quality aggravation.On the other hand, in " MODE2 " shown in Figure 5, can not improve simultaneity, but, therefore not produce granular noise, become high image quality owing to can eliminate the KTC noise.

Fig. 8 is the flow chart of the setting order of expression " MODE1 " and " MODE2 ".MODE switches can be by manual setting and automatic setting control.The action of Fig. 8 is carried out by the control of above-mentioned control part C.

Among the step S1, when in carrying the camera (for example video tape recorder) of this imageing sensor, manually setting by the user, among the step S2, control part C sets " MODE1 " that improves simultaneity as the physical culture pattern, as " MODE2 " that set by mode standard as high image quality.

Among the step S1, when carrying out automatic setting by the user in this camera, among the step S3, control part C handles the DSP that uses by colour signal and judges it is to amplify the gain of using imageing sensor by 1 times of use or gain.When gain is amplified among the step S4, it is dark but obtain " MODE2 " of the mode standard of high image quality to set subject.When being not the gain amplification, among the step S5, judge semaphore, change memory time (TS) among the step S6.Set among the step S8 " MODE1 " memory time among the step S7 (TS) than 1050H in short-term.When memory time among the step S7, (TS) was 1050H, set among the step S9 " MODE2 ".By the setting of this " MODE1 " and " MODE2 ", among the step S10, timing generating circuit 8 switches the pulse of output Φ READ, Φ VREAD, Φ RESET.The fiducial value that the gain judgement of step 3 and the memory time of step 7 are judged can change arbitrarily.

But read frequency is accelerated among first embodiment, especially, is made as 2 times horizontal line in the high visual field film (highvision movie) of 2,000,000 pixels when counting, and the signal of 37MHz becomes 2 times 75MHz at a high speed.

Fig. 9 represents the countermeasure of first embodiment.Make during the vertical flyback consistent with the light period of fluorescent lamp.For example, be that the zone of 60Hz is set at 8.3mS, is that the zone of 50Hz is set at 10mS in the frequency of electric power system in the frequency of electric power system during the vertical flyback.Fig. 9 represents the action of 8.3mS during the vertical flyback in zone of 60Hz.In the 30HzVGA action of standard, vertical scanning period is set at the 2.8mS of 45H.In the example of Fig. 9, press the horizontal line number action of 8.3mS, the 1 frame 640H of 160H during the vertical flyback.Operating frequency is accelerated to be original 640/525=1.22 times.There is the frequency slightly of 45MHz to increase in the high visual field film of 2,000,000 pixels.During than long memory time of the 8.3mS of the minimum light period of fluorescent lamp, carry out " MODE2 ".Set " MODE1 " during smaller or equal to 8.3mS memory time.By this action, the operating frequency increase by slightly can improve the simultaneity below 83mS memory time.

In the camera of the lens stop F2.8 of the cmos image sensor of 330,000 pixels of using first embodiment, it during common office photography the memory time about 10mS.For implementing in brighter place such as physical culture, improving simultaneity below 8.3mS memory time (10mS) is effective method.When 8.3mS memory time (10mS) was following, during by " MODE2 " photography, each horizontal storage time started departed from, and the luminous quantity that therefore produces fluorescent lamp is poor, produces the horizontal stripe of the luminance of corresponding fluorescent lamp in the reproduction picture of monitor.Therefore, by being made as " MODE1 ", 1 frame stored time started is identical, does not therefore produce the horizontal stripe of the luminance of corresponding fluorescent lamp.But interframe produces signal level difference, yet, can be same with the CCD imaging apparatus, by improving by every frame ride gain (GAIN).Switching to " MODE1 " when therefore, 8.3mS memory time (10mS) is following is effective method.

The switching benchmark of " MODE1 " and " MODE2 " can be 2 times 20mS or 16.6mS of the minimum light period of fluorescent lamp, when producing 1/2 memory time of fluorescent lamp flicker, can be set at 4.15mS (5mS).In addition, do not change vertical effective scanning line number among first embodiment and increase during the vertical flyback.But reducing vertical effective scanning line number increases during the vertical flyback also passable.The valid pixel number of VGA is level 640 pixels, vertical 480 pixels, the ratio of width to height 4: 3.With the vertical cutting of 360 pixels its, be 16: 9 of HDTV specification to make it, obtain the 10.5mS of 165H during 360H during the vertical effective scanning, the vertical flyback by 1 frame 525H.In addition, in 1,230,000 pixels of 4 times of pixel counts of VGA, become vertical 720 pixels by being made as 16: 9 of HDTV mode under level 1280 pixels, vertical 960 pixels, can meet level 1280 pixels of HDTV, the specification of vertical 720 pixels.Under the 60Hz action situation of HDTV mode, the 8.3mS (10mS) that arrives the luminous least unit of fluorescent lamp memory time implements " MODE2 " before.At its 4.15mS of 1/2 or switch to " MODE1 " below the 5mS.Under the mode that reduces this vertical effective scanning line, can realize with original identical frequency, do not need frame memory yet.In addition, same under " MODE1 " with Fig. 6, PD is read enforcement more than 2 times, obtain 2 times saturation signal of photodiode, improve the S/N ratio.

Figure 10 is the figure of circuit structure of the countermeasure of expression first embodiment.Discharge with transistor T e and distribution Φ ESREAD (electronic shutter read pulse) by the signal that appends photodiode (PD) on each unit 1, on the vertical signal line (VLIN) can with read action and irrespectively carry out discharging operation.Therefore, as original, can be by action memory time of 1 frame 525H.Consequently the output of imageing sensor is also as the signal that originally becomes 12MHz.

The example that is suitable for the solid camera head of this first embodiment at the digital VTR that is used for cartoon photographic has been described in above-mentioned, but this solid camera head is also applicable to the digital camera that is used for still image photographing.

Figure 11 is the block diagram of structure of the digital camera of the expression solid camera head that is suitable for the first embodiment of the present invention.Digital camera 200 comprises microcomputer 201, connects signal processing part 202, Image Data Compression portion 203 and video memory 204 regularly take place on microcomputer 201.Connect video memory 204 and LCD monitor 205 in the Image Data Compression portion 203.In addition, configuration this solid camera head (transducer) S on the optical axis of lens 206, solid camera head S go up to connect signal processing part 202 regularly take place.In addition, comprise power supply unit 207 on the digital camera 200.

Picture signal handling part 202, Image Data Compression portion 203 and video memory 204 regularly take place in microcomputer 201 controls.Transducer S outputs to timing with this picture signal picture signal handling part 202 takes place according to the picture of the signal picked-up that comes self-timing generation picture signal handling part 202 through lens 206 incidents.The picture signal that picture signal handling part 202 handles regularly taking place output to Image Data Compression portion 203, is transformed to analog signal and is presented on the LCD monitor 205.When depressing photo knob, picture signal is recorded on the video memory 204 by 203 data compressions of Image Data Compression portion.Under the reproduction mode, read into data the Image Data Compression portion 103 and be transformed to analog signal, be presented on the LCD monitor from video memory 204.

Solid camera head S is applicable under the situation of digital camera 200, and is identical under the action of solid camera head S and the situation that is applicable to digital camera 100.

Figure 12 is the figure of circuit structure of scale-up version cmos image sensor S of 330,000 pixels of the expression second embodiment of the present invention.Among Figure 12, the part identical with Fig. 1 adds same-sign.In this structure, comprise 3 vertical movement transistors.Do not have whole pixels to read special-purpose Φ READ DRIVER simultaneously, but input Φ READ pulse on the pulse selector 71 is supplied with as Φ READn to each horizontal line from pulse selector 71.In addition, by control circuit 81 control vertical transfer registers memory time (ES) 5, vertical transfer register (RO) 6 and " MODE1 " pulse generating circuit 82 with " MODE2 ".Be controlled to and cooperate the output signal that memory time, control circuit 81 came switch pulse generation circuit 82 to the switching of " MODE1 " and the pulse of " MODE2 ".

Figure 13 is the circuit diagram of pulse selector 71.Output ROn, ESn (electronic shutter control input pulse), ADRn to pulse selector 71 is supplied with from 3 vertical transfer registers (RO) 6, (ES) 5, (ADR) 10 export Φ READn, Φ RESETn, Φ ADRESn through AND circuit, OR circuit to unit 1.Supply with Φ READ, Φ ADRES, Φ RESET from timing generating circuit 8 to each AND circuit.

Figure 14 is the oscillogram of driving timing of the action of expression " MODE1 ".At this moment, imageing sensor is by 1 field 30Hz action.

Among Figure 14, order is discharged for example signal of 4 horizontal photodiodes (PD) during the horizontal effective scanning of corresponding stored time.At this moment, pulse selector 71 order during horizontal effective scanning applies Φ RESET1～Φ RESET4 to each test section (DN), and each test section (DN) resets.Then, pulse selector 71 applies Φ READ1～Φ READ4 to each photodiode (PD) order during next horizontal effective scanning, carry out the discharging operation of signal by electronic shutter.Equally, pulse selector 71 each test section (DN) order to next 4 line during next horizontal effective scanning applies Φ RESET5～Φ RESET8, and each test section (DN) resets.Pulse selector 71 applies Φ READ5～Φ READ8 to each photodiode (PD) order during next horizontal effective scanning then, carries out the discharging operation of signal by electronic shutter.Reiteration should move, and discharged the signal of whole horizontal photodiodes (PD).

Then, after the memory time of setting by ESDATA, carry out reading action from the signal of photodiode (PD).At this moment, pulse selector 71 applies Φ RESET1～Φ RESET4 to each test section pipe (DN) order during horizontal effective scanning, and each test section (DN) resets.Then, pulse selector 71 applies Φ READ1～Φ READ4 to each photodiode (PD) order during next horizontal effective scanning, carry out the action of reading from photodiode (PD).Equally, pulse selector 71 each test section (DN) order to next 4 line during next horizontal effective scanning applies Φ RESET5～Φ RESET8, and each test section (DN) resets.Pulse selector 71 applies Φ READ5～Φ READ8 to each photodiode (PD) order during next horizontal effective scanning then, carries out the action of reading from photodiode (PD).Reiteration should move, and read the signal of whole horizontal photodiodes (PD).

Afterwards, carry out reading to vertical signal line VLIN.At first, pulse selector 71 is made as HI with Φ ADRES1, and " signal level+reset level " of the test section of horizontal line No.1 read into vertical signal line.Then, by pulse selector 71 Φ RESET1 is made as HI reset detection portion, to vertical signal line output reset level, AD translation circuit 2 is got except that reset level from " signal level+reset level " by the difference action of de-noising circuit, only output signal.This action by each horizontal flyback sweep during 1 horizontal line ground order of 1 horizontal line carry out.

Figure 15 is the figure of the output waveform of expression vertical transfer register (ES) 5, (RO) 6, (ADR) 10.Among Figure 15, cooperate the output waveform of Figure 14, when the electronic shutter during 1 horizontal effective scanning is discharged, become HI in proper order from the ES1～ES4 of vertical transfer register (ES) 5.In addition, when the signal during 1 horizontal effective scanning is read, become HI in proper order from the RO1～RO4 of vertical transfer register (RO) 6.When vertical signal line is exported, become HI from the ADR1～ADR4 of vertical transfer register (ADR) 10 order during horizontal effective scanning.Carry out this action for horizontal line No.1～480 orders.

Among this second embodiment, discharge of the electronic shutter of 4 horizontal line enforcement photodiodes (PD) and signal are read during 1 horizontal effective scanning, but as long as in the scope that Φ READ pulse and Φ RESET pulse can be replied, the line number during per 1 horizontal effective scanning can increase.In addition, pulse produces and is not limited to during 1 horizontal effective scanning, can 1 horizontal scan period during comprising horizontal flyback sweep produce.

Figure 16 is the figure of the driving timing of the expression action of comparing further " MODE1 " that improves simultaneity with Figure 14.

Among Figure 16, when electronic shutter is discharged and signal when reading, be 1 group in during 1 horizontal effective scanning, select these a plurality of horizontal lines simultaneously,, discharge or read in proper order from photodiode (PD) by a plurality of horizontal each group of selecting with a plurality of horizontal lines.For example, pulse selector 71 applies Φ READ1～Φ READ4 by the pulse of identical phase place.Then, the pulse by identical phase place applies Φ READ5～Φ READ8.Like this, be 1 group of pulse that applies same phase with 4 horizontal lines, in addition, apply by per 4 horizontal line ground successive offset phase places, compare with the situation of Figure 14, can obtain 4 times simultaneity.4 horizontal lines are same phase, but can be increased to possible line number from 2 horizontal lines.

Figure 17 is the figure of the output waveform of expression vertical transfer register (ES) 5, (RO) 6.Among Figure 17, cooperate the output waveform of Figure 16, the output of the output of vertical transfer register (ES) 5 and vertical transfer register (RO) 6 is 1 group with 4 horizontal lines and becomes HI simultaneously respectively.Vertical transfer register (ADR) becomes HI with the same per 1 horizontal line ground of per 1 horizontal line of Fig. 5.

Figure 18 is the figure of the action of the above-mentioned cmos image sensor of expression.Among Figure 18, represent the variation of the memory time of photodiodes with memory time 1,2,3.1 o'clock the longest memory time, only 1 horizontal line enforcement PD discharge, PD read during 1 horizontal effective scanning.Therefore, the time started of respectively storing of horizontal line No.1 and horizontal line No.480 is departed from 1 frame (30Hz) approximately.On the other hand, in memory time 2,2 horizontal lines enforcement PD discharge, PD read during 1 horizontal effective scanning.Therefore, compare with memory time 1, it is about 1/2 that the difference of respectively storing the time started of horizontal line No.1 and horizontal line No.480 becomes, and simultaneity is enhanced.In addition, in memory time 3,8 horizontal lines enforcement PD discharge, PD read during 1 horizontal effective scanning.Therefore, compare with memory time 1, the difference of respectively storing the time started of horizontal line No.1 and horizontal line No.480 is improved as about 1/8.In addition, read, can further improve simultaneity by 16 horizontal lines during 1 horizontal effective scanning, 32 horizontal lines enforcement PD discharge, PD.The signal that test section (DN) is gone up storage has nothing to do to reading with memory time of vertical signal line (VLIN), 1 horizontal line ground output of 1 horizontal line during horizontal effective scanning.

In the mechanical shutter of general slr camera, implement the focal plane action of 1/125 second～1/250 second shutter speed.In the present embodiment, during the action of 30Hz (1/30 second) cartoon photographic,, become 1/120 second or 1/240 second shutter speed of 8 times of speed of 4 times of speed by reading 4 horizontal lines or 8 horizontal actions during 1 horizontal effective scanning, same with slr camera.In addition,, compare, can improve simultaneity with slr camera by increasing the horizontal line number.

As mentioned above, in the present embodiment, switch and carry out the action of " MODE1 " and " MODE2 ", " MODE1 " can improve simultaneity down.But, because the deviation of per 1 pixel that the KTC noise shown in Figure 20 (back explanation) causes makes to produce granular noise, image quality aggravation.On the other hand, can not improve simultaneity in " MODE2 ", but, therefore not produce granular noise, become high image quality owing to can eliminate the KTC noise.The timing diagram of MODE2 is identical with Fig. 5.

Figure 19 is the flow chart of the setting order of expression " MODE1 " and " MODE2 ".MODE switches can be by manual setting and automatic setting control.The action of Figure 19 is carried out by the control of above-mentioned control part C.

Among the step S11, when in carrying the camera (for example video tape recorder) of this imageing sensor, manually setting by the user, among the step S12, control part C sets " MODE1 " that improves simultaneity as the physical culture pattern, as " MODE2 " that set high image quality by mode standard.

Among the step S11, when carrying out automatic setting by the user in this camera, among the step S13, control part C handles the DSP that uses by colour signal and judges it is to amplify the gain of using imageing sensor by 1 times of use or gain.When gain is amplified among the step S14, it is dark but obtain " MODE2 " of the mode standard of high image quality to set subject.When being not the gain amplification, among the step S15, judge semaphore, change memory time (TS) among the step S16.Set among the step S18 " MODE1 " memory time among the step S17 (TS) than 525H in short-term.When memory time among the step S17, (TS) was 525H, set among the step S19 " MODE2 ".By the setting of this " MODE1 " and " MODE2 ", among the step S20, the pulse that timing generating circuit 8 switches output Φ READ and Φ RESET.The fiducial value that the gain judgement of step 13 and the memory time of step 17 are judged can change arbitrarily.

In the READ pulse generating circuit in the timing generating circuit 8, but line number (produced simultaneously horizontal line number) takes place in Φ READ pulse generation number and Φ READ that the corresponding stored time changes in the 1H.

Φ READ pulse generation number in the 1H is:

Φ READ pulse generation number=1+ (525-storage line number)/storage line number

The line number takes place Φ READ can line number=Φ READ pulse generation number/maximum Φ READ pulse generation number calculating take place from Φ READ.Maximum Φ READ pulse generation number is made as 32.Φ READ pulse generation numerical table produces Φ READ pulse several times during showing 1H, and this cycle of pressing 1.98 microseconds during 1/30 (second)/525 (line)=63.5 microsecond produces 32 times Φ READ pulse.

Simultaneity (distortion line) is few more for the distortion line number that souvenir goes out, and improves.The fiducial value that the gain judgement of step S13 and the memory time of step S17 are judged can change arbitrarily.

General slr camera is nearly all implemented the focal-plane shutter action.Focal-plane shutter is moving the slit in film the place ahead up and down or on the left and right directions.General acceptable current slr camera usually with gap width as opening comprehensively, move by 1/125～1/250 second shutter speed.In the camera of present embodiment,, obtain and use the same simultaneity of slr camera in slit up and down by being 1/125 second memory time 126H, being 63H by 1/250 second memory time.In addition, memory time is short more, and slr camera improves simultaneity more.

The timing diagram of the KTC noise countermeasure when Figure 20 is the expression low-light (level).For example, in the memory time 2 and memory time 3 of Figure 18, implement " MODE1 " of Figure 20.At this moment, because subject is very bright, make the electronic shutter action.Therefore, signal level increases, and the KTC noise effect is little.In contrast, during low-light (level), the action for memory time 1 can not get simultaneity.At this moment, implement " MODE2 ",, but be stored on the photodiode (PD), from photodiode (PD) read output signal, output to vertical signal line (VLII) during per 1 horizontal flyback sweep not in test section (DN) storage signal.

Under " MODE1 ", at first, for the invalid signals of leakage current of reset detection portion (DN) etc. applies Φ RESET pulse.Then, for the signal that reads out from photodiode (PD) applies Φ READ pulse, read and inhibit signal at test section (DN).Then, when applying Φ ADRES pulse during the horizontal flyback sweep, " signal level+reset level " that test section (DN) keeps outputs to vertical signal line (VLIN).Then, apply Φ RESET pulse, to vertical signal line (VLIN) output reset level.Afterwards, implementing reset level and move with the difference of " signal level+reset level " in AD translation circuit 2, remove the reset noise composition from " signal level+reset level ", only is signal.But, because the reset level during the reset level of initial test section (DN) and the horizontal flyback sweep is different, sneaked into the KTC noise in this signal.

On the other hand, under " MODE2 ", at first, for the invalid signals of leakage current of reset detection portion (DN) etc. applies Φ RESET pulse.At this moment, to vertical signal line (VLIN) output reset level.Then, apply Φ READ pulse for the signal that reads out from photodiode (PD).Like this, at test section (DN) read output signal.Should " signal level+reset level " output to vertical signal line (VLIN).Afterwards, implementing reset level and move with the difference of " signal level+reset level " in AD translation circuit 2, remove the reset noise composition from " signal level+reset level ", only is signal.Because reset level does not change, therefore do not sneak into the KTC noise in this action.

Signal is with positive output in " MODE1 ".On the other hand, " MODE1 " middle signal is with negative output.The signal of counter-rotating " MODE2 " was to become signal just when therefore, numeral was exported.

In " MODE1 ", at first, test section (DN) has signal, afterwards, because reset detection portion (DN) is sneaked in the test section after resetting (DN) because the KTC noise that the level difference of homing action causes.On the other hand, in " MODE2 ", at first reset level is exported in reset detection portion (DN) back, so sneaks into the KTC noise in this reset level.Afterwards, from photodiode (PD) read output signal of conveying type fully.Test section (DN) is " reset level that comprises signal level+KTC noise ".And, in the AD translation circuit 2,, get and remove the reset level that comprises the KTC noise by " reset level that comprises signal level+KTC noise " difference action with the reset level that comprises the KTC noise, can only export the signal that does not comprise the KTC noise.Be somebody's turn to do the high S/Nization that " MODE1 " and " MODE2 " can realize low-light (level) by the switching of corresponding stored time.

In the foregoing description, narrated 1 pixel, 1 cellular constructions that constitute by 1 photodiode (PD) and 4 transistors, but KTC noise that also can be when switching " MODE1 " and " MODE2 " reduction low-light (level) in 1 pixel, 1 cellular construction that constitutes by 1 photodiode (PD) and 5 transistors shown in Figure 10.

In addition, so-called " MODE1 " and " MODE2 " is the signal polarity counter-rotating after the AD conversion.Among Figure 12, the output after " MODE1 " and " MODE2 " reverses the AD conversion down.The method that the input polarity of the opening comparator that switches the AD translation circuit under " MODE1 " and " MODE2 " is arranged in addition.At this moment, under " MODE1 ", with the positive side of signal input comparator, with RAMP waveform input minus side.On the other hand, under " MODE2 ", on the contrary,, the RAMP waveform is imported positive side with the minus side of signal input comparator.By in the input of comparator, reversal amplifier being set, whether use counter-rotating to amplify by " MODE1 " and " MODE2 " is changeable.In the foregoing description, be that example is illustrated with the imageing sensor of 330,000 pixel VGA modes, but can be than its more pixel count.

The storage time started that the original C mos image sensor normally cooperates the per 1 horizontal line ground of the operating frequency of 1 frame to depart from each photodiode moves.Therefore, from initial horizontal line horizontal line to the end, storage time started difference when absorbing dynamic subject, has image to become the improper situation of inclination, points out to be short of simultaneity.

Different therewith, present embodiment in the electronic shutter action of cmos image sensor, execution be interior 2 time-division ground actions of reading the signal of storing in the photodiode of two-dimensional arrangement above the horizon during 1 horizontal effective scanning by each line.The memory time of this electronic shutter action is short more, and the interior sense wire number from photodiode increases during 1 horizontal effective scanning.By this method, can be corresponding electronic shutter improve simultaneity memory time and do not change during the vertical flyback.

In addition, additional embodiments is in the electronic shutter action of cmos image sensor, that carry out is 1/2 4.15mS by being made as luminous minimum period of becoming fluorescent lamp during the vertical flyback with 1 frame (or 1 field) or 5mS is above and about below 1/2 in 1 image duration (or 1 field), after discharging signal simultaneously from whole photodiodes of two-dimensional arrangement, with above-mentioned each photodiode storage signal, the action of after memory time, reading the signal of above-mentioned whole photodiodes simultaneously.

By will being set at 1/2 during the vertical flyback, can be in 1 whole image duration with fader control at 1/2 pitch (step).That is, memory time controlled 1 frame, 1/2 frame, 1/4 frame of being made as ...In addition, by below memory time 1/2 frame, can in 1 time control below the horizontal scan period, make memory time.

On the other hand, by with being set at 1/2 4.15mS or the 5mS of luminous minimum period of becoming fluorescent lamp during the vertical flyback or being set at 8.3mS or the 10mS of the luminous minimum period that becomes fluorescent lamp, can realize the continuous cartoon photographic of MPEG mode, Motion JPEG mode etc.Especially, the ratio of width to height by the HDTV mode is 9 pairs 16, can not use memory and the action that directly shows on monitor.In addition, the number of scanning lines of 1 frame does not increase, and can carry out the action same with original driving frequency.

In the present embodiment,, but also be applicable to the interleaving mode of 2 field 1 pictures by the progressive mode explanation that obtains 1 image 1 image duration.

Figure 21 is the figure of circuit structure of cmos image sensor (solid camera head) S of 330,000 pixels that form on semiconductor substrate of the expression third embodiment of the present invention.Part identical with Fig. 2 among Figure 21 adds same-sign.Among Figure 21, connect frame memory 11 and subtraction circuit 12 on the AD translation circuit 2, in addition, frame memory 11 connects subtraction circuit 12.

Figure 22 is the timing diagram of action of the cmos image sensor of expression the 3rd embodiment.Among Figure 22, represent the memory time of photodiode with memory time 1.Among the 3rd embodiment, be 1095H during the vertical flyback, vertically be 480H during the effective scanning.

As can be seen from Figure 22, in " MODE1 ", the storage time started of whole horizontal line No.1～480 is identical, and all the PD discharge is read with identical timing action with PD in horizontal line No.1～480.The output of the signal of reading in the test section (DN) 1 frame (1575H) (or 1 field) 1/3 during the order carry out.But, the PD discharging operation with carry out to the output action of vertical signal line (VLIN) is not overlapping.The signal charge of horizontal line No.1～480 is when the output action of vertical signal line (VLIN), before Φ READ is made as HI, Φ RESET is made as HI, remove the leakage current of test section (DN) after, from photodiode (PD) to test section (DN) read output signal.

In memory time 1,1 frame (1575H) (or 1 field) 2/3 during with whole photodiodes (PD) storages, read the signal charge of whole photodiodes (PD) storage simultaneously at test section (DN).Afterwards, order is read signal charge from horizontal line No.1 to line No.480 to vertical signal line (VLIN) in during 1/3 of 1 frame.The signal sequence of reading at vertical signal line (VLIN) is transformed to digital signal by AD translation circuit 2 and is stored in the frame memory 11.At this moment, also store the signal of the leakage current (dark current) of test section (DN) in the frame memory 11 with the signal of photodiode (PD).

Then, behind the whole test sections of beginning Reset (DN) of (1 frame 1/3 during) during the vertical effective scanning, do not apply Φ READ pulse, but order will be read into vertical signal line (VLIN) by the leakage current charge stored of test section (DN).Be transformed in digital signal and the input subtraction circuit 12 by AD translation circuit 2 at the signal sequence that vertical signal line (VLIN) is read.At this moment, only import the signal of the leakage current of test section (DN) in the subtraction circuit 12.

The signal of having exported the leakage current of the signal of photodiode (PD) of unit of signal of the leakage current that is input to subtraction circuit 12 and test section (DN) is read into subtraction circuit 12 from frame memory 11.Subtraction circuit 12 deducts from the signal of the leakage current of the signal of the photodiode (PD) read from frame memory 11 and test section (DN) from the signal and the output of the leakage current of the test section (DN) of AD translation circuit 2 inputs.That is, the leakage current of test section (DN) is about 100 times a size of the dark current of photodiode (PD).

In addition, in the above-mentioned example, the signal storage of the leakage current of the signal of photodiode (PD) and test section (DN) is in frame memory 11, afterwards, only import the signal of the leakage current of test section (DN) in the subtraction circuit 12, but behind the signal input subtraction circuit 12 with the leakage current of the signal of photodiode (PD) and test section (DN), only in frame memory 11, store the signal of the leakage current of test section (DN), carry out same subtraction process.

According to the 3rd embodiment,, can obtain the image that image quality is further improved by removing the leakage current of test section (DN).

As mentioned above, solid camera head can be realized image quality improving according to an embodiment of the invention.That is, can improve the shortcoming of the no simultaneity of cmos image sensor, use the little transducer of image size can improve simultaneity, in addition, can realize should right KTC noise the low-light (level) photography, can obtain the image of leakage current that should right test section (DN) simultaneously.In addition, the solid camera head of embodiments of the invention except that digital camera, digital camera also applicable to the band camera portable phone in.

Solid camera head can provide solid camera head, digital camera and the digital camera of realizing image quality improving according to an embodiment of the invention.

Claims (18)

1. solid camera head, from in two-dimensional arrangement on the semiconductor substrate photodiode, be used for discharging signal from the above-mentioned photodiode of each unit of reading grid and being used to detect the test section of the signal of reading of this photodiode read output signal after, with above-mentioned each photodiode storage signal, after its memory time, from above-mentioned each photodiode read output signal, it is characterized in that, comprise

First pulse signal that a plurality of horizontal lines ground carries out being used to discharge the signal of 1 horizontal described each photodiode in the 1st horizontal scan period is applied to the action of corresponding described each unit, and second pulse signal that a plurality of horizontal lines ground carries out being used to read the signal of 1 horizontal described each photodiode in the 2nd horizontal scan period is applied to the circuit of action of described each unit of correspondence simultaneously.

2. solid camera head according to claim 1 is characterized in that,

When described circuit shortened more in described memory time, increase the number of times that applies the action of described first and second pulse signals in described first and second horizontal scan period more.

3. solid camera head according to claim 1 is characterized in that, comprises

Switch the commutation circuit of first pattern and second pattern, described first pattern is to read the signal of storing in the described photodiode and detect the signal level of this test section at described test section, described test section afterwards resets, detect the reset level of this test section, output is based on the signal of the difference of described detected signal level and reset level, and described second pattern is to reset described test section before described photodiode read output signal, detect the reset level of this test section, read the signal of storing in the described photodiode and detect the signal level of this test section at described test section afterwards, output is based on the signal of the difference of described detected reset level and signal level

Described commutation circuit switches to described first pattern during less than the very first time in described memory time, switch to described second pattern during more than or equal to described first stipulated time in described memory time.

4. solid camera head according to claim 1 is characterized in that,

When described circuit is discharged the signal of described each photodiode at the same time, also simultaneously it is read.

5. solid camera head according to claim 1 is characterized in that,

The vertical scanning period of described circuit during 1 frame or 1 field produces more than 2 times the signal read pulse of described photodiode, signal plus and the output that will read from described photodiode.

6. solid camera head, from in two-dimensional arrangement on the semiconductor substrate photodiode, be used for discharging signal from the described photodiode of each unit of reading grid and being used to detect the test section of the signal of reading of this photodiode read output signal after, with described each photodiode storage signal, after its memory time, at described test section behind described each photodiode read output signal, from described test section output signal, it is characterized in that, comprise

The first pulse signal that many horizontal scanning lines carry out being used for discharging the signal of 1 horizontal described each photodiode in the 1st horizontal scan period be applied to the action of corresponding described each unit, and the second pulse signal that a plurality of horizontal lines carry out being used for reading the signal of 1 horizontal described each photodiode in the 2nd horizontal scan period simultaneously is applied to the action of corresponding described each unit and the circuit that be applied to the action of corresponding described each unit to the 3rd pulse signal that each of each horizontal scan period carries out being used for the signal of 1 horizontal described test section of output.

7. solid camera head according to claim 6 is characterized in that,

Described circuit is used for discharging the action of signal simultaneously and reading all actions of the signal of horizontal described each photodiode simultaneously at whole horizontal described each photodiode.

8. solid camera head according to claim 6 is characterized in that,

Described circuit carries out discharging in proper order by each horizontal line the action of the signal of a plurality of horizontal described each photodiode during the first horizontal effective scanning, carry out calling over by each horizontal line the action of the signal of a plurality of horizontal described each photodiode during the second horizontal effective scanning.

9. solid camera head according to claim 6 is characterized in that,

Described circuit carries out discharging in proper order by every group of horizontal line the action of signal of described each photodiode of a plurality of horizontal line groups during the first horizontal effective scanning, carry out calling over by every group of horizontal line the action of signal of described each photodiode of a plurality of horizontal line groups during the second horizontal effective scanning.

10. solid camera head according to claim 6 is characterized in that,

Comprise the commutation circuit of switching first pattern and second pattern, described first pattern is to read the signal of storing in the described photodiode and detect the signal level of this test section at described test section, described test section afterwards resets, detect the reset level of this test section, output is based on the signal of the difference of described detected signal level and reset level, and described second pattern is to reset described test section before described photodiode read output signal, detect the reset level of this test section, read the signal of storing in the described photodiode and detect the signal level of this test section at described test section afterwards, output is based on the signal of the difference of described detected reset level and signal level

Described commutation circuit switches to described first pattern during less than the very first time in described memory time, switch to described second pattern during more than or equal to described first stipulated time in described memory time.

11. solid camera head according to claim 10 is characterized in that,

In described second pattern, described circuit is discharged the action of the signal of 1 horizontal described each photodiode during first horizontal flyback sweep, read the action of the signal of 1 horizontal described each photodiode during second horizontal flyback sweep.

12. solid camera head according to claim 10 is characterized in that,

In first pattern, get the poor of first signal and secondary signal, wherein said first signal is after discharging signal from the described photodiode of described each unit, with described each photodiode storage signal, after its memory time described test section behind described each photodiode read output signal from described test section output, and described secondary signal is after exporting this first signal, after the described test section that resets, export from described test section not from described photodiode read output signal.

13. solid camera head according to claim 6 is characterized in that,

In being set to described memory time during whole period of 1 frame or the vertical flyback arbitrarily during.

14. solid camera head according to claim 6 is characterized in that,

The vertical scanning period of described circuit during 1 frame or 1 field produces more than 2 times the signal read pulse of described photodiode, signal plus and the output that will read from described photodiode.

15. a digital camera is characterized in that,

Use the described solid camera head of claim 1.

16. a digital camera is characterized in that,

Use the described solid camera head of claim 6.

17. a digital camera is characterized in that,

Use the described solid camera head of claim 1.

18. a digital camera is characterized in that,

Use the described solid camera head of claim 6.

Images