CN1320636C - 具有改善的驱动电流的半导体组件及其制造方法 - Google Patents
具有改善的驱动电流的半导体组件及其制造方法 Download PDFInfo
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Abstract
一种高效能且具改善驱动电流的半导体组件及其制造方法。该半导体组件具有建立于一有源区上的源极与漏极区,组件长度是异于其宽度。制造一或一个以上的隔离区于该有源区周围,接着将该隔离区填充以一预定的隔离材料,其体积收缩经一退火程序后是超过0.5%,之后形成一栅电极于该有源区上,并形成一或一个以上的介电质侧壁间隔物是于该栅电极旁,之后再将一接触蚀刻停止层覆盖于组件上。其中该隔离区、侧壁间隔物以及接触蚀刻停止层对于施加于有源区上的净应变的调和均有贡献,因此可改善驱动电流。
Description
技术领域
本发明是有关于在互补型金属氧化半导体集成电路(CMOS integratedcircuit)中制造高效能(high performance)的场效晶体管(field-effecttransistor),且特别有关于整合或调制应变诱导(strain-induced)程序步骤以增强晶体管效能。
背景技术
极大规模集成电路(very large scale integrated circuits)中使用场效晶体管(FET)时常遭受组件制造时的某些程序步骤产生之硅以及/或硅-锗基底的晶格失配(lattice mismatch)所引发的应变力(strain stress)或机械应力(mechanical stress)等问题,而晶体管的栅极电沟道(gate electricchannel)中所引发的应变力是可影响晶体管的电场强度(electrical fieldstrength)以及载流子迁移效能(carrier mobility performance)。在互补型金氧半组件中,可将应变作用(strain effect)视为一格外困难处理的问题,因组件中是包含各种不同的晶体管类型。在一定大小以及方位的晶体管上提供不同强度及方向的应变力对于不同的晶体管型态有不同的影响;例如,张应力(tensile stress)/应变(strain)施于平行n-沟道金氧半晶体管的栅极沟道方向上将提供改善的驱动电流(drive current;Id)效能,而当同样的张力施加于一大小及方向相同的p-沟道金氧半晶体管时则将导致削减的驱动电流效能。当晶体管的大小以及距离成几何级数缩小,其应变/应力(stress)对于金氧半晶体管上的影响即变为相对更强且难以克服。
在互补型金氧半晶体管组件的制造流程中,有许多会导致应变工艺,而其中一个关键的工艺例如为浅沟槽绝缘(shallow trench isolation;STI)的制作,其涉及于基底块材上建立一用以隔离以及定义晶体管的有源区的构造;而在沟槽蚀刻、沟槽填充、平坦化以及退火(anneal)等形成一完整浅沟槽绝缘结构的工艺步骤中,将导致晶体管遭受至少来自二个轴的方向上的应力。而非直接修饰块材基底的方法也可能会施加额外的应力于晶体管上,例如产生如侧壁间隔物(sidewall spacer)以及接触蚀刻停止层(contact etch stoplayer;CES)等沉积或成长于晶体管的栅极上方以及/或邻近的薄膜。而其它产生应变的工艺例如金属硅化程序(metal silicidation process),其是牵涉在邻近栅极沟道处形成一相异材料的新层的反应。
图1是一现有的场效晶体管100的剖面图示,而图中也显示了上述中会产生应变的结构,并同时标示一三向轴以显示相对于场效晶体管100所施加的应变场(strain field)的三个方向。位于浅沟槽绝缘结构102a与102b之间的基底101范围即为晶体管的有源区,而包含一栅极氧化层103以与栅电极104的栅极区则形成于此有源区内,栅极侧壁衬垫(gate sidewallliner)105与栅极侧壁间隔物106a与106b则毗邻于该栅极区旁。如图1中所显示的栅极电沟道距离g,其定义为晶体管的栅极区域下介于源极(距离s)与漏极(距离d)基底区域的基底表面,而源极s与漏极d区域则定义为由栅极沟道的末端往外延伸至浅沟槽绝缘结构的范围。金属硅化电极(metal-silicided electrode)的区域是定义为形成于晶体管的栅极、源极以及漏极区域的上方,如图1中所显示的栅极硅化物(gate silicide)107、源极硅化物(source silicide)108以及漏极硅化物(drain silicide)109的区域,而接触蚀刻停止层110则于形成接触组件的图案化及蚀刻操作前即位于整个晶体管上方。
以下于本发明的讨论中,应变/应力是藉由三向轴x、y及z以具体说明。如图1所示,首先定义该平行基底的栅极沟道上由源极往漏极区的方向为x方向,而垂直基底的栅极沟道的张力轴线则定义为y方向,而第三应变方向的轴线z则定义为x、y轴基底平面的法线方向。注意图1中所示的晶体管的不同组成构造均将施加不同强度与方向的应变力于晶体管的栅极沟道上,而在一般的互补型金属氧化半导体技术中,其来自浅沟槽绝缘结构x-y双轴的应变是占净效应(net effect)中的一大部分。
因此,业界极需一种可调节不同组件的制造过程与结构中所引发的净应变(net strain)的方法,而本发明是提供一种工程以及设计的方法,其是利用优先调节某些强度或轴向的应变以提供n型及p型金氧半晶体管具有同步的改善。
发明内容
一种高效能且具改善驱动电流的半导体组件及其制造方法。该半导体组件具有建立于一有源区上的源极与漏极区,组件长度是异于其宽度。制造一或一个以上的隔离区于该有源区周围,接着将该隔离区填充以一预定的隔离材料,其体积收缩经一退火程序后是超过0.5%,之后形成一栅电极于该有源区上,并形成一或一个以上的介电质侧壁间隔物是于该栅电极旁,之后再将一接触蚀刻停止层覆盖于组件上。其中该隔离区、侧壁间隔物以及接触蚀刻停止层对于施加于有源区上的净应变的调和均有贡献,因此可改善驱动电流。
附图说明
图1是阐明一藉由一般普遍方法所形成的金氧半场效晶体管的剖面侧视图。
图2是说明应变场于任一三个应变轴向上的改变所造成对n型及p型金氧半场效晶体管栅极沟道的影响关系图表。
图3是阐明一金氧半场效晶体管之上方平面图,其显示晶体管有源区之长度是小于其宽度。
图4是阐明一金氧半场效晶体管的上方平面图,其显示晶体管有源区的长度是大于其宽度。
图5A及图5B是相当于图3及图4中的晶体管的样本电路布局。
图6A至图6D是依照本揭露一实施例中于某些浅沟槽绝缘制造步骤中其半导体基底的一系列剖面侧视图。
图7A至图7D为依照本揭露一实施例于建造浅沟槽绝缘结构后,一金氧半场效晶体管经由某些会产生应变的程序步骤中的一系列剖面侧视图。
图8是显示一依照本揭露的样本材料的原子结构。
符号说明:
100~场效晶体管; 101~基底;
102~浅沟槽绝缘结构; 103~栅极氧化层;
104~栅电极; 105~栅极侧壁衬垫;
106~栅极侧壁间隔物; 107~栅极硅化物;
108~源极硅化物; 109~漏极硅化物;
110~接触蚀刻停止层; 300~场效晶体管;
301~栅电极; 302~源极区;
303~漏极区; 304~浅沟槽绝缘区;
400~场效晶体管; 401~栅电极区域;
402~源极区域; 403~漏极区域;
404~浅沟槽绝缘区域; 600~场效晶体管;
601~基底; 602~浅沟槽绝缘开口;
603~沟槽侧壁衬垫层; 604~介电材料;
700~场效晶体管; 701~基底;
702~浅沟槽绝缘结构; 703~栅极氧化层;
704~栅电极; 705~侧壁衬垫层;
706~侧壁间隔物; 707~栅极硅化区域;
708~源极硅化区域; 709~漏极硅化区域;
710~接触蚀刻停止层; 800~有源区原子结构;
802~载流方向; 804~有源区宽度方向;
806~有源区长度方向。
D~由栅电极沿x应变方向至源极或漏极区最外端的距离;LOD~沿栅极沟道与x应变轴方向排列的有源区长度;W~垂直栅极沟道与y应变轴方向排列的有源区宽度;LG~栅极沟道与x应变方向成直线的距离。
具体实施方式
为让本发明的上述和其它目的、特征、和优点能更明显易懂,下文特举出较佳实施例,并配合所附图式,作详细说明如下:
本揭露是叙述一种可于互补型金氧半电路中同步改善n型及p型金氧半晶体管效能的方法,其是藉由调节来自于现有的集成电路制造过程中所产生的应变。
图2为说明应变场于任一三个应变轴向上的改变所造成对n型及p型金氧半场效晶体管栅极沟道的影响作用的表格,符号“+”或“-”代表在一所给予的方向上,其所需用以改善任一晶体管型态的驱动电流效能的应变改变。该“+”符号是表示该张应变(tensile strain)/应力增加(压缩应变(compressive strain)较小)较佳于驱动电流Id的改善,当符号为“-”时则说明一张应变的削减(较大的压缩应变)较佳;此表中所显示的应变强度与方向间的相互关系概略说明了欲同时改善n沟道与p沟道金氧半晶体管的效能的复杂度与困难度。藉由增加x-y双轴上的平面的张应变可改善n型金氧半场效晶体管的效能,而p型金氧半场效晶体管的同步改善则可藉由增加法线z方向的张应变场(tensile strain field)而达成。所增加于双轴平面上的第三应变即为一增加于全晶体管栅极沟道上的平面非等向性(anisotropic)的张应变,其将可用以改善p型金氧半晶体管的效能,并付出相对于n型金氧半晶体管所获得的净效能增益较小的代价。
图3显示一般金氧半场效晶体管300于完成晶体管的金属硅化程序后的上方平面图标,其阐述一藉由定义浅沟槽绝缘结构的方向以调和应变的范例。晶体管的栅电极301是与毗邻栅极的源极302与漏极区303一同显示,而用以局限晶体管有源区的浅沟槽绝缘区304则位于晶体管周围。图3中受浅沟槽绝缘结构所局限的晶体管有源区的尺寸是藉由距离LOD、W、D以及LG来定义。LOD是定义为沿栅极沟道的x应变轴方向的区域长度,即由源极的外端延伸至漏极范围的最末外端。距离W为有源区上垂直栅极沟道的y应变轴方向的宽度,其自源极或漏极的一外端延伸至源极或漏极的另一末端。距离D则定义为由晶体管栅电极沿该x应变方向至源极或漏极区的最外端的距离。距离LG则相当以及于晶体管的栅极沟道与x应变方向成直线的距离。此晶体管范例的有源区为矩形,浅沟槽绝缘所束缚的区域宽度W大于该区域的长度LOD,提供一由浅沟槽绝缘所诱导的双轴应变,其y轴的应变强度大于x轴的应变强度;而参照图2的图表,此种受浅沟槽绝缘结构所束缚的有源区设计对于n型金氧半组件是最有利的,并且不会损害p型金氧半组件的效能。
图4显示另一金氧半场效晶体管400的上方平面图示,该晶体管与图3的晶体管的制造用途相仿。晶体管400具有与图3的同样组成,其具有一栅电极401、源极402、漏极403以及浅沟槽绝缘404等区域,但上述组成的陈列方式有异,因此浅沟槽绝缘结构所束缚的晶体管有源区相对于图3的矩形是呈现如字母“H”的外型。图4的晶体管范例中,该晶体管的有源区宽度W(y应变方向)是小于长度LOD(x应变方向),然而注意该毗邻晶体管沟道的浅沟槽结构已被源极与漏极电极自该“H”型左侧及右侧的延伸所限制,且该受限的浅沟槽绝缘结构可有效将LOD降低至一适当与D对应的更小距离,而x应变的强度也随之下降。此“H”变型是提供栅极沟道一强度较小的x应变,因此较有利于p型金氧半晶体管。
回到图2的图表中,不同场效晶体管类型的不同晶体管区域外型将由于所施加的应变力不同而提供不同驱动电流的效能。任一场效晶体管型态的浅沟槽绝缘构造,其有目的提供设计布局(design layout)尺寸的大小将有助于晶体管效能的同步改善以及/或最佳协调。新的晶体管方向参量(parameter)LOD以及D可于一般组件仿真工具例如为SPICE仿真程序中作为如额外的设计决定参数,而藉由此方法,增强n型及p型金氧半晶体管的效能可藉由浅沟槽结构长度、宽度方向设计而优先调节施于栅极沟道上的x-y双轴应变。
图5A及图5B是分别显示如图3及图4中所述的晶体管电路布局(circuitlayout)的范例。图5A为相对图3的矩形有源区的晶体管上方平面图示,其中所显示的组件具有一大于0.60微米之宽度W与0.35微米的距离D。图5B为相对图4的“H”型有源区的晶体管上方平面图示,其显示一小于或等于0.60微米的宽度W与0.69微米的距离D。本实施例所提出的设计指导方针即对矩形有源区的用途较倾向于宽度距离W大于0.60微米,而对“H”型有源区的用途则倾向于宽度W小于或等于0.60微米,故设计指导方针是可根据一种特别技术方法的需求而有所变更。
现参照图6A至图6E,其显示一场效晶体管600在某些浅沟槽绝缘制造的工艺步骤中的剖面侧视图。图6A是显示一半导体硅基底601与数个隔离区域/自基底的上方表面开口的沟槽(trench)602a-b。基底材料可为典型用于生产集成电路的任何半导体,而基底的光阻遮蔽(photoresist masking)以及等离子蚀刻(plasma etching)等一般步骤则可用以建立浅沟槽绝缘的开口602a及602b。一种薄、热成长的氧化硅(silicon oxide)沟槽侧壁衬垫层(trenchliner layer)603可如图6B所示成长于该暴露的基底以及开口的沟槽上。
之后将该已开口的沟槽以一绝缘材料(isolation material)例如某些介电材料(dielectrical material)填充,而由该已完成的(即已填充、回火及平坦化)沟槽所产生的应变即定义为来自浅沟槽绝缘构造施加于晶体管有源区的净应变。根据本发明的揭露,该填充的沟槽应具备一种材料特征,即在相当的高温下具有一相对大的体积,并且当该组件冷却后其体积收缩(volumeshrinkage)至少达至0.5%;而在一些实施例中,其体积收缩较佳为大于5%,或甚至到8%,体积收缩是决定由浅沟槽绝缘构造施加于晶体管有源区的净应变。
一范例中,藉由一高密度等离子(high-density plasma;HDP)为基础的工艺沉积一结构性松散且具多孔性的氧化硅介电材料于基底上以及沟槽中,图6C为晶体管刚于高密度等离子多孔性氧化硅604沉积填充后的图示,该多孔性介电质是可决定更高程度于晶体管有源区上的浅沟槽绝缘张应变;而所附加的多孔性杂质可为大原子材料例如锗。于浅沟槽填充后,该结构是于炉管(furnace)中高温退火,其温度通常大于摄氏900度以稳定浅沟槽绝缘所沉积的介电质。贯穿退火程序的始末,当温度升高并且回复,氧化硅是历经了体积的膨胀以及收缩,使用该变异的多孔性以高密度等离子为基础的氧化硅是较一般填充材料可容许一较大量的收缩。
此多孔性氧化物自沉积后至热退火(thermal anneal)后其体积收缩一般将大于0.5%,而较高的收缩程度是产生一较高程度的内张应变(intrinsictensile strain)于填充材料(fill material)上,并反过来施加于晶体管的有源区上。
其它的氧化硅的沉积方法或可用于产生退火后欲表现出0.5%的体积收缩的多孔性氧化物,如利用四乙氧基硅烷(tetraethyl orthosilicate;TEOS)或硅烷(silane)为来源材料的低压化学气相沉积法(low pressure chemicalvapor deposition;LPCVD)或常压化学气相沉积法(atmospheric pressurechemical vapor deposition;APCVD)等方法可转用以生产具松散结构(loosestructure)多孔性氧化硅的沟槽填充介电质,而其它类似的方法例如次常压化学气相沉积法(semi-atmosphere chemical vapor deposition;SACVD)或旋涂式玻璃法(spin-on-glass;SOG)也可适用于产生所欲的结果。藉此方法所产生的沉积材料于高温时将具有一相对松散以及较大的体积,但当温度降低时,该氧化物例如为二氧化硅的体积将会收缩。
而任何其它介电材料、多孔性或非多孔性或具有至少20Mpa的内张应力(intrinsic tensile stress)的材料均可作为另一选择使用;而氮化硅(silicon nitride)、掺杂的氮化硅(doped silicon nitride)以及氮氧化硅(silicon oxynitride)则为此类材料的范例。产生此类介电薄膜的工艺可转为提供所欲的内应力程度,而该些工艺可以是以等离子为基础、或低压化学气相沉积法与常压化学气相沉积法;上述方法可调节施加于有源区上的x-y平面应变,因此可与一净平面应变(net planar strain)的调节相关联。
退火步骤后,浅沟槽绝缘构造是经由整体平坦化以移除过量的浅沟槽绝缘填充物,如此半导体基底的表面除该浅沟槽是中已由该平坦的介电质填充外,并无任何浅沟槽绝缘的填充物残留。化学机械研磨(chemical-mechanicalpolishing;CMP)的湿蚀刻(wet etch)化学以及/或干式等离子蚀刻(dryplasma etch)化学可用于沟槽的平坦化。图6D是阐述基底及浅沟槽绝缘结构于平坦化后的图示,此时,该基底是预备好形成场效晶体管于该已完成浅沟槽绝缘构造所限制的有源区中。
图7A至图7D为显示一场效晶体管700于形成浅沟槽绝缘结构后在某些导致应变的程序步骤中的一系列侧面剖视图。x-y双轴的应力调节的方法是如前所述,而某些其它则可藉由调节来自第三应变轴的应力以获得额外晶体管效能的提升。图7A显示一半导体硅基底701、已完成的浅沟槽绝缘结构702a与702b,以及具有栅极氧化层703与栅电极704的栅极,晶体管的侧壁侧壁衬垫层随后是沉积于晶体管上,接着再沉积侧壁间隔物(spacer layer)。
一用于侧壁间隔物706a-b的具有高内张力薄膜的较佳规格将导致一较佳的高张应变于栅极沟道上,一般侧壁间隔物706a-b是包含例如此实施例的氮化硅,但可为任何的介电材料;此实施例中,该侧壁间隔物的内应力程度是大于12Mpa。侧壁衬垫层705一般是包含氧化硅,但可为任何介电材料。在沉积晶体管侧壁侧壁衬垫层以及侧壁间隔物薄膜之后,该两层别之后是经一光阻图案遮蔽与蚀刻以形成直接毗连于栅极区侧壁的间隔物的结构。图7B是阐述侧壁衬垫705以及侧壁间隔物706a与706b于遮蔽以及蚀刻工艺完成后的图示。
图7C显示一具有源极708、漏极709以与栅极707的完整硅化区域的晶体管。侧壁间隔物706a-b形成后,基底的晶体管源极与漏极区708-709也已然形成,这些区域之后是经金属硅化以达减阻(resistance reduction)的作用,并于之后可进行接触连接(contact connection)。耐火的金属(refractorymetal)可于一般硅化程序中作为源极金属,而该金属材料可为一单一层别、单一元素、掺杂的金属(doped metal)或为一不同金属的复合迭(compositestack)。该完整的硅化程序是经由一些步骤执行,首先金属层沉积于晶体管上,接着通常(metal silicide)于一炉管或快速热处理反应室(rapid thermalprocess chamber)中高温退火以形成金属硅化物,而未反应的金属则之后利用一湿式蚀刻化学蚀刻该晶体管及其周围区域,仅留下该金属硅化层(metalsilicided layer)。
金属(或复合金属层)在硅化前以及退火后的体积收缩至少需为10%,以使源极与漏极区内已进行退火的硅化层(silicided layer)具有一大于20Mpa的内应力;而介于源极与漏极基底区域以及源极与漏极金属硅化区域的热膨胀失配(thermal expansion mismatch)于硅化物退火的操作下将大于0.5%以上。经使用如上述改变体积收缩以调整内应力程度的方法可提供沉积的金属所欲的内应力,施加于栅极沟道的张应变程度可经调节至晶体管驱动电流效能增强所需的程度。
图7D是显示接触蚀刻停止层710于图案遮蔽(pattern masking)以及蚀刻该层以产生接触开口(contact opening)前即沉积于整个晶体管的上方,而该接触蚀刻停止层是藉由一化学气相沉积步骤所生成。接触蚀刻停止层具有经修饰的内应力以施加一影响有源区净应变的应力,举例来说,如使用本发明前述的实施例的方法,经调节由此接触蚀刻停止层所引发的z方向的应力可改变施加于晶体管有源区与栅极沟道上的净应变,而调整层别的沉积步骤以修饰内应力以及/或使用额外的操作例如锗离子的植入(Germanium ionimplantation)以修饰该层别于法线z方向上的内应变可用以调节晶体管有源区的净应变。
侧壁间隔物及接触蚀刻停止层依不同程度可修饰该垂直于x-y平面方向上的应力,其可归类如一净垂直应力(net vertical strain);垂直与平面的净应力的结合称为全净应变(overall net strain),其最终是影响驱动电流的效能。晶体管的净应变调节可藉由对于产生应变的工艺的选择设计的方法完成,透过对某单位过程的内应力程度的规格与变动,可调节应变修饰的累积效应(cumulative effect)所欲的许多方向轴上达到该所合适的应变强度以增强晶体管效能至所需量及程度。
图8为说明一样本材料(sample material)的有源区原子结构800,除利用多种不同办法控制如上述中的应变,该应变也可藉由有源区中不同方向的原子距离(atomic distance)而控制。无论是n型或p型组件,其有源区中具有一为电洞或电子移动的载流(carrier flow),如图8所示,该载流是被视为具有一方向802。为将改善的驱动电流超越应力控制,一具有改善的驱动电流的p型半导体组件,其平行有源区宽度方向804的原子距离是大于平行有源区的长度方向806或平行于载流方向的原子距离;而相反地,一n型半导体组件,其有源区上较佳具有一平行载流方向或有源区长度方向806的原子距离大于垂直载流方向或平行有源区宽度方向的原子距离。有多种不同的方法可用以决定原子距离,例如,原子距离可藉由抽样一些晶格像(latticeimage)于一高分辨率穿透式电子显微镜(high resolution TransparentElecron Microscope)或经由绕射图案(diffraction pattern)的计算所决定。
本发明所揭露的实施例可适用于任何建造于半导体基底上的场效晶体管,藉由沉积或成长会产生应力的薄膜于晶体管上。
因此由以上可知根据本发明所揭露的组件构造及其制造方法是提供一可用以实现及解决改善互补型金氧半组件的载流子迁移以及驱动电流等问题的方法,甚至可同时改善互补型金属氧化半导体电路中的n型以及p型金氧半晶体管。注意本发明的揭露是同样提供一种利用现有工艺方法所制造的场效晶体管的大小及密度进一步收缩的解决办法,并且提供更简单的修饰净机械应力以及在栅极沟道上受到晶体管的浅沟槽结构、侧壁间隔物、硅化层以及接触蚀刻停止层的外型与性质所诱导的应变的方法,而依照本发明所揭露的组件制造方法是容易合并于当前现有的***。
虽然本发明已以较佳实施例揭露如上,然其并非用以限定本发明,任何熟习此技艺者,在不脱离本发明的精神和范围内,当可作些许的更动与润饰,因此本发明的保护范围当视所附的权利要求范围所界定者为准。
Claims (20)
1.一种制造具有改善的驱动电流的半导体组件的方法,该半导体组件具有形成于一有源区上的源极与漏极区,而该有源区的长度是不同于其宽度,其是包括下列步骤:
制造一或一个以上的以一隔离材料填满的隔离区围绕于该有源区;以及
将该隔离区退火;
其中该隔离材料于退火后至少具有0.5%的体积收缩,以及其中由该隔离材料的收缩所导致位于该有源区长的方向的应力是异于位于该有源区宽的方向由隔离材料收缩所导致的应力。
2.根据权利要求1所述的制造具有改善的驱动电流的半导体组件的方法,其中填充该隔离区的材料为一多孔性隔离材料。
3.根据权利要求2所述的制造具有改善的驱动电流的半导体组件的方法,其中该多孔性隔离材料是含锗材料。
4.根据权利要求1所述的制造具有改善的驱动电流的半导体组件的方法,其中该隔离材料具有一至少20Mpa的内张应力。
5.根据权利要求1所述的制造具有改善的驱动电流的半导体组件的方法,其中该隔离材料于退火程序后具有至少8%的体积收缩。
6.根据权利要求1所述的制造具有改善的驱动电流的半导体组件的方法,还包括:
形成一金属层覆盖于该源极或漏极区;以及
将覆盖于源极与漏极区的该金属层施以一退火程序以形成一硅化物,其中该硅化物具有一大于20Mpa的内应力。
7.根据权利要求6所述的制造具有改善的驱动电流的半导体组件的方法,其中该硅化物具有一大于10%的体积收缩。
8.根据权利要求6所述的制造具有改善的驱动电流的半导体组件的方法,其中介于该源极或漏极区与该硅化物间的一热膨胀失配于退火冷却后是大于0.5%。
9.根据权利要求1所述的制造具有改善的驱动电流的半导体组件的方法,还包括:
形成一栅电极覆盖于该有源区;以及
形成至少一介电质侧壁间隔物毗邻于该栅电极旁,其中该介电质侧壁间隔物是具有一大于12Mpa的内应力。
10.根据权利要求1所述的制造具有改善的驱动电流的半导体组件的方法,还包括:
形成一接触蚀刻停止层于组件上,其中该接触蚀刻停止层具有经修饰的内应力以施加一影响有源区净应变的应力;
其中该有源区包括一矩形有源区或一H型有源区,该矩形有源区的宽度距离大于0.60微米,而该H型有源区的宽度小于或等于0.60微米。
11.一种具有改善的驱动电流的半导体组件,其具有一有源区,且该有源区的长度是不同于其宽度,其包括:
一或一个以上以一预定隔离材料所填充的隔离区围绕于有源区旁;
其中该隔离材料于退火后至少具有0.5%的体积收缩,以及其中由该隔离材料的收缩所导致位于该有源区长的方向的应力是异于位于该有源区宽的方向由隔离材料收缩所导致的应力;
其中该半导体组件是金属氧化物半导体场效应晶体管。
12.根据权利要求11所述的具有改善的驱动电流的半导体组件,其中该隔离材料具有一至少20Mpa的内张应力。
13.根据权利要求11所述的具有改善的驱动电流的半导体组件,其中该隔离材料于退火程序后具有至少8%的体积收缩。
14.根据权利要求11所述的具有改善的驱动电流的半导体组件,还包括:
建立于有源区上的源极与漏极区;以及
一金属层,其覆盖于源极与漏极区上以形成一硅化物;
其中该有源区包括一矩形有源区或一H型有源区,该矩形有源区的宽度距离大于0.60微米,而该H型有源区的宽度小于或等于0.60微米。
15.根据权利要求14所述的具有改善的驱动电流的半导体组件,其中该硅化物具有一大于20Mpa的内应力。
16.根据权利要求14所述的具有改善的驱动电流的半导体组件,其中该硅化物具有一大于10%的体积收缩。
17.根据权利要求14所述的具有改善的驱动电流的半导体组件,其中介于源极或漏极区与硅化物间的一热膨胀失配于退火程序中是大于0.5%。
18.根据权利要求11所述的具有改善的驱动电流的半导体组件,还包括:
一栅电极,覆盖于有源区上;以及
至少一介电质侧壁间隔物于毗邻于该栅电极旁;
其中该侧壁间隔物具有调和平面垂直净应变的贡献以改善驱动电流,该有源区包括一矩形有源区或一H型有源区,该矩形有源区的宽度距离大于0.60微米,而该H型有源区的宽度小于或等于0.60微米。
19.根据权利要求18所述的具有改善的驱动电流的半导体组件,其中该介电层侧壁间隔物具有一大于12Mpa的内应力。
20.根据权利要求11所述的具有改善的驱动电流的半导体组件,还包括:
一接触蚀刻停止层覆盖于组件之上;
其中该接触蚀刻停止层具有调和平面垂直净应变的贡献以改善驱动电流,该有源区包括一矩形有源区或一H型有源区,该矩形有源区的宽度距离大于0.60微米,而该H型有源区的宽度小于或等于0.60微米。
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