CN1319372C - Method and device for sampling digital image - Google Patents

Abstract

The present invention provides a method and a device for sampling digital images in a lowered frequency mode. By processing on a time axis, the complexity of calculation and a device architecture is decreased, and the problems of a blurring effect and loss of information of a part of image caused by sampling in a lowered frequency mode are solved. Thus, the purpose of sampling digital image in a lowered frequency mode is obtained.

Description

Method and device for sampling digital image

Technical Field

The present invention relates to a method and apparatus for digital image down sampling, and more particularly, to a method and apparatus for down sampling by processing on a time axis.

Background

In a digital image system, the frame format conversion must be achieved by performing a corresponding conversion of the sampling frequency on the digital image data. For example, enlarging an image screen of 800 × 600 pixels to 1024 × 768 pixels corresponds to up-sampling image data in two dimensions, i.e., horizontally and vertically. Conversely, reducing an image frame of 1024 × 768 pixels to 800 × 600 pixels corresponds to down-sampling.

Two methods, namely a rejection method and an interpolation method, are common in the realization method of image frame reduction. The abandon method is to directly use the pixel closest to the down-sampling position in the original image frame as the result of down-sampling. The interpolation method is linear interpolation or interpolation by other numerical methods, and the result after down-sampling is obtained by calculating the pixel data of the original image at the position close to the down-sampling point. FIG. 1 is a schematic diagram of the result of down-sampling by the discard method and interpolation method (5: 4).

Interpolation down-sampling generally results in more accurate conversion, but still distorts the image information due to down-sampling. However, this method requires multiplication and addition of two or more pixel data in the original image, and requires storage of at least one time of pixel data in the original image, which is costly to implement. FIG. 2 is a circuit diagram of the interpolation method, which includes a vertical interpolation circuit 11 or (and) a horizontal interpolation circuit 12, a line data buffer 13, a down-sampling calculation control circuit 14 and a data buffer (FIFO) 15. Interpolation arithmetic circuits typically require multipliers and adders, but only adders with an accuracy of one-half.

The hardware for implementing the discard method is very simple, and fig. 3 is a circuit diagram of the discard method, which includes a down-sampling calculation control circuit 21, a vertical discard method selection output circuit 22 or (and) a horizontal discard method selection output circuit 23, and a data buffer 24. However, since the method directly takes out a portion of pixels with fixed positions from the original image as the result of down-sampling, some image information is directly discarded, and thus sufficient image information cannot be retained. For example, the T pattern in the original frame may become-or-I or even completely invisible depending on the frame position of the T pattern after the discarding down-sampling. Wherein,

because either down-sampling will cause information loss, it is impossible to retain the complete original image information; the purpose of down-sampling is to obtain the information corresponding to the image by the displayed content under the condition; thus, accurate interpolation is not necessarily meaningful to the user; while simple interpolation (1/2 accuracy) only sacrifices image quality to save multipliers, the hardware requirement is still large; but the rejection is unacceptable because the truly meaningful information may be rejected and not interpreted. It is therefore an object of the present invention to retain the information of the image even with the effect of simple interpolation (1/2 accuracy), using a discarding method.

Disclosure of Invention

In view of the above problems, it is an object of the present invention to provide a sampling method using the characteristics of the time axis.

Another objective of the present invention is to provide a method and apparatus for sampling digital images, which can retain the original graphic information after down-sampling by using the mechanism of initial offset.

It is another object of the present invention to provide an apparatus and method that can achieve the same cost as the rejection method, but after down-sampling, provide the user with enough image information to perform the interpretation, even a clearer image than the interpolation method for the user to interpret, or to approach the effect of the simple interpolation method (1/2 precision).

Conventional practice considers only a single picture, but does not consider from the point of view that the output image is a continuous picture. The invention provides a method for processing digital images of continuous pictures, for two adjacent pictures A and B, the information discarded by the abandon method on the picture A can be reproduced on the picture B, for a user, the complete image information can be still remained and can be interpreted, and on the hardware, the effect of frequency reduction sampling can be achieved only by adding an initial offset mechanism on a frequency reduction sampling calculation control circuit.

For the image of the characters, the more original and clear information is reserved, and the best interpretation effect can be obtained. The interpolation method can make the image fuzzified effect, but is not beneficial to the interpretation of the characters, more original clear information is reserved by using the method than by using the interpolation method, and a better effect is provided for the interpretation of the characters by a user. In addition to the original clear information, the setting of the initial offset value can be used to switch a smaller amount of different information of A/B pictures, thereby having a better reading effect on the character images.

On the other hand, for graphic images, accurate interpolation can achieve better results. The method can utilize the average of image information caused by visual persistence on a time axis to human eyes to make the effect of approximate simple interpolation (1/2 precision), and the effect is also achieved through the setting of an initial offset value.

To achieve the above object, the present invention provides a digital image down-sampling apparatus comprising: a first-in first-out type data buffer (FIFO) for storing the pixel data after down sampling to overcome the asynchronous read/write problem of data in real-time system; a down-sampling calculation control circuit for controlling whether to read the currently input pixel data into a data buffer (FIFO) as a result of down-sampling and the setting of the initial offset value. The purpose of digital image frequency-reducing sampling is achieved by the visual persistence effect through selecting and rejecting pixel data of different picture positions in continuous images.

The present invention will be described in detail below with reference to the accompanying drawings by way of specific examples.

Drawings

FIG. 1 is a diagram illustrating the conventional method of obtaining (5: 4) down-sampling results by the discard method and interpolation method;

FIG. 2 is a circuit schematic of a conventional interpolation method;

FIG. 3 is a circuit schematic of a conventional discard method;

FIG. 4 is a schematic diagram of an apparatus for down sampling a digital image according to the present invention;

FIG. 5 is a signal control diagram of an apparatus for digital image down-sampling according to the present invention;

FIGS. 6A and 6B are waveform diagrams of various output signals of the digital image;

FIG. 7 is a block diagram of an apparatus for down sampling digital images according to the present invention;

FIG. 8A is one embodiment of the parity picture determination logic of FIG. 7;

FIG. 8B is a diagram of the input-output waveforms of FIG. 8A;

FIG. 9 is a device architecture diagram of the pixel selection logic of FIG. 7;

FIGS. 10A-10C are conceptual diagrams of the present invention digital image down-sampling;

FIG. 11B is a block diagram of a preferred embodiment of the initial Offset selection accumulation register with Offset0 ═ 0 and Offset1 ═ 1 (M/N) — according to the present invention;

FIG. 11A is a waveform diagram of FIG. 11B;

FIG. 12 is a block diagram of a preferred embodiment of an 8-bit initial Offset selection accumulation register with digital Offset 0-1/4 and Offset 1-3/4 according to the present invention;

FIG. 13 is a table of simulated embodiment data for down sampling using the present invention.

The reference numbers illustrate: 40-digital image down-sampling device; 41-first-in first-out type data buffer; 42-down sampling computation control circuit; 71-three terminal input AND logic gate; 72-parity picture determination logic; 73, 74-pixel selection logic; 91-initial offset selection accumulation buffer; 92-an adder; 93-D type flip-flop; 94-a multiplexer; the 75-two terminals are input into an AND logic gate.

Detailed Description

The following describes the method and apparatus for down sampling a digital image according to the present invention with reference to the accompanying drawings.

FIG. 4 is a schematic diagram of an apparatus for down-sampling a digital image according to the present invention. As shown in the figure, the present invention successive digital image down-sampling device 40 comprises a first-in-first-out type data buffer (FIFO)41 and its down-sampling calculation control circuit 42. The read control logic of the control circuit 42 in the digital image down-sampling device 40 according to the present invention generates the Write Enable (WE) signal required by the data buffer 41 according to the image scaling, the pixel position and the image ordinal number, and writes the digital image pixel data into the data buffer 41. The pixel data read out from the data buffer 41 is the result of the continuous digital image down-sampling device 40 of the present invention.

FIG. 5 is a signal control diagram of an apparatus for digital image down-sampling according to the present invention. Examples of the types of input signals ICLK, IVS, IHS, IDEN, IDATA are shown in FIGS. 6A and 6B. The input image is composed of continuous pictures, and the minimum constitution unit of the pictures is a pixel, namely each point in the pictures. The pixels at the same vertical position are collected to form a horizontal pixel line, and then all the horizontal pixel lines at the vertical positions are collected to form a complete two-dimensional picture. In the signal waveforms shown in FIG. 6A and FIG. 6B, ICLK is the clock signal of the input image; the IVS is an initial signal of an input picture, and the period of the IVS signal is the period of a single picture in the image; IHS is a starting signal of a horizontal pixel line in an input picture; IDEN is a pixel data indication signal; when IDEN is 1, the IDATA signal sends out the pixel data of the picture by taking ICLK as a clock. In the above signals, IDATA, IHS and IDEN change synchronously with ICLK, IVS change synchronously with IHS, and ICLK, IVS, IHS and IDEN of all frames in the image maintain fixed relation. As shown in fig. 6A, the signals are the image data signals of one horizontal line in an image frame, when IDEN is 1(high), the IDATA signal clocks the pixel data signals of a single horizontal line of the image frame with ICLK, when the next IDEN is again 1, the signals are the pixel data signals of the next horizontal line, and when IDEN is 0(low), the signals are the intervals of the pixel data signals of each horizontal line. The signals shown in fig. 6B are schematic image data signals including a plurality of horizontal lines in a whole image frame, wherein the pixel data of the plurality of horizontal lines transmitted by each IDATA signal can display the whole image frame when the IVS is 0(low), and the interval between the image frames when the IVS is 1 (high).

The input signals OCLK and RE in fig. five are the clock signal (OCLK) and the Read Enable signal (Read Enable, RE) for the subsequent device (not shown in the figure) to Read out the down-sampling result from the data buffer 41; the output signal ODATA is the read down-sampling result.

The input signals HR and VR in fig. 5 are used to set the horizontal and vertical down-sampling ratios of the present device, each represented by N bits. For example, if N is 4 and a 20 × 9 frame is to be downsampled to a 16 × 8 frame, the ratio of horizontal and vertical downsampling is 5/4 and 9/8, respectively; the decimal part of the down sampling ratio is expressed by binary system to obtain HR (1/4 × 2)⁴＝[0100]，VR＝1/8*2⁴＝[0010]。

FIG. 7 is a block diagram of the digital image down-sampling apparatus according to the present invention. As shown, the read control logic of the downsampling calculation control circuit 42 includes: three-terminal input AND logic gate 71, parity judgment logic 72, pixel selection logic 73, horizontal pixel line selection logic 74, AND two-terminal input AND logic gate 75.

The three-terminal input AND logic gate 71 is configured to logically AND the selection signal NCR generated by the pixel selection logic 73 AND the horizontal pixel line selection logic 74 with the external input signal IDEN to serve as a Write Enable (WE) signal for storing the image data IDATA into the data buffer register 41. If the NCR output from the pixel selection logic 73 is 0(Low), it indicates that the pixel data is not to be written into the data buffer 41, i.e., the pixel is to be discarded. If the NCR output from the horizontal pixel line selection logic 74 is 0(Low), it indicates that the entire horizontal pixel data is not required to be written into the data buffer 41, i.e., the entire horizontal pixel is discarded. One embodiment of the parity determination logic 72 is a D-type flip-flop as shown in FIG. 8A. The D-type flip-flop, which uses the input frame start signal IVS as a trigger source, generates the SEL signal with a reverse phase change period equal to the frame period, as shown in FIG. 8B. The consecutive frames in the image can be divided into the odd frames and the even frames which are interlaced with each other according to the SEL signal.

The pixel selection logic 73 has the same structure as the horizontal pixel line selection logic 74, as shown in fig. 9. TRI is a trigger signal, when TRI changes from 0 to 1, the Sum output of the adder 92 is pushed into the N-bit initial offset selection accumulation buffer 91, and the overflow indicator of the N-bit adder 92 is pushed into the D-type flip-flop 93. The positive output Q of the D-type flip-flop 93 is used to control the value outputted from the multiplexer 94 to the adder to be 0 or INC; the negative output QB is the selection signal NCR, and when the NCR output is 0, the input image data IDATA is not written into the data buffer 41. When the reset signal RST is 1, the output of the flip-flop 93 is cleared (NCR ═ 1); when SEL is 0, the initial Offset selection accumulation buffer 91 is reset to Offset0, and when SEL is 1, the initial Offset selection accumulation buffer 91 is reset to Offset 1.

The concept of the present invention digital image down-sampling device 40 is shown in FIG. 10A, FIG. 10B1, FIG. 10B2, and FIG. 10C. FIG. 10A shows a 6 × 6 single frame in which the viewed image is composed of a continuous playback of the single frame. If the frame is down-sampled to 4 × 4, the down-conversion ratio is 3: 2, so the ideal down-sampling positions are 0, 1.5, 3, 4.5 of the horizontal and vertical positions. The dropping down sampling is performed by using the pixel data at frame positions 0, 1, 3, and 4 as the sampling result, as shown in FIG. 10B 1. It can be seen from the figure that the frequency reduction result achieved by the abandon method can not present the original graphic information on the screen. If the ideal frame downsampling positions 0, 1.5, 3, and 4.5 plus the offset 0.5 are 0.5, 2, 3.5, and 5, the pixel data at frame positions 0, 2, 3, and 5 are changed to the downsampling in the discarding method, as shown in FIG. 10B 2. Similar to FIG. 10B1, the down conversion result after adding the offset still cannot present the original graphic information on the screen. However, a careful examination will find that the original graphic information on the screen is distributed in the positions of fig. 10B1 and fig. 10B 2. That is, the sum of fig. 10B1 and fig. 10B2 includes all the original graphic information. If FIG. 10B1 and FIG. 10B2 were alternated as a result of down-sampling, the image would be the sum of FIG. 10B1 and FIG. 10B2 due to the persistence of vision effect of the human eye, as shown in FIG. 10C. The graphic information of the original picture is not rendered completely by the discarding method.

From the above results, the image is composed of consecutive frames, and the image can be regarded as an even frame and an odd frame interlaced with each other. According to the present invention, if M pixel data on horizontal or vertical lines in a digital image are to be down-sampled to N pixels (wherein M, N is a positive integer and N < M < 2N), the following is performed:

taking M/N X plus Offset0 as ideal down-sampling positions (X is an integer increasing sequence from 0 to N-1) for even pictures, and taking N pixels with positions equal to M/N X + Offset0 integer values from original M-point pixel data to form down-sampling results of the even pictures;

for odd pictures, M/N X plus Offset1 is used as an ideal down-sampling position, N pixels with the positions equal to (M/N X) + Offset1 integer values are extracted from the original M-point pixel data, and the down-sampling result of the odd pictures is formed.

The continuous image formed by the frequency-reducing sampling results of the even-numbered image and the odd-numbered image can completely present the graphic information of the original image due to the persistence effect of human eyes because the continuous image comprises all the pixel information in the original image.

The initial Offset selection accumulation buffer 91 is the mechanism of the Offset0 and Offset1, which can be designed differently for different purposes, and the invention proposes two concepts, one is the least picture change and the other is the effect of approaching the simple interpolation (1/2 precision).

The method aims at the least picture change, namely, the continuous images have the most same output points, so that the images have more stable and clearer effects, and the images of the characters can be more easily interpreted by users. The Offset is designed to be the difference between Offset0 and Offset1, which is equal to the remainder of the M/N down-conversion multiple, i.e., | Offset1-Offset0| (M/N) -1. Let Offset1 be (M/N) -1 if Offset is 0, which may be the case in the design of fig. 11A and 11B, an embodiment of the initial Offset selection accumulation register 91A, after RST is finished, creates a RST _ Pulse as in fig. 11A, and when RST is 1, Offset is cleared to 0; when SEL is equal to 1, RST-Pulse loads sum of the adder as Offset1, as shown in fig. 11B. Fig. 11B shows an embodiment of the initial Offset selection accumulation register 91a with Offset0 being 0 and Offset1 being (M/N) -1.

Another approach is to use the effect of simple interpolation (1/2 accuracy), which is based on the persistence of vision of continuous picture changes, as the average on the time axis, so that 1/2 accuracy interpolation can be achieved, and the image of the graph has better scale effect. From the down sampling of 1024 → 800 in the example of fig. 13, the same interpolation effect as 1/2 can be obtained with the settings of Offset 0-1/4 and Offset 1-3/4.

Let K * M/N X) * be the integer part of (M/N X), P be the fractional part of (M/N X),

if P is more than or equal to 0 and less than 1/4, $\mathrm{Effect}\_\mathrm{pixel}=\frac{K+\mathrm{<figure-callout\; id="2"\; label="K"\; filenames="C0213052300111.png"\; state="\{\{state\}\}">K</figure-callout>}}{2}=K;$

if 1/4 is not less than P < 3/4, $\mathrm{Effect}\_\mathrm{pixel}=\frac{K+(K+1)}{2}=K+0.5;$

if P is more than or equal to 3/4 and less than 1, $\mathrm{Effect}\_\mathrm{pixel}=\frac{(K+1)+(K+1)}{2}=K+1;$

fig. 12 shows another embodiment of an 8-bit initial Offset selection accumulation buffer 91b with Offset 0-1/4 and Offset 1-3/4, where the accumulation buffer 91b is selected by SEL to be reset to 01000000b (Offset 0-1/4) or 11000000b (Offset 3/4).

Minor changes and modifications may be made without departing from the spirit and scope of the invention.

Claims (14)

1. A digital image sampling device for receiving and sampling at least one input image, comprising:

a frame judgment logic circuit, which divides the input image into at least two groups of sampling images according to the change of the time axis; and the number of the first and second groups,

and the selecting logic circuit receives the distinguished sampling images output by the image judging logic circuit, performs pixel sampling by using a corresponding sampling point for each group of sampling images, and at least partially complements each other according to the corresponding sampling points selected by the different groups of sampling images.

2. The digital image sampling device of claim 1, further comprising:

a data buffer for receiving and temporarily storing the pixels sampled by the selection logic and outputting the pixels as sampled output image data, wherein the unselected pixels are discarded.

3. The digital image sampling device of claim 2, wherein the output image data after pixel sampling by the selection logic is at least divided into a first group of frames and a second group of frames, wherein the data discarded from the first group of frames is retained in the second group of frames following the first group of frames.

4. The digital image sampling device of claim 1 wherein the frame determination logic divides the input image into two groups of sampled images that are consecutive in time, and the selection logic selects the corresponding sampling points with offsets of 1/4 and 3/4 for the two groups of sampled images, respectively.

5. The digital image sampling device of claim 2, wherein the frame judgment logic divides the input image into two consecutive sets of sampled images, and the selection logic selects the corresponding sampling points for the two sets of sampled images with offsets of 0 and (M/N) -1, wherein M is the vertical/horizontal pixel of the input image and N is the vertical/horizontal pixel of the output image.

6. The digital image sampling device of claim 1, wherein the selection logic further comprises:

a horizontal pixel line selection logic circuit for sampling pixels of each horizontal pixel line according to the input sampling image and outputting a horizontal sampling signal; and

a vertical pixel selection logic circuit for performing vertical pixel sampling according to the input sampling image and outputting a vertical sampling signal;

wherein the horizontal sampling signal and the vertical sampling signal form a sampled output image data.

7. The digital image sampling device of claim 1, wherein the frame determination logic is a flip-flop.

8. A digital image sampling method is applied to receiving a continuous input image and sampling, and comprises the following steps:

generating a sampling signal, wherein the sampling signal comprises at least two groups of sampling models, and the continuous input images are divided into at least two groups of sampling images which are continuously replaced according to the change of a clock;

sampling, wherein each group of sampling images are respectively subjected to pixel sampling by a corresponding sampling point according to each group of sampling models of the sampling signals, and at least part of the corresponding sampling points selected according to the different groups of sampling images are complementary;

and outputting the image, namely outputting the continuous successive images sampled according to each group of sampling models into a sampled output image.

9. The method of claim 8 wherein unselected pixels are discarded.

10. The method of claim 8, wherein the output image after pixel sampling is divided into a first set of frames and a second set of frames alternately according to time variation, wherein the data discarded from the first set of frames is retained in the second set of frames following the first set of frames.

11. The method of claim 8, wherein the input image is divided into two groups of sampling images that are consecutive in time, and the corresponding sampling points of the two groups of sampling models corresponding to the input image are respectively 1/4 and 3/4.

12. The method of claim 8, wherein the input image is divided into two consecutive sets of sampling images, and the offsets of the corresponding sampling points selected by the two sets of sampling models corresponding to the two sets of sampling images are 0 and (M/N) -1, respectively, where M is a vertical/horizontal pixel of the input image and N is a vertical/horizontal pixel of the output image.

13. The digital image sampling method of claim 8, wherein the sampling step further comprises:

a horizontal pixel line selecting step, which is to sample the pixels of each horizontal pixel line according to the input sampling image and output a horizontal sampling signal; and

a vertical pixel selection step, which is to perform vertical pixel sampling according to the input sampling image and output a vertical sampling signal;

wherein the horizontal sampling signal and the vertical sampling signal form the output image after sampling.

14. The method according to claim 8, wherein the sampling patterns are partially complementary to each other.

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