CN1315194C - Silicon material on insulator with double-buried structure, its prepn. and usage - Google Patents
Silicon material on insulator with double-buried structure, its prepn. and usage Download PDFInfo
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- CN1315194C CN1315194C CNB2004100172396A CN200410017239A CN1315194C CN 1315194 C CN1315194 C CN 1315194C CN B2004100172396 A CNB2004100172396 A CN B2004100172396A CN 200410017239 A CN200410017239 A CN 200410017239A CN 1315194 C CN1315194 C CN 1315194C
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Abstract
The present invention relates to a silicon on insulator (SOI) material with a double buried structure, a preparation method thereof and a usage thereof, which is characterized in that the SOI material has the double buried structure, wherein the lower buried layer is a continuous insulating buried layer, and the upper buried layer is a discontinuous graphic insulating buried layer. The thickness of a top silicon layer in an SOI regional area on the upper buried layer is from 0.05 to 0.4 micrometer, and the thickness of a top silicon layer not in the SOI regional area of the upper buried layer is from 0.6 to 20 micrometers. The preparation method comprises: the SOI material with the continuous buried layer, which is prepared by the separation by implanted oxygen (SIMOX) technique is used as a substrate, and a thick monocrystal silicon layer is obtained by silicon vapor phase epitaxial growth, the discontinuous upper buried structure is obtained by the graphic SIMOX technique, or the continuous upper buried structure is changed into a discontinuous upper buried structure by the combination of the reaction ion etching technique and the silicon selectivity epitaxy technique. The prepared material provides a substrate material for the monolithic integration of an SOI photoelectronic device.
Description
Technical field
The present invention proposes a kind of silicon (SOI) material on the integrated insulator of photoelectron and method for preparing this material of being applied to,, belong to photoelectron integrated technology field for the integrated backing material that provides of the monolithic of SOI opto-electronic device.
Background technology
Silicon on the insulating barrier (SOI) material is a kind of important materials extremely likely in microelectronics field, can realize the insulation isolation of components and parts in the integrated circuit, fundamentally eliminate the parasitic latch-up in the body silicon CMOS circuit, thereby make chip have advantages such as high speed, low-power consumption, high temperature resistant, anti-irradiation, the SOI technology is known as " the si-substrate integrated circuit technology of 21 century " in the world.At optical communication field, because silicon is transparent in the optical communications wavelength scope, the refractive index difference of silicon and silicon dioxide is very big, so has advantages such as low-loss, compact conformation, birefringence effect be little based on the fiber waveguide device of SOI material.In addition, the SOI fiber waveguide device is compatible fully with ripe silicon microelectronic processing technology.Therefore, possess the SOI material of the excellent properties of photonic propulsion and electronics simultaneously, will become the main flow material of preparation photoelectron integration system chip (SOC).
The SOI technology is because its unique advantages has range of application very widely at microelectronic.Yet, the SOI device of different purposes or structure to the requirement of device layer thickness from tens nanometer to tens microns, have nothing in common with each other: for example high voltage down the SOI device of work need the SOI substrate of thick film silicon layer (＞1 μ m) usually, and the silicon film thickness of full-exhaustion SOI requirement on devices substrate even less than 0.1 μ m (www.SiGen.com; J.P. Courlene base, the silicon integrated circuit technology of SOI technology-21 century, Science Press, 1993).For SOI fiber waveguide devices such as SOI optical switch, SOI optical modulator, SOI array waveguide gratings, it then normally is substrate with the thick film SOI material, the requirement ducting layer is that the thickness of top silicon surface is several microns and even tens microns (Wei Hongzhen, Yu Jinzhong, Zhang Xiaofeng etc., the SOI integrated opto-electronic device, semiconductor optoelectronic, vol.22, no.1, p.7-11,2001; P.D.Trinh, S.Yegnanarayanan, B.Jalali, Silicon-on-insulator phased-arraywavelength multi/demultiplexer with extremely low-polarizationsensitivity, IEEE Photonics Technology Letters, vol.9, no.7, p.940-942,1997).Therefore, for the monolithic of realizing the SOI opto-electronic device integrated, it is very necessary that preparation can provide the SOI backing material of different-thickness top silicon surface simultaneously, to satisfy the requirement different to device layer thickness with the thin film SOI opto-electronic device of thick film SOI opto-electronic device.
The most ripe at present and commercial SOI material preparation technology, mainly contain silicon bonding and back of the body corrosion technology (BESOI, Bond and Etched back SOI) and inject oxygen isolation technology (SIMOX, Separationby IMplanted OXygen) two kinds of (J.P.Colinge, R.W.Bower, Silicon-on-insulator technology, MRS Bulletin, vol.23, no.12, p.13-15,1998; K.Izumi, History of SIMOX material, MRS Bulletin, vol.23, no.12, p.20-24,1998).The BESOI technology can prepare buried regions and all very thick thick film SOI material of top layer silicon thickness, but the reduction process behind the bonding causes the uniformity of its thickness to be difficult to be guaranteed, and promptly the planarization of the upper surface of top silicon surface is not ideal enough.The SIMOX technology can obtain high-quality thin film SOI material usually, its top layer silicon very thin thickness, generally be no more than 400nm (S.Bagchi, S.J.Krause, P.Roitman, Dose dependence of microstructural development of buriedoxide in oxygen implanted silicon-on-insulator material, AppliedPhysics Letters, vol.71, no.15, p.2136-2138,1997); But can increase top layer silicon thickness, thereby obtain the thick film SOI material that thickness is even, the interface is smooth by ripe growing epitaxial silicon technology.Because the waveguide interface that the waveguide surface out-of-flatness causes distortion scattering is the important light scattering mechanism of fiber waveguide device, so the fiber waveguide device based on BESOI SOI backing material has relatively large optical transmission loss usually, therefore the SOI backing material of SIMOX technology preparation is more suitable for being applied to the integrated (Marcuse of photoelectron comparatively speaking, D., Light transmission optics, Van NostrandReinhold, 1982; B.Jalali, S.Yegnanarayanan, T.Yoon, et al., Advancesin silicon-on-insulator optoelectronics, IEEE J.Selected Topics inQuantum Electronics, vol.4, no.6, p.938-947,1998).But, be that the top layer silicon thickness of SOI backing material of the single continuous buried structure of BESOI technology or SIMOX technology preparation all is single, can not satisfy the different requirements to device layer thickness when integrated of dissimilar SOI opto-electronic device monolithics simultaneously.
Deficiency in view of the SOI backing material of conventional structure, the inventor has proposed a kind of design of the SOI backing material with double-buried structure and the method for preparing this structural material, enable to provide simultaneously the top silicon surface of different-thickness, thereby can further satisfy the needs of SOI photoelectron integrated technology.
Summary of the invention
The present invention proposes a kind of silicon (SOI) material and manufacture method that is used on the integrated insulator of photoelectron, it is characterized in that: this material has double-buried structure, and wherein descending buried regions is continuous insulating buried layer, and last buried regions is discontinuous graphical insulating buried layer.The SOI regional area of buried regions on existing, the thickness of top layer silicon is 0.05～0.4 μ m, satisfies the requirement of partial SOI device to device layer thickness; And not having the SOI regional area of buried regions, the thickness of top layer silicon is 0.6～20 μ m, has both satisfied the requirement of partial SOI device to device layer thickness, also satisfies the requirement of SOI fiber waveguide device to ducting layer thickness simultaneously.The integrated backing material that provides of the monolithic of SOI opto-electronic device is provided the prepared SOI material of the present invention.
Purpose possibility of the present invention is by a kind of realization the in two kinds of methods narrating below.
The first kind of preparation method who specifically is used for the integrated SOI material of photoelectron is that the SOI material with continuous buried regions for preparing with notes oxygen (SIMOX) technology of isolating is a substrate, obtain thicker monocrystalline silicon layer through the silicon-phase epitaxial growth again, adopt graphical SIMOX technology to obtain the discontinuous buried structure of going up at last again, be applied to the integrated SOI material of photoelectron thereby prepared.Concrete processing step is as follows:
(1) vapor phase epitaxial growth monocrystalline silicon layer.
The SOI material with continuous buried regions that utilizes the preparation of SIMOX technology after process semiconductor standard cleaning technology is cleaned, is put into epitaxial furnace reative cell with substrate as substrate; In hydrogen atmosphere, the baking substrate is 0.5～1 hour in 1000～1200 ℃ temperature range, to remove the oxide layer of substrate surface, improves the substrate surface situation simultaneously; Adopt SiCl
4, SiHCl
3, SiH
2Cl
2, or SiH
4Carry out the monocrystalline silicon epitaxial growth as the silicon source, concrete course of reaction is as follows respectively:
Epitaxial growth temperature is 1000～1200 ℃, and deposition rate is 0.3～0.8 μ m/min, and the THICKNESS CONTROL of top layer silicon is in 0.6～20 mu m range.Can select suitable doped source to prepare dissimilar epitaxial loayer (n type, p type or intrinsic) during epitaxial growth as required, the outer time-delay of n type can feed the PH of dilution
3Or AsH
3, and preparation p type is delayed time outward, then feeds the B of dilution
2H
6
(2) photoetching ion injecting mask.
On the thick film SIMOX SOI material that obtains, adopt graphical SIMOX technology, can obtain the discontinuous graphical buried regions of going up, thereby realize that the SOI regional area with thicker top silicon surface that has the SOI regional area with thin top silicon surface of going up buried regions and do not have buried regions exists simultaneously on backing material.
In order to protect the material area that does not generate buried structure, need enough thick mask to stop the ion of injection.Growth or deposit the SiO that a layer thickness is 200～800nm on the thick film SIMOX SOI material that obtains
2, Si
3N
4, ganoine thin films such as polysilicon or metal are as the ion injecting mask, adopt photoetching process to obtain patterned ion implanted region territory on mask.
(3) low dose ion injects.
It is the key that forms the SOI material of high quality graphics buried regions that oxonium ion injects.Because being the oxonium ion part, graphical SIMOX technology injects, if adopt high dose injection technology parameter then will in material, produce a large amount of defectives, and cause material surface that very big difference in height (S.Bagchi is arranged, Y.Yu, M.Mendicino, et al., Defect analysis of patterned SOI material, IEEEInternational SOI Conference, p.121-122,1999).In order to obtain the SOI material of high quality graphics buried regions, need to adopt low dosage SIMOX technology, dosage and energy exist one to optimize relation simultaneously, to guarantee the quality (J.Margail of oxygen buried layer, J.Stoemenos, C.Jaussaud, et al., Reduced defect density in silicon-on-insulator structuresformed by oxygen implantation in two steps, Applied Physics Letters, vol.54, no.6, p.526-528,1989; M.Chen, X.Wang, J.Chen, et al., Does-energy match for the formation of high-integrity buried oxidelayers in low-dose separation-by-implantation-of-oxygen materials, Applied Physics Letters, vol.80, no.3, p.880-882,2002).When ion injected, underlayer temperature was 400～700 ℃, and oxonium ion energy (E) is 30～200keV, and optimizing dosage (D) accordingly is 1.5～7.0 * 10
17Cm
-2, the optimization formulate between dosage and energy is: D (10
17Cm
-2)=(0.035 ± 0.005) * E (keV).
The ion that injects removes O
+Can also be outward O
2 +, HO
+, H
2O
+, N
+, N
2 +Deng containing oxygen or nitrogenous ion to form SiO
2, Si
3N
4Perhaps their mixing buried regions.
(4) high annealing.
Finish after low dose ion injection and the removal mask, backing material is carried out high annealing, annealing temperature is 1200～1375 ℃, and annealing time is 1～24 hour, and annealing atmosphere is Ar and O
2Perhaps N
2With O
2Mist, O wherein
2Volume content can be 0.1%～20%.
In the zone that ion injects, formed continuous on buried structure, the thickness of top layer silicon is 0.05～0.4 μ m; And in the zone that no ion injects, not having buried structure, the thickness of top layer silicon still is 0.6～20 μ m.
Second kind of preparation method provided by the invention is that the SOI material with continuous buried regions for preparing with notes oxygen (SIMOX) technology of isolating is a substrate, the silicon-phase epitaxial growth obtains thicker monocrystalline silicon layer, adopt conventional SIMOX technology to obtain continuous last buried structure, association reaction ion etching technology and the silicon selective epitaxial process continuous situation that will go up buried structure changes into discontinuous again, through after the chemico-mechanical polishing, be applied to the integrated SOI material of photoelectron thereby prepared.Concrete processing step is as follows:
(1) vapor phase epitaxial growth monocrystalline silicon layer.
The SOI material with continuous buried regions that utilizes the preparation of SIMOX technology after process semiconductor standard cleaning technology is cleaned, is put into epitaxial furnace reative cell with substrate as substrate; In hydrogen atmosphere, the baking substrate is 0.5～1 hour in 1000～1200 ℃ temperature range, to remove the oxide layer of substrate surface, improves the substrate surface situation simultaneously; Adopt SiCl
4, SiHCl
3, SiH
2Cl
2, or SiH
4Carry out the monocrystalline silicon epitaxial growth as the silicon source, concrete course of reaction is as follows respectively:
Epitaxial growth temperature is 1000～1200 ℃, and deposition rate is 0.3～0.8 μ m/min, and the THICKNESS CONTROL of top layer silicon is in 0.6～20 mu m range.Can select suitable doped source to prepare dissimilar epitaxial loayer (n type, p type or intrinsic) during epitaxial growth as required, the outer time-delay of n type can feed the PH of dilution
3Or AsH
3, and preparation p type is delayed time outward, then feeds the B of dilution
2H
6
(2) ion injects.
When oxonium ion injected, underlayer temperature was 400～700 ℃, and the energy of oxonium ion is 30～300keV, and dosage is 1.0 * 10
17～2.5 * 10
18Cm
-2
The ion that injects removes O
+Can also be outward O
2 +, HO
+, H
2O
+, N
+, N
2 +Deng containing oxygen or nitrogenous ion to form SiO
2, Si
3N
4Perhaps their mixing buried regions.
(3) high annealing.
After finishing the ion injection, backing material is carried out high annealing, annealing temperature is 1200～1375 ℃, and annealing time is 1～24 hour, and annealing atmosphere is Ar and O
2Perhaps N
2With O
2Mist, O wherein
2Volume content can be 0.5%～80%.
Through behind the above processing step, formed upper and lower two-layer continuous buried structure in the backing material, the thickness of top layer silicon is 0.05～0.4 μ m.
(4) photoetching reactive ion etching mask.
In order to realize that the SOI regional area that has the SOI regional area of thin top silicon surface and have thicker top silicon surface exists simultaneously on backing material, can be by reactive ion etching technology again in conjunction with the silicon selective epitaxial process, with continuous the last buried structure of the backing material that obtained change into discontinuous graphical on buried structure.
To keep the material area of going up buried structure in order protecting, to need enough thick mask to avoid reactive ion etching.Growth or deposit the SiO that a layer thickness is 400～600nm on the SIMOX SOI material of the co-continuous buried structure that obtains
2Perhaps Si
3N
4Film adopts photoetching process to obtain patterned etch areas on mask as the reactive ion etching mask.
(5) reactive ion etching.
Utilize reactive ion etching technology to remove etch areas interior top silicon layer and last buried structure, etching depth is controlled at till the silicon fiml that partly enters under the buried structure, in order to avoid residual last buried regions influences next step monocrystalline silicon selective epitaxial.
(6) silicon selective epitaxial growth.
Etching mask is continued as the selective epitaxial mask, thereby all there is SiO in other region surface except that etch areas
2Perhaps Si
3N
4Film; When epitaxial growth monocrystalline silicon, at SiO
2Perhaps Si
3N
4Can't obtain monocrystalline silicon on the film, so the grooved area that only obtains of the growth district of monocrystalline silicon, thereby realize the selective epitaxial of monocrystalline silicon for reactive ion etching.The temperature of selective epitaxial growth is 850～1050 ℃, and epitaxially grown gas source is that silane adds an amount of hydrogen chloride gas or dichlorosilane, and the thickness of control epitaxial monocrystalline silicon is consistent with the material thickness that reactive ion etching is removed.
(7) chemico-mechanical polishing.
The substrate material surface out-of-flatness that selective epitaxial obtained is carried out chemico-mechanical polishing and is made its planarization.
The continuous buried structure of the selected SOI backing material that utilizes the preparation of SIMOX technology among two kinds of preparation methods of the silicon-on-insulator material of double-buried structure provided by the invention, promptly the continuous buried structure down of this material can be SiO
2Buried regions, Si
3N
4Buried regions or their mixing buried regions.The ion that injects removes O
+Can also be outward O
2 +, HO
+, H
2O
+, N
+, N
2 +Deng containing oxygen or nitrogenous ion to form SiO
2, Si
3N
4Perhaps their mixing buried regions.
The integrated backing material that provides of the monolithic of SOI opto-electronic device is provided the silicon-on-insulator material of double-buried structure provided by the invention
Description of drawings
Fig. 1 is the silicon-on-insulator material structural representation of double-buried structure provided by the invention.
Fig. 2 is the processing step schematic diagram that is applied to first kind of preparation method of the integrated SOI material of photoelectron.
(A) be schematic diagram with SOI backing material of continuous buried regions;
(B) be schematic diagram behind the silicon-phase epitaxial.
(C) for making the schematic diagram behind the mask by lithography;
(D) schematic diagram that injects for ion;
(E) be schematic diagram behind the high annealing;
Fig. 3 is the processing step schematic diagram that is applied to second kind of preparation method of the integrated SOI material of photoelectron.
(A) be the schematic diagram behind the SOI backing material silicon-phase epitaxial with continuous buried regions.
(B) schematic diagram that injects for ion;
(C) be schematic diagram behind the high annealing;
(D) for making the schematic diagram behind the mask by lithography;
(E) be schematic diagram after the reactive ion etching;
(F) be silicon selective epitaxial and through the schematic diagram after the chemico-mechanical polishing;
In the drawings, 1 for having the SOI backing material of continuous buried regions; 2 is the monocrystalline silicon layer of extension; 3 is the ion injecting mask; 4 is oxonium ion; 5 for being injected into the oxygen in the top layer silicon; 6 is the discontinuous graphical buried regions of going up; 7 is continuous following buried regions; 8 for existing the top layer silicon of the SOI regional area of going up buried regions; 9 is the top layer silicon that does not have the SOI regional area of buried regions; 10 is the continuous last buried regions that forms behind the high annealing; 11 is the reactive ion etching mask; 12 is the groove of reactive ion etching.
Embodiment
Below specifically introduce embodiment in conjunction with the accompanying drawings, helps to understand substantive distinguishing features of the present invention and obvious improvement and cut down, but enforcement of the present invention never only is confined to following examples.
Utilize the SiO that has of SIMOX technology preparation
2The SOI material of buried regions is as substrate continuously, and (Fig. 2 after A) process semiconductor standard cleaning technology is cleaned, puts into the epitaxial furnace reative cell with substrate; In hydrogen atmosphere, the baking substrate is 40 minutes under 1180 ℃ temperature, to remove the oxide layer of substrate surface, improves the substrate surface situation simultaneously then.Time-delay outside feeds B
2H
6As doped source, select SiCl for use
4Carry out the epitaxial growth of monocrystalline silicon P type as the silicon source, (Fig. 2, B), epitaxial growth temperature is 1180 ℃, and deposition rate is 0.7 μ m/min, and the thickness of delaying top layer silicon outward is 5 μ m.Oxidation growth one layer thickness is the Si of 200nm on the P type thick film SIMOX SOI material that obtains
3N
4Film adopts photoetching process to obtain patterned ion implanted region territory on mask as the ion injecting mask.(Fig. 2 C) adopts low dose ion to inject, and underlayer temperature is 650 ℃, and oxonium ion energy 160keV, dosage are 5.5 * 10
17Cm
-2(Fig. 2 D) removes after the mask, at Ar+1.5%O
2Atmosphere in backing material is carried out high annealing, annealing temperature is 1250 ℃, annealing time is 4 hours.Finally prepared and be applied to the integrated SOI material of photoelectron, (Fig. 2, E) its to have the top silicon surface thickness of the SOI regional area of going up buried regions be 0.2 μ m, and its top silicon surface thickness that does not have the SOI regional area of buried regions is 5 μ m.The material of preparation is as the integrated backing material of using of the monolithic of SOI opto-electronic device
Utilize the Si that has of SIMOX technology preparation
3N
4The SOI material of buried regions is as substrate continuously, and (Fig. 3 after A) process semiconductor standard cleaning technology is cleaned, puts into the epitaxial furnace reative cell with substrate; In hydrogen atmosphere, the baking substrate is 1 hour under 1130 ℃ temperature, to remove the oxide layer of substrate surface, improves the substrate surface situation simultaneously then.Adopt SiHCl
3Carry out the epitaxial growth of monocrystalline silicon intrinsic as the silicon source, epitaxial growth temperature is 1130 ℃, and deposition rate is 0.6 μ m/min, and the thickness of delaying top layer silicon outward is 10 μ m.Inject oxonium ion, underlayer temperature is 700 ℃, and the energy of oxonium ion is 180keV, and dosage is 1.8 * 10
18Cm
-2(Fig. 3, B).At Ar+4.0%O
2Atmosphere in backing material is carried out high annealing, annealing temperature is 1200 ℃, annealing time be 20 hours (Fig. 3, C).Deposition one layer thickness is the SiO of 500nm on the SIMOX SOI material of the co-continuous buried structure that obtains
2Film is as the reactive ion etching mask, adopt photoetching process on mask, obtains patterned etch areas (Fig. 3 D), utilizes reactive ion etching technology to remove etch areas interior top silicon layer and last buried structure, etching depth be 0.9 μ m (Fig. 3, E).Etching mask is continued to adopt SiH as the selective epitaxial mask
4: HCl=10: 1 mist carries out the monocrystalline silicon selective epitaxial growth as gas source, and epitaxial growth temperature is 950 ℃, the groove that the monocrystalline silicon growing zone obtains for reactive ion etching, and the thickness of epitaxial monocrystalline silicon also is 0.9 μ m.After finishing selective epitaxial, the substrate material surface that obtains is carried out chemico-mechanical polishing make its planarization.Finally prepared and be applied to the integrated SOI material of photoelectron (Fig. 3, F), its top silicon surface thickness of exist going up the SOI regional area of buried regions is 0.4 μ m, and its top silicon surface thickness that does not have the SOI regional area of buried regions is 10 μ m.(Fig. 1)
Claims (8)
1, a kind of silicon-on-insulator material of double-buried structure is characterized in that the following buried regions of two buried regions is continuous insulating buried layer, and last buried regions is discontinuous graphical insulating buried layer; The SOI regional area of buried regions on existing, the thickness of top layer silicon is 0.05～0.4 μ m, and does not have the SOI regional area of buried regions, the thickness of top layer silicon is 0.6～20 μ m.
2, the method for the silicon-on-insulator material of preparation a kind of double-buried structure as claimed in claim 1, it is characterized in that preparing the SOI material with continuous buried regions with notes oxygen isolation SIMOX technology is substrate, the silicon-phase epitaxial growth obtains monocrystalline silicon layer, adopt graphical injection oxygen isolation technology to obtain the discontinuous buried structure of going up again, be applied to the integrated SOI material of photoelectron thereby prepared; Processing step is as follows:
(1) vapor phase epitaxial growth monocrystalline silicon layer: the SOI material with continuous buried regions that utilizes the preparation of SIMOX technology after process semiconductor standard cleaning technology is cleaned, is put into epitaxial furnace reative cell with substrate as substrate; In hydrogen atmosphere, the baking substrate is 0.5～1 hour in 1000～1200 ℃ temperature range; Adopt SiCl
4, SiHCl
3, SiH
2Cl
2, or SiH
4Carry out the monocrystalline silicon epitaxial growth as the silicon source, epitaxial growth temperature is 1000～1200 ℃, and deposition rate is 0.3～0.8 μ m/min, and the THICKNESS CONTROL of top layer silicon is in 0.6～20 mu m range;
(2) photoetching ion injecting mask: growth or deposit the SiO that a layer thickness is 200～800nm on the thick film SIMOX SOI material that obtains
2, Si
3N
4, ganoine thin films such as polysilicon or metal are as the ion injecting mask, adopt photoetching process to obtain patterned ion implanted region territory on mask;
(3) low dose ion injects: adopt low dose ion to inject, underlayer temperature is 400～700 ℃, and the oxonium ion ENERGY E is 30～200keV, and corresponding dosage D is 1.5～7.0 * 10
17Cm
-2, the optimization formulate between dosage and energy is: D (10
17Cm
-2)=(0.035 ± 0.005) * E (keV);
(4) high annealing: remove after the mask, backing material is carried out high annealing, annealing temperature is 1200～1375 ℃, and annealing time is 1～24 hour, and annealing atmosphere is Ar and O
2Perhaps N
2With O
2Mist, O wherein
2Volume content be 0.1%～20%.
3, press the preparation method of the silicon-on-insulator material of the described double-buried structure of claim 2, it is characterized in that the ion-oxygen ion, the O that inject
2 +, HO
+, H
2O
+, N
+, N
2 +Contain oxygen or nitrogenous ion to form SiO
2, Si
3N
4Perhaps their mixing buried regions.
4, press the preparation method of the silicon-on-insulator material of the described double-buried structure of claim 2, it is characterized in that the continuous buried structure of the selected SOI backing material that utilizes the preparation of SIMOX technology, be SiO
2Buried regions, Si
3N
4Buried regions or their mixing buried regions.
5, the method for the silicon-on-insulator material of preparation a kind of double-buried structure as claimed in claim 1, it is characterized in that it being that the SOI material with continuous buried regions for preparing with notes oxygen isolation SIMOX technology is a substrate, the silicon-phase epitaxial growth obtains thicker monocrystalline silicon layer, adopt conventional SIMOX technology to obtain continuous last buried structure, association reaction ion etching technology and the silicon selective epitaxial process continuous situation that will go up buried structure changes into discontinuous again, through after the chemico-mechanical polishing, be applied to the integrated SOI material of photoelectron thereby prepared; Concrete processing step is:
(1) vapor phase epitaxial growth monocrystalline silicon layer: the SOI material with continuous buried regions that utilizes the preparation of SIMOX technology after process semiconductor standard cleaning technology is cleaned, is put into epitaxial furnace reative cell with substrate as substrate; In hydrogen atmosphere, the baking substrate is 0.5～1 hour in 1000～1200 ℃ temperature range; Adopt SiCl
4, SiHCl
3, SiH
2Cl
2, or SiH
4Carry out the monocrystalline silicon epitaxial growth as the silicon source, epitaxial growth temperature is 1000～1200 ℃, and deposition rate is 0.3～0.8 μ m/min, and the THICKNESS CONTROL of top layer silicon is in 0.6～20 mu m range;
(2) ion injects: when oxonium ion injected, underlayer temperature was 400～700 ℃, and the energy of oxonium ion is 30～300keV, and dosage is 1.0 * 10
17～2.5 * 10
18Cm
-2
(3) high annealing: backing material is carried out high annealing, and annealing temperature is 1200～1375 ℃, and annealing time is 1～24 hour, and annealing atmosphere is Ar and O
2Perhaps N
2With O
2Mist, O wherein
2Volume content be 0.5%～80%;
(4) photoetching reactive ion etching mask: growth or deposit the SiO that a layer thickness is 400～600nm on the SIMOX SOI material of the co-continuous buried structure that obtains
2Perhaps Si
3N
4Film adopts photoetching process to obtain patterned etch areas on mask as the reactive ion etching mask;
(5) reactive ion etching: utilize reactive ion etching technology to remove etch areas interior top silicon layer and last buried structure, etching depth is controlled at till the silicon fiml that partly enters under the buried structure, in order to avoid residual last buried regions influences next step monocrystalline silicon selective epitaxial;
(6) silicon selective epitaxial growth: etching mask is continued as the selective epitaxial mask, adopt method epitaxial growth monocrystalline silicon in the groove that reactive ion etching obtains of selective epitaxial; The temperature of selective epitaxial growth is 850～1050 ℃, and epitaxially grown gas source is that silane adds an amount of hydrogen chloride gas or dichlorosilane, and the thickness of control epitaxial monocrystalline silicon is consistent with the material thickness that reactive ion etching is removed;
(7) substrate material surface is carried out chemico-mechanical polishing and make its planarization.
6, press the preparation method of the silicon-on-insulator material of the described double-buried structure of claim 5, it is characterized in that the ion that injects is oxonium ion, O
2 +, HO
+, H
2O
+, N
+, N
2 +Contain oxygen or nitrogenous ion to form SiO
2, Si
3N
4Perhaps their mixing buried regions.
7, press the preparation method of the silicon-on-insulator material of the described double-buried structure of claim 5, it is characterized in that the continuous buried structure of the selected SOI backing material that utilizes the preparation of SIMOX technology, be SiO
2Buried regions, Si
3N
4Buried regions or their mixing buried regions.
8, the application of the silicon-on-insulator material of a kind of double-buried structure as claimed in claim 1 is characterized in that the single chip integrated backing material as the SOI opto-electronic device.
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| CN1315194C true CN1315194C (en) | 2007-05-09 |
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| CN100595928C (en) * | 2007-12-28 | 2010-03-24 | 上海新傲科技股份有限公司 | Semiconductor substrate, preparing technique and application in advanced three-dimensional electronic packaging |
| CN101621009B (en) * | 2008-07-02 | 2012-03-21 | 中国科学院微电子研究所 | Method for manufacturing body-contact structure of partially depleted SOI MOSFET |
| CN101604657B (en) * | 2009-06-19 | 2011-02-09 | 上海新傲科技股份有限公司 | Method for preparing silicon substrate on double-buried layer insulator |
| CN102130039B (en) * | 2010-12-27 | 2013-04-10 | 上海新傲科技股份有限公司 | Method for preparing semiconductor substrate with insulated buried layer by adopting gettering process |
| CN102130038A (en) * | 2010-12-27 | 2011-07-20 | 上海新傲科技股份有限公司 | Method for preparing silicon-on-insulator by ion implantation |
| JP5752264B2 (en) | 2010-12-27 | 2015-07-22 | シャンハイ シングイ テクノロジー カンパニー リミテッドＳｈａｎｇｈａｉ Ｓｉｍｇｕｉ Ｔｅｃｈｎｏｌｏｇｙ Ｃｏ．， Ｌｔｄ | Method for manufacturing a semiconductor substrate with an insulating layer by an impurity gettering process |
| CN102522416B (en) * | 2011-12-30 | 2014-10-01 | 中国科学院上海高等研究院 | Image sensor and production method thereof |
| CN102709296B (en) * | 2012-06-11 | 2014-12-03 | 中国电子科技集团公司第五十八研究所 | Silicon-on-insulator (SOI)/metal oxide semiconductor (MOS) device structure for connecting negative voltage on backgate through negative charge pump and manufacturing method |
| CN105097732A (en) * | 2014-05-22 | 2015-11-25 | 上海北京大学微电子研究院 | SOI high-voltage structure for reducing self-heating effect |
| CN112242342A (en) * | 2019-07-17 | 2021-01-19 | 上海新微技术研发中心有限公司 | Monocrystalline silicon local area SOI substrate, photoelectric device and preparation method |
| CN110890418B (en) * | 2019-12-02 | 2021-11-05 | 中国科学院上海微***与信息技术研究所 | Transistor structure with double buried oxide layers and preparation method thereof |
| CN113433618B (en) * | 2021-06-04 | 2022-07-08 | 华东师范大学 | On-chip integrated optical waveguide structure and preparation method thereof |
| CN114582859B (en) * | 2022-05-05 | 2022-07-05 | 微龛(广州)半导体有限公司 | ESD protection device structure for thin film transistor and preparation method |
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| CN1424754A (en) * | 2002-12-27 | 2003-06-18 | 中国科学院上海微***与信息技术研究所 | Preparation of silicon material on pattern dielectric body by dose-energy optimalized oxygen filling insulation |
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