CN1314204C - A method for reducing circuit power consumption in large scale integrated circuit - Google Patents
A method for reducing circuit power consumption in large scale integrated circuit Download PDFInfo
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- CN1314204C CN1314204C CNB2004100380098A CN200410038009A CN1314204C CN 1314204 C CN1314204 C CN 1314204C CN B2004100380098 A CNB2004100380098 A CN B2004100380098A CN 200410038009 A CN200410038009 A CN 200410038009A CN 1314204 C CN1314204 C CN 1314204C
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Abstract
The present invention relates to a method for reducing circuit power consumption in a large scale integrated circuit, which belongs to the technical field of the design of a CMOS integrated circuit. The method has the steps that firstly, the threshold value of each logic gate in a circuit is set into low threshold value, and then the delay time and the maximum buffering time of each logic gate is calculated; secondly, the buffering time of each logic gate in the circuit is redistributed according to the calculated results, so that the buffering time of the logic gates is larger than the delay inequality of the logic gates under the low threshold value and a known high threshold value; thirdly, the set high threshold value of the logic gates replaces the logic gate threshold value of which the buffering time is greater than the delay inequality of the logic gates in the logic gates. The method of the present invention greatly lowers the amount of logic gates with low threshold value under the premise of guaranteeing the functions of the circuit, and thus, lowers power consumption generated by leakage current in the circuit.
Description
Technical field
The present invention relates to a kind of method that reduces circuit power consumption in the large scale integrated circuit, belong to complementary metal oxide semiconductors (CMOS) (hereinafter to be referred as CMOS) integrated circuit (IC) design technical field.
Background technology
In large scale integrated circuit design, because integrated circuit technology has entered the sub-micro stage, the scale and the area of circuit are increasing, and speed is more and more faster, and the number of gate is also in very fast growth on the unit are.So power problems becomes a very important problem that faces in the circuit design.
In CMOS Logic Circuit Design in the past, two kinds of power consumptions of main consideration: first kind is in the circuit upset, sometime, the conducting simultaneously of N type field effect transistor (field effect transistor: Field Effect Transistor is hereinafter to be referred as FET) circuit and P type FET circuit produces through current and flows directly to ground from power supply; Second kind of power consumption is dynamic power consumption, and the power consumption that produces when promptly circuit when upset discharges and recharges the electric capacity of gate, interconnection line or other equipment is normally considered at most when circuit design, and its computing formula is:
For first kind of power consumption, people can suppress the generation of through current well by suitably designing cmos circuit.For dynamic power consumption, reduce supply voltage as can be seen by computing formula and can significantly reduce dynamic power consumption.Though the performance of circuit can reduce owing to the reduction of supply voltage in theory, but because the development of FET technology, the various parasitic capacitances of FET were also constantly reducing when threshold voltage reduced, make circuit performance not only not reduce, increase on the contrary, meanwhile the dynamic power consumption of circuit also becomes more and more lower.
But along with constantly dwindling of integrated circuit characteristic size, the threshold voltage of supply voltage and FET is all in continuous reduction.When the threshold voltage of FET reduces to a certain degree the time, the leakage current of FET will be exponential increase, and threshold voltage is low more, and the ratio of the power consumption that leakage current causes in the logic circuit chip is just big more.Because the speed of high threshold FET is slower than low threshold value FET, but its leakage current can reduce a lot, people have proposed to adopt the solution of dual threshold FET and many threshold values FET when circuit design, its basic thought is to select to use high threshold FET on non-critical path, thereby in the leakage current power consumption that guarantees to reduce under the prerequisite that circuit performance does not reduce circuit.But in the method in the past, determine which FET to adopt the strategy and the imperfection of high threshold, some has only considered the simplest gate---inverter (United States Patent (USP): US20030070147), and it is can not make full use of buffer time (slack time), thereby also little to the effect that reduces the leakage current power consumption.
Summary of the invention
The objective of the invention is to propose a kind of method that reduces circuit power consumption in the large scale integrated circuit, allow all gates all use the FET of low threshold value to realize, obtain circuit buffer time and time-delay situation by static timing analysis, guaranteeing under the correct prerequisite of sequential and function buffer time to be carried out reasonable distribution, make buffer time in the circuit many as far as possible greater than the gate of the delay inequality Δ D between self height thresholding, thus the power consumption that then FET of these gates is reduced leakage current to greatest extent and produced with high threshold FET replacement.
The method of circuit power consumption can have following two kinds in the reduction large scale integrated circuit that the present invention proposes, and first kind may further comprise the steps:
(1) threshold value with the gate in the circuit is made as low threshold value, calculates the time-delay and the maximum cushioning time of each gate;
(2) redistribute buffer time of each gate in the foregoing circuit according to the aforementioned calculation result, make buffer time of gate greater than the delay inequality under low thresholding and known high thresholding of this gate;
(3) replace in the above-mentioned gate buffer time greater than the gate threshold value of logic gate delay difference with the gate high threshold of setting.
The low threshold value of gate is 0.1 volt～0.3 volt in the circuit in the said method.
In the said method, the time-delay of each gate of counting circuit and maximum cushioning time method comprise the steps:
(1) circuit is mapped as an oriented weighted graph;
(2) obtain in the circuit each time-delay and maximum cushioning time with the static timing analysis method.The method that circuit is mapped as an oriented weighted graph is:
(1) gate in the circuit is mapped as the summit of oriented weighted graph;
(2) interconnection line in the circuit is mapped as the limit of oriented weighted graph;
(3) time-delay between the gate pin and Interconnect Delay are mapped as the weights on oriented weighted graph limit in the circuit.
Redistribute the method for the buffer time of each gate in the circuit in the said method, comprise the steps:
(1) establishes the circuit logic door N is arranged
LKind, N
L=1,2,3 ... N
L
(2) calculate the time-delay D of each gate when high threshold
H, the time-delay D when hanging down threshold value
L, the delay inequality that obtains between the height thresholding of this gate is Δ D=D
H-D
L
(3) according to maximum cushioning time of each gate, use genetic algorithm and linear programming method, make buffer time of gate as much as possible greater than himself delay inequality Δ D.
Second method may further comprise the steps:
(1) initiation threshold with gate in the circuit is made as low threshold value, time-delay in the counting circuit under the initial thresholding of gate and maximum cushioning time,
(2) establish above-mentioned low thresholding and gate and allow that m high thresholding arranged between the highest thresholding, from m high thresholding, choose a high thresholding Vi, redistribute buffer time of each gate in the foregoing circuit according to the aforementioned calculation result, make buffer time of gate greater than the delay inequality of gate under above-mentioned low thresholding and the high thresholding Vi that chooses;
(3) with buffer time in the above-mentioned gate in the above-mentioned high thresholding Vi replacement circuit of choosing of gate greater than the gate threshold value of logic gate delay difference;
(4) repeating step (2) and (3), m the power consumption of counting circuit under m high thresholding;
(5) choose lowest power consumption from an above-mentioned m power consumption, the corresponding high thresholding of power consumption is for optimizing high thresholding therewith;
(6) with the high thresholding in the high thresholding replacement step of above-mentioned optimization (2), repeating step (2), (3).
The method of circuit power consumption in the reduction large scale integrated circuit that the present invention proposes, under the prerequisite of the function that guarantees circuit, the reduction of amplitude peak the quantity of low Threshold Logic Gate, and then reduced the power consumption that leakage current produced in the circuit.
Description of drawings
Fig. 1 is the circuit diagram of the inventive method institute foundation.
Fig. 2 is the oriented weighted graph that is mapped to by circuit diagram.
Embodiment
The method of circuit power consumption can have two kinds in the reduction large scale integrated circuit that the present invention proposes.
First method at first is made as low threshold value with the threshold value of the gate in the circuit, calculates the time-delay and the maximum cushioning time of each gate; Redistribute buffer time of each gate in the foregoing circuit according to result of calculation, make buffer time of gate greater than the delay inequality under low thresholding and known high thresholding of this gate; Replace in the above-mentioned gate buffer time greater than the gate threshold value of logic gate delay difference with the gate high threshold of setting.
The low threshold value of the gate in the circuit in the said method is dual threshold that industrial quarters adopted or the lower threshold value in many threshold technologies, is generally between 0.1 volt to 0.3 volt.
In the said method, the time-delay of each gate of counting circuit and maximum cushioning time method at first are mapped as circuit an oriented weighted graph; Obtain in the circuit each time-delay and maximum cushioning time with the static timing analysis method.The method that circuit is mapped as an oriented weighted graph is the summit that the gate in the circuit is mapped as oriented weighted graph; Interconnection line in the circuit is mapped as the limit of oriented weighted graph; Time-delay in the circuit between the pin of gate and Interconnect Delay are mapped as the weights on oriented weighted graph limit.
Redistribute the method for the buffer time of each gate in the circuit in the said method, at first establishing the circuit logic door has N
LKind, N
L=1,2,3 ... N
LCalculate the time-delay D of each gate when high threshold
H, the time-delay D when hanging down threshold value
L, the delay inequality that obtains between the height thresholding of this gate is Δ D=D
H-D
LAccording to the maximum cushioning time of each gate, use genetic algorithm and linear programming method, make buffer time of gate as much as possible greater than himself delay inequality Δ D.
Second method, at first the initiation threshold with gate in the circuit is made as low threshold value, time-delay in the counting circuit under the initial thresholding of gate and maximum cushioning time, if above-mentioned low thresholding and gate allow that m high thresholding arranged between the highest thresholding, from m high thresholding, choose a high thresholding Vi, redistribute buffer time of each gate in the foregoing circuit according to the aforementioned calculation result, make buffer time of gate greater than the delay inequality of gate under above-mentioned low thresholding and the high thresholding Vi that chooses; With buffer time in the above-mentioned gate in the above-mentioned high thresholding Vi replacement circuit of choosing of gate greater than the gate threshold value of logic gate delay difference; M the power consumption of double counting circuit under m high thresholding; Choose lowest power consumption from m power consumption, the corresponding high thresholding of power consumption is for optimizing high thresholding therewith; With optimizing the high thresholding that high thresholding replaces first method, optimize circuit.
Below introduce principle of the present invention in detail:
The method of the reduction circuit power consumption that the present invention proposes, at first for a large-scale integrated circuit, it is abstracted into an oriented weighted graph G (V, A, c), gate in the circuit is mapped to the summit V of figure, and the interconnection line in the circuit is mapped to the limit A of figure, and the time-delay in the circuit between the pin of gate is mapped to the weights c on figure limit.For example Fig. 1 is the circuit diagram of the inventive method institute foundation, is abstracted into an oriented weighted graph shown in Figure 2 according to above-mentioned rule.
Then FET threshold value in all gates in the circuit is made as lowly, circuit is fastest like this, the leakage current maximum.Then use the algorithm of static timing analysis (STA) and figure to provide the time-delay and the maximum cushioning time of each gate in the circuit.
If high threshold is fixed during design circuit.Extract the species number N of gate in the circuit
L, N
L=1,2,3 ... N
LFor j kind gate (0＜i≤N
L), obtain the time-delay D when high threshold
H, the time-delay D when hanging down threshold value
L, and then the delay inequality that obtains between the height thresholding of j kind gate is Δ D=D
H-D
LAccording to the maximum cushioning time of each gate, use genetic algorithm and linear programming method, reasonably distribute the buffer time of each gate of initial circuit, make buffer time of gate as much as possible greater than himself Δ D, that is:
Wherein, slack_time (i) is the buffer time of i gate in the circuit, i
LBe the type of i gate, the number of the gate that N is in the circuit to be comprised, function lambda (i, i
L) be defined as:
Improve the threshold value of buffer time greater than the gate of self Δ D, thus the circuit after being optimized.
If the circuit high threshold is not determined during design, then at first need to determine the high threshold of the optimum of optimum power consumption correspondence by iteration.
At first the initiation threshold with the gate in the circuit is made as low threshold value, any one thresholding between low thresholding and the highest thresholding of gate is made as high thresholding Vi, i is any one in m the high thresholding, time-delay in the counting circuit under the initial thresholding of gate and maximum cushioning time.
Redistribute the buffer time of each gate in the foregoing circuit according to the aforementioned calculation result, make buffer time of gate greater than the delay inequality of this gate under the height thresholding, with the gate threshold value of above-mentioned gate buffer time in the above-mentioned high threshold replacement circuit of gate greater than the delay inequality of this gate.
Fix after the optimum high threshold, extract the species number N of gate in the circuit
L, N
L=1,2,3 ... N
LFor j kind gate (0＜i≤V
L), obtain the time-delay D when optimum high threshold
H, the time-delay D when hanging down threshold value
L, and then the delay inequality that obtains between the height thresholding of j kind gate is Δ D=D
H-D
LAccording to the maximum cushioning time of each gate, use genetic algorithm and linear programming method, reasonably distribute the buffer time of each gate of initial circuit, make buffer time of gate as much as possible greater than himself Δ D, that is:
Wherein, slack_time (i) is the buffer time of i gate in the circuit, i
LBe the type of i gate, the number of the gate that N is in the circuit to be comprised, function lambda (i, i
L) be defined as:
Improve the threshold value of buffer time greater than the gate of self Δ D, thus the circuit after being optimized.
Claims (6)
1, a kind of method that reduces circuit power consumption in the large scale integrated circuit is characterized in that this method may further comprise the steps:
(1) threshold value with the gate in the circuit is made as low threshold value, calculate the time-delay and the maximum cushioning time of each gate, computational methods are: at first circuit is mapped as an oriented weighted graph, its process comprises: (a) gate in the circuit is mapped as the summit of oriented weighted graph, (b) interconnection line in the circuit is mapped as the limit of oriented weighted graph, and (c) time-delay between the gate pin and Interconnect Delay are mapped as the weights on oriented weighted graph limit in the circuit; Obtain in the circuit each time-delay and maximum cushioning time then with the static timing analysis method;
(2) redistribute buffer time of each gate in the foregoing circuit according to the aforementioned calculation result, make buffer time of gate greater than the delay inequality under low thresholding and known high thresholding of this gate;
(3) replace in the above-mentioned gate buffer time greater than the gate threshold value of logic gate delay difference with the gate high threshold of setting.
2, the method for claim 1 is characterized in that the low threshold value of gate is 0.1 volt～0.3 volt in the wherein said circuit.
3, the method for claim 1 is characterized in that the wherein said method of redistributing the buffer time of each gate in the circuit, comprises the steps:
(1) establishes the circuit logic door N is arranged
LKind, N
L=1,2,3 ... N
L
(2) calculate the time-delay D of each gate when high threshold
H, the time-delay D when hanging down threshold value
L, the delay inequality that obtains between the height thresholding of this gate is Δ D=D
H-D
L
(3) according to maximum cushioning time of each gate, use genetic algorithm and linear programming method, make buffer time of gate as much as possible greater than himself delay inequality Δ D.
4, a kind of method that reduces circuit power consumption in the large scale integrated circuit is characterized in that this method may further comprise the steps:
(1) initiation threshold with gate in the circuit is made as low threshold value, time-delay in the counting circuit under the initial thresholding of gate and maximum cushioning time, computational methods are at first being mapped as circuit an oriented weighted graph, its process comprises that the gate in (a) circuit is mapped as the summit of oriented weighted graph, (b) interconnection line in the circuit is mapped as the limit of oriented weighted graph, and (c) time-delay between the gate pin and Interconnect Delay are mapped as the weights on oriented weighted graph limit in the circuit; Obtain in the circuit each time-delay and maximum cushioning time then with the static timing analysis method;
(2) establish above-mentioned low thresholding and gate and allow that m high thresholding arranged between the highest thresholding, from m high thresholding, choose a high thresholding Vi, redistribute buffer time of each gate in the foregoing circuit according to the aforementioned calculation result, make buffer time of gate greater than the delay inequality of gate under above-mentioned low thresholding and the high thresholding Vi that chooses;
(3) with buffer time in the above-mentioned gate in the above-mentioned high thresholding Vi replacement circuit of choosing of gate greater than the gate threshold value of logic gate delay difference;
(4) repeating step (2) and (3), m the power consumption of counting circuit under m high thresholding;
(5) choose lowest power consumption from an above-mentioned m power consumption, the corresponding high thresholding of power consumption is for optimizing high thresholding therewith;
(6) with the high thresholding in the high thresholding replacement step of above-mentioned optimization (2), repeating step (2), (3).
5, method as claimed in claim 4 is characterized in that the low threshold value of gate is 0.1 volt～0.3 volt in the wherein said circuit.
6, method as claimed in claim 4 is characterized in that the wherein said method of redistributing the buffer time of each gate in the circuit, comprises the steps:
(1) establishes the circuit logic door N is arranged
LKind, N
L=1,2,3 ... N
L
(2) calculate the time-delay D of each gate when high threshold
H, the time-delay D when hanging down threshold value
L, the delay inequality that obtains between the height thresholding of this gate is Δ D=D
H-D
L
(3) according to maximum cushioning time of each gate, use genetic algorithm and linear programming method, make buffer time of gate as much as possible greater than himself delay inequality Δ D.
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| CNB2004100380098A CN1314204C (en) | 2004-05-14 | 2004-05-14 | A method for reducing circuit power consumption in large scale integrated circuit |
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| CNB2004100380098A CN1314204C (en) | 2004-05-14 | 2004-05-14 | A method for reducing circuit power consumption in large scale integrated circuit |
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| CN1314204C true CN1314204C (en) | 2007-05-02 |
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| US8856564B2 (en) * | 2009-12-18 | 2014-10-07 | Intel Corporation | Method and apparatus for power profile shaping using time-interleaved voltage modulation |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6653868B2 (en) * | 2001-07-17 | 2003-11-25 | Renesas Technology Corporation | Semiconductor integrated circuit, method and program for designing the semiconductor integrated circuit |
| US6668358B2 (en) * | 2001-10-01 | 2003-12-23 | International Business Machines Corporation | Dual threshold gate array or standard cell power saving library circuits |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6653868B2 (en) * | 2001-07-17 | 2003-11-25 | Renesas Technology Corporation | Semiconductor integrated circuit, method and program for designing the semiconductor integrated circuit |
| US6668358B2 (en) * | 2001-10-01 | 2003-12-23 | International Business Machines Corporation | Dual threshold gate array or standard cell power saving library circuits |
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Granted publication date: 20070502 Termination date: 20140514 |