CN1312769C - Directly connected chip packaging structure - Google Patents

Directly connected chip packaging structure Download PDF

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Publication number
CN1312769C
CN1312769C CNB2004100660953A CN200410066095A CN1312769C CN 1312769 C CN1312769 C CN 1312769C CN B2004100660953 A CNB2004100660953 A CN B2004100660953A CN 200410066095 A CN200410066095 A CN 200410066095A CN 1312769 C CN1312769 C CN 1312769C
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CN
China
Prior art keywords
chip
lead frame
terminal pin
present
packaging structure
Prior art date
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Active
Application number
CNB2004100660953A
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Chinese (zh)
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CN1635635A (en
Inventor
梁志忠
刘道明
周正伟
茅礼卿
闻荣福
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changdian Technology Management Co ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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Priority to CNB2004100660953A priority Critical patent/CN1312769C/en
Publication of CN1635635A publication Critical patent/CN1635635A/en
Application granted granted Critical
Publication of CN1312769C publication Critical patent/CN1312769C/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

The present invention relates to a direct jointed chip packaging structure which belongs to the technical fields of a discrete semiconductor device and an integrated circuit. The present invention comprises a chip 1, a lead frame 3 and a plastic package body 5, wherein the chip 1 is arranged on a bearing base island 3.1 of the lead frame 3; the back side of the chip 1 is glued with the bearing base island 3.1 via glue 2. The present invention is characterized in that the end of a leading wire pin 3.2 of the lead frame 3 is made into a spring pin; the front surface of the chip 1 is directly welded with the end of the leading wire 3.2 via solder 4; the plastic package body packages the chip 1, the bearing base island 3.1 of the lead frame 3 and the end of the leading pin 3.2. The present invention can reduces impedance rate, enhance current flow and heat dissipation capacity and reduce cost, has no need of regulating parameter parts and has firm connection.

Description

The direct connection chip-packaging structure
Technical field:
The present invention relates to a kind of chip-packaging structure, especially relate to a kind of direct connection chip-packaging structure.Belong to discrete-semiconductor device and technical field of integrated circuits.
Background technology:
Traditional Chip Packaging indirect lead type structure generally commonly used.Its encapsulating structure is referring to Fig. 1～2: functional chip 1 ' place die-attach area 3 ' carrying Ji Dao on; chip 1 ' back side and die-attach area 3 ' carrying base island between with the conduction or non-conductive adhesive 2 ' binding; chip 1 ' front and die-attach area 3 ' terminal pin between with signal guidance gold thread 4 ' welding, then with protection with plastic packaging material body 5 ' with chip 1 ', die-attach area 3 ' carrying Ji Dao and signal guidance gold thread 4 ' encapsulation.It mainly has the following disadvantages:
1, adopt the spun gold welding between chip and the die-attach area, two pads are arranged, contact area is little.Shortcoming is: electrical impedance rate height, magnitude of current restriction is big and heat-sinking capability is relatively poor.
2, Ji Dao and spun gold routing pin weld all need silver-plated.Shortcoming is: silver-plated cost is higher, and because of silver-plated bad scrappage also higher.
3, the solder joint mode is that gold goal+heat+ultrasonic wave is pressed on the chip on the wafer.Shortcoming is that the parameter of every operation is limited bigger, and careless slightly chip surface and the chip internal circuit of promptly can causing is impaired, and promptly will remodify parameter because of different chip thickness and spun gold diameter difference.
Summary of the invention:
The objective of the invention is to overcome above-mentioned deficiency, the direct connection chip-packaging structure that provide a kind of and can lower the electrical impedance rate, improves the magnitude of current and heat-sinking capability, reduces cost, argument section can be adjusted, is connected firmly.
The object of the present invention is achieved like this: a kind of direct connection chip-packaging structure, comprise chip, lead frame and plastic packaging material body, chip places on the carrying Ji Dao of lead frame, chip back is glued with carrying Ji Dao, the terminal pin foot that is characterized in lead frame is made spring pin, chip front side and terminal pin foot directly weld with scolder, and the plastic packaging material body is with the carrying Ji Dao and the encapsulation of terminal pin foot of chip, lead frame.And because the terminal pin of flexible function, so can regulate the various pressure of sealing chip became uneven automatically.
Compare with traditional routing mode, the present invention has following advantage:
1, the direct and chip front side welding with terminal pin has only a pad, and contact area is big.Advantage is: lower the electrical impedance rate, improve the magnitude of current, improve heat-sinking capability.
2, the terminal pin weld need not silver-plated.Advantage is: fully save silver-plated and because of silver-plated bad cost.
3, the spring terminal pin gently be pressed in chip surface, and adopt slicker solder silver or tin cream to weld.Advantage: the one, because of the advantage of spring can overcome different chip thickness, and argument section almost can be adjusted; The 2nd, contact area is big, and it is strong to link fastness, is difficult for being separated.
Description of drawings:
Fig. 1 is general indirect lead type chip-packaging structure front elevation commonly used.
Fig. 2 is the A-A cut-away view of Fig. 1.
Fig. 3 is a direct connection chip-packaging structure front elevation of the present invention.
Fig. 4 is the B-B cut-away view of Fig. 3.
Embodiment:
As Fig. 3～4, the present invention is a kind of direct connection chip-packaging structure.Form with plastic packaging material body 5 with conduction or non-conductive adhesive 2, die-attach area 3 and protection by functional chip 1, chip and carrying Ji Dao binding.
Functional chip 1 places on the carrying base island 3.1 of die-attach area 3; link with conduction or non-conductive adhesive 2 between chip 1 back side and the basic island 3.1 of carrying; signal guidance terminal pin 3.2 foots of die-attach area 3 are made spring pin; terminal pin 3.2 foots offer connect apertures 3.2.1; terminal pin 3.2 foots place chip 1 front; terminal pin 3.2 foots and chip 1 link with slicker solder silver or tin cream 4 welding; brazing metal 4 infiltrates in the terminal pin 3.2 foot connect apertures 3.2.1; be the rivet-like left-hand thread with terminal pin 3.2 foots and be connected, use plastic packaging material body 5 with chip 1 with protection then; the carrying base island 3.1 of die-attach area 3 and the encapsulation of terminal pin 3.2 foots.

Claims (2)

1, a kind of direct connection chip-packaging structure, comprise chip (1), lead frame (3) and plastic packaging material body (5), chip (1) places on the carrying Ji Dao (3.1) of lead frame (3), chip (1) back side is bonding with glue (2) with carrying Ji Dao (3.1), terminal pin (3.2) foot that it is characterized in that lead frame (3) is made spring pin, chip (1) is positive directly to be welded with scolder (4) with terminal pin (3.2) foot, and plastic packaging material body (5) is with the carrying Ji Dao (3.1) and the encapsulation of terminal pin (3.2) foot of chip (1), lead frame (3).
2, a kind of direct connection chip-packaging structure according to claim 1, it is characterized in that terminal pin (3.2) foot offers connect apertures (3.2.1), scolder (4) infiltrates in the connect apertures (3.2.1), is the rivet-like left-hand thread with terminal pin (3.2) foot and is connected.
CNB2004100660953A 2004-12-17 2004-12-17 Directly connected chip packaging structure Active CN1312769C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNB2004100660953A CN1312769C (en) 2004-12-17 2004-12-17 Directly connected chip packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNB2004100660953A CN1312769C (en) 2004-12-17 2004-12-17 Directly connected chip packaging structure

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN 200710007838 Division CN1992253A (en) 2004-12-17 2004-12-17 Lead frame for direct connected chip packaging

Publications (2)

Publication Number Publication Date
CN1635635A CN1635635A (en) 2005-07-06
CN1312769C true CN1312769C (en) 2007-04-25

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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101958305B (en) * 2010-09-04 2012-09-19 江苏长电科技股份有限公司 Double-side graph chip forward module package structure and package method thereof
CN101958303B (en) * 2010-09-04 2012-09-05 江苏长电科技股份有限公司 Double-side graph chip forward single package structure and package method thereof
CN101927669B (en) * 2010-09-19 2012-08-15 广东省粤晶高科股份有限公司 Packaging process for tire pressure monitoring device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07297320A (en) * 1994-04-25 1995-11-10 Hitachi Cable Ltd Bga type semiconductor device
CN1162841A (en) * 1996-03-22 1997-10-22 株式会社日立制作所 Semiconductor device and manufacturing method thereof
CN1303520A (en) * 1998-05-29 2001-07-11 罗姆股份有限公司 Semiconductor device
CN2758976Y (en) * 2004-12-17 2006-02-15 江苏长电科技股份有限公司 Direct jointed chip packaging structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07297320A (en) * 1994-04-25 1995-11-10 Hitachi Cable Ltd Bga type semiconductor device
CN1162841A (en) * 1996-03-22 1997-10-22 株式会社日立制作所 Semiconductor device and manufacturing method thereof
CN1303520A (en) * 1998-05-29 2001-07-11 罗姆股份有限公司 Semiconductor device
CN2758976Y (en) * 2004-12-17 2006-02-15 江苏长电科技股份有限公司 Direct jointed chip packaging structure

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Effective date of registration: 20221115

Address after: 201201 room 111, building 1, No. 200, Jichuang Road, Pudong New Area, Shanghai

Patentee after: Changdian Technology Management Co.,Ltd.

Address before: 214431 No. 275 middle Binjiang Road, Jiangsu, Jiangyin

Patentee before: JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY Co.,Ltd.