CN1303498A - Method for accessing individually addressable and data processing system - Google Patents

Method for accessing individually addressable and data processing system Download PDF

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Publication number
CN1303498A
CN1303498A CN99806653A CN99806653A CN1303498A CN 1303498 A CN1303498 A CN 1303498A CN 99806653 A CN99806653 A CN 99806653A CN 99806653 A CN99806653 A CN 99806653A CN 1303498 A CN1303498 A CN 1303498A
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China
Prior art keywords
ram
data
address
adr
rom
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CN99806653A
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Chinese (zh)
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G·莫赛尔
R·比希勒
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Siemens AG
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Siemens AG
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)

Abstract

The invention relates to a method for accessing individually addressable data, wherein the address of a datum that is to be accessed is not transmitted to the corresponding electronic component via the address bus but it is detected instead by means of an algorithm in the component itself from an address of a datum which was accessed previously. This makes it possible to save energy when accessing data, which is particularly advantageous in the case of mobile electrical devices.

Description

The access method of single addressable data, data handling system
The present invention relates to the access method and the data handling system that is applicable to this method of single addressable data, they especially can be used for mobile electronic device.
Modern electronic equipment, particularly data processing equipment or communication facilities, the electronic component that all has control device and separately establish with it has the electronic component of single addressable data as storer or other.Like this, for example (,) storer can be divided into single addressable storage unit and wherein the storage data.For from these storage unit read datas or to they write datas, control device links to each other with storer with control bus by address bus, data bus.Here bus can be regarded as one group of line, a plurality of elements can be connected together by them.
In the beginning of each bus cycles, the address of respective memory unit is placed on the address bus.By control bus notice control device, carry out the data transmission (reading or writing) of what type.In addition, control bus is adjusted the accurate sequential in each bus cycles in each stage.Carry out intrinsic data transmission by data bus at last.Therefore, the line number of data bus has determined how many positions of transmission between control device and storer simultaneously.Such bus system is to be controlled by the countless logic gates of control device inside.
In addition, control device can have so-called register.It is a kind of storage unit, is positioned at control device inside and therefore need not just can reply by bus system transmission data.
In the method for being utilized the number bus system that the element of separately establishing with it (as memory set or associative memory group) is conducted interviews at present by the external control device, basic criterion is access speed or required time of storage unit access data.To this, before the each storage unit access of said method-wherein corresponding address being put on the address bus-being shown is reliably and fast, does not therefore need these access methods are made an amendment.
But show recently, especially to mobile electronic device such as mobile radio terminal device or portable computer, access speed not only, and also the electric consumption when single addressable data or storage unit carried out this type of visit has also all become a crucial criterion.
Therefore task of the present invention is, a kind of method and data handling system are provided, and available thus a kind of effective and reliable mode realizes the single addressable data access that economizes on electricity.
This task realizes by the characteristic of independent claims.Expansion scheme of the present invention illustrates in the dependent claims.
In view of the above, the present invention is based on following a kind of thought, that is: the address of the single addressable data that will visit of the next one is to try to achieve according to the address of the single addressable data of visiting in the past according to a kind of algorithm in respective element.
Can realize thus: at least under following situation, be that new address is can determine from old address according to a kind of algorithm the time, new address just needn't be sent to corresponding element by address bus, thereby need not to upload feed signals at address bus, thereby also just can save electric energy.
In the application's scope, electronic component can be regarded as each element that includes single addressable data, for example memory set, memory module, associative memory group or the like.
Expansion scheme regulation of the present invention, one or more addresses of the data that temporary transient storage was visited before one or more in control device and the element externally, whether measure in control device wants the address of visit data can obtain from a described temporary address by a kind of predetermined algorithm, and possible words, with relevant herein information or even the information of relevant used algorithm send element to.
By in the commonly used system of reality-in this system be at least temporarily alternately the commute nonvolatile memory the present invention that conducts interviews-introduce that becomes estranged can realize very large energy-efficient, this especially has bigger meaning to the mobile device such as mobile radio terminal device.
To do to describe further to the present invention by preferred embodiment below.Embodiment will describe by the accompanying drawing of listing below.
Wherein:
Fig. 1 is the synoptic diagram of a control device and two storeies,
The synoptic diagram that Fig. 2 carries out read access for the data of RAM storer that its address is temporarily stored.
Fig. 1 shows control device STE for example by the visit of number bus system to memory RAM, ROM.Owing to these storeies are to be in particular the mobile electronic device that is used for such as mobile radio terminal device to install, and therefore should be enough reliably with vibration resistance, so in storer, preferentially select easy mistake RAM memory RAM for use, or non-volatile ROM storer ROM, for example EPROM or short-access storage.
But the present invention also is applicable to other electronic component of visit.Like this, also need single addressable data are carried out read operation to the element inquiry clock that has the real-time clock function by the number bus system.At this, for clock is set, can carry out read access to hour information of another address, rather than to the read access of minute information or to the write access of hour information.The professional is familiar with many other elements that have single addressable data.
The present invention can be used among the element or a plurality of element of data handling system.Below tell about the application that the present invention visits the RAM storer earlier.
It for example can realize and be installed in the electronic equipment-have storer SPE_STE by processor or micromonitor system external control device STE-, and this storer can be realized by register or memory set, and one or more address AD R_RAM_ALT of the data DAT of the memory RAM of visiting before wherein storing.At this, " outside " refers to outside memory RAM, ROM.
Memory RAM, ROM are made up of a lot of storage unit, wherein can store single addressable data DAT, and it are assigned address AD R respectively.In addition, memory RAM has a memory block SPE_RAM, and the latter can realize by register, and wherein store the address AD R_RAM_ALT of one or more storage unit of visiting in the past.
Memory RAM, ROM can be divided into bigger or less sub-piece, and form corresponding addressing (1.1.1 1.1.2).
External control device STE and the memory RAM, the ROM that separately establish with it are connected to each other by bus system.Control bus C_BUS at first transmits the type that memory RAM, ROM are conducted interviews, and address bus ADR_BUS at first transmits the address AD R that wants visit data, and data bus D_BUS then transmits data between memory RAM, ROM and control device STE.
The address AD R_RAM_NEU of the next data DAT that will visit of control device STE mensuration whether try to achieve from data address ADR_RAM_ALT by available a kind of algorithm, and corresponding information being sent to corresponding memory RAM and control device STE_RAM by control bus C_BUS, this control device STE_RAM realizes in memory RAM place or its.
Have only a kind of algorithm in one embodiment, this algorithm not only is known to the control device STE, and the control device STE_RAM of memory RAM also knows.In this case, the control device STE_RAM address AD R_RAM_NEU that only is apprised of the data DAT that the next one will visit can obtain from the address AD R_RAM_ALT of the data DAT that visited in the past by this algorithm known.
A lot of algorithm ALGi are arranged in another embodiment, and these algorithms not only are known to the control device STE, and the control device STE_RAM of memory RAM also knows.In this case, control device STE_RAM also is apprised of in addition according to any this algorithm known and can determines the data DAT address AD R_RAM_NEU that the next one will be visited from the data DAT address AD R_RAM_ALT that visited in the past.The example of algorithm is more than one, increases the address when read access, and reduce the address when write access.
For other transfer algorithm type information, also can use the special combination of additional control line or existing control line.
The address AD R_RAM_NEU of the next data DAT that will visit is no longer by address bus ADR_BUS transmission, but in the control device STE_RAM of memory RAM, from address AD R_RAM_ALT, draw this address AD R_RAM_NEU with a kind of predetermined algorithm, and with it as reference address.At the storer place or the control device STE_RAM that realizes in it can realize that wherein, the address corresponding to storage unit not at the same level is divided by hardware counter or multistage hardware counter.
Because the frequent continuous memory cell (1.1.1 1.1.2 or 1.1.1 2.1.1) (for example linear code sequence in the program ROM) of visit,, needn't activate address bus driver, thereby can reduce power consumption so use in this case when of the present invention.This effect is especially obvious in the following cases, promptly in the data DAT process that two addresses link to each other in reference-to storage ROM, visit another memory RAM again, this be because, address wire often changes their state (0 to 1 or opposite) in this case, and this has exactly increased power consumption.
It is the data of the ADR_RAM_NEU flow graphs when carrying out read access that accompanying drawing 2 shows the address.
The accompanying drawing left side shows the method step of carrying out in control device STE side, and the right side shows the method step of carrying out in the control device STE_RAM side of memory RAM.
In order to carry out the instruction L (ADR_RAM_NEU) of the data DAT that reads on the address AD R_RAM_NEU, at first the address AD R_RAM_ALT with this address AD R_RAM_NEU and the data DAT that visited in the past compares VGL (ADR_RAM_NEU; ADR_RAM_ALT).Determine whether thus and can from old address ADR_RAM_ALT, try to achieve new address AD R_RAM_NEU with a kind of algorithm ALG.If not this situation, then pass through address bus ADR_BUS to memory RAM transfer address ADR_RAM_NEU.
Also can in a lot of pre-defined algorithm ALGi, obtain a kind of appropriate algorithm ALG1.The information that can from old address ADR_RAM_ALT, obtain with a kind of algorithm ALG about new address AD R_RAM_NEU, and if possible, also, all send the control device STE_RAM of memory RAM to by control bus C_BUS relevant for the type information of algorithm ALG1.There, new address AD R_RAM_NEU from old address ADR_RAM_ALT obtains ADR_RAM_NEU (ADR_RAM_ALT by algorithm ALG or the ALG1 that learns there; ALG1).
For example, from old address ADR_RAM_ALT, obtain new address AD R_RAM_NEU by increasing address value or increase part address value with hardware counter.The DAT data DAT (ADR_RAM_NEU) that has address AD R_RAM_NEU then is sent to external control device STE by data bus D_BUS, and can continue there to handle.
In one embodiment of the invention, this new address AD R_RAM_NEU of this moment is become old address ADR_RAM_ALT, it and is used as ADR_RAM_ALT and temporary transient storage not only in control device STE or affiliated storer SPE_STE in the SPE_RAM of the memory block of memory RAM.
Similar with the application of the invention described above visit RAM storer, also can conduct interviews to the ROM storer.At this moment, temporary transient address stored is expressed as ADR_ROM_ALT.
Tell about the present invention hereinafter with reference to a specific embodiment, wherein, the read operation of data to be processed (variable) in the RAM memory RAM is controlled by the program code among the ROM storer ROM.
The code sequence that begins from address AD R_ROM among the ROM storer ROM (this code sequence reads in some data division that begins from address AD R_RAM the RAM memory RAM) is by following formation:
1. fetch data from the address (instruction 1)
2. watch next data (instruction 2)
Must 3. these data also be read? (instruction 3)
4. if (instruction 4) again starts anew
This circulation constantly goes on, up to running through the data that last will be read.
To this, in classic method, following message is also transmitted by bus system:
Explain Data bus Address bus
Instruction fetch
1 from ROM Instruction 1 ?ADR_ROM
Fetch data 1 Data 1 ?ADR_RAM
Instruction fetch 2 from ROM Instruction 2 ?ADR_ROM+1
Instruction fetch 3 from ROM Instruction 3 ?ADR_ROM+2
Instruction fetch 4 from ROM Instruction 4 ?ADR_ROM+3
Instruction fetch 1 from ROM Instruction 1 ?ADR_ROM
Fetch data 2 Data 2 ?ADR_RAM+1
Instruction fetch 2 from ROM Instruction 2 ?ADR_ROM+1
Instruction fetch 3 from ROM Instruction 3 ?ADR_ROM+2
Instruction fetch 4 from ROM Instruction 4 ?ADR_ROM+3
Instruction fetch 1 from ROM Instruction 1 ?ADR_ROM
Fetch data 3 Data 2 ?ADR_RAM+2
Instruction fetch 2 from ROM Instruction 2 ?ADR_ROM+1
Instruction fetch 3 from ROM Instruction 3 ?ADR_ROM+2
Instruction fetch 4 from ROM Instruction 4 ?ADR_ROM+3
Instruction fetch 1 from ROM Instruction 1 ?ADR_ROM
Fetch data 4 Data 4 ?ADR_RAM+3
Instruction fetch 2 from ROM Instruction 2 ?ADR_ROM+1
Instruction fetch 3 from ROM Instruction 3 ?ADR_ROM+2
Instruction fetch 4 from ROM Instruction 4 ?ADR_ROM+3
Instruction fetch 1 from ROM Instruction 1 ?ADR_ROM
Fetch data 5 Data 5 ?ADR_RAM+4
● ● ?●
● ● ?●
● ● ?●
As seen, before and after visit RAM memory RAM, address bus changes its state probably on a lot of lines, and this has caused high power consumption.
In the method for the invention, wherein stored the address of last visit data in the RAM memory RAM, following message is also transmitted by bus system:
Explain Data bus Address bus
Instruction fetch
1 from ROM Instruction 1 ?ADR_ROM
Fetch data 1 Data 1 ?ADR_RAM
Instruction fetch 2 from ROM Instruction 2 ?ADR_ROM+1
Instruction fetch 3 from ROM Instruction 3 ?ADR_ROM+2
Instruction fetch 4 from ROM Instruction 4 ?ADR_ROM+3
Instruction fetch 1 from ROM Instruction 1 ?ADR_ROM
Fetch data 2 Data 2
Instruction fetch 2 from ROM Instruction 2 ?ADR_ROM+1
Instruction fetch 3 from ROM Instruction 3 ?ADR_ROM+2
Instruction fetch 4 from ROM Instruction 4 ?ADR_ROM+3
Instruction fetch 1 from ROM Instruction 1 ?ADR_ROM
Fetch data 3 Data 2
Instruction fetch 2 from ROM Instruction 2 ?ADR_ROM+1
Instruction fetch 3 from ROM Instruction 3 ?ADR_ROM+2
Instruction fetch 4 from ROM Instruction 4 ?ADR_ROM+3
Instruction fetch 1 from ROM Instruction 1 ?ADR_ROM
Fetch data 4 Data 4
Instruction fetch 2 from ROM Instruction 2 ?ADR_ROM+1
Instruction fetch 3 from ROM Instruction 3 ?ADR_ROM+2
Instruction fetch 4 from ROM Instruction 4 ?ADR_ROM+3
Instruction fetch 1 from ROM Instruction 1 ?ADR_ROM
Fetch data 5 Data 5
● ● ?●
● ● ?●
● ● ?●
Because the data address that will visit in the RAM storer is arranged by ascending order, therefore according to the present invention not needs always data address is placed on the address bus.Change owing on address bus, only need to implement less state, so just caused the electric energy saving.
In the method for the invention, the address of in RAM memory RAM and ROM storer ROM, all having stored last visit data wherein, following message is also transmitted by bus system:
Explain Data bus Address bus
Instruction fetch
1 from ROM Instruction 1 ?ADR_ROM
Fetch data 1 Data 1 ?ADR_RAM
Instruction fetch 2 from ROM Instruction 2
Instruction fetch 3 from ROM Instruction 3
Instruction fetch 4 from ROM Instruction 4
Instruction fetch 1 from ROM Instruction 1 ?ADR_ROM
Fetch data 2 Data 2
Instruction fetch 2 from ROM Instruction 2
Instruction fetch 3 from ROM Instruction 3
Instruction fetch 4 from ROM Instruction 4
Instruction fetch 1 from ROM Instruction 1 ?ADR_ROM
Fetch data 3 Data 2
Instruction fetch 2 from ROM Instruction 2
Instruction fetch 3 from ROM Instruction 3
Instruction fetch 4 from ROM Instruction 4
Instruction fetch 1 from ROM Instruction 1 ?ADR_ROM
Fetch data 4 Data 4
Instruction fetch 2 from ROM Instruction 2
Instruction fetch 3 from ROM Instruction 3
Instruction fetch 4 from ROM Instruction 4
Instruction fetch 1 from ROM Instruction 1 ?ADR_ROM
Fetch data 5 Data 5
● ● ?●
● ● ?●
● ● ?●
As seen, on address wire, produce state variation still less this moment.According to the algorithm that uses and the control signal of employing, also can make by address wire transmission address still less.

Claims (11)

  1. Control device (STE) use the number bus system visit a plurality of electronic components (ROM, the method for single addressable data (DAT) RAM), wherein
    The address (ADR_RAM_NEU) of data that will be accessed in the element (RAM) draws the address (ADR_RAM_ALT) according to a kind of algorithm accessed data before this element (RAM) in this element (RAM).
  2. 2. according to the process of claim 1 wherein
    A) in an element (RAM), temporarily stored the address (ADR_RAM_ALT) of this element data of accessed mistake before at least one at least,
    B) in control device (STE), temporarily stored the address (ADR_RAM_ALT) of the data of accessed mistake before at least one of at least one element (RAM),
    C) whether the address (ADR_RAM_NEU) of the data that measuring element (RAM) will be accessed can obtain from temporary address (ADR_RAM_ALT) by a kind of predetermined algorithm, and
    D) possible words are notified to element (RAM) with this information.
  3. 3. the method that one of requires according to aforesaid right, wherein
    If need visit data address (ADR_RAM_NEU) can according to a kind of pre-defined algorithm from before obtain the address (ADR_RAM_ALT) of accessed data, then the address (ADR_RAM_NEU) of the data of this need visit is not to transmit to element (RAM) from control device (STE), but the address (ADR_RAM_NEU) of the data of should need visiting in element (RAM) according to a kind of pre-defined algorithm from before draw the address (ADR_RAM_ALT) of data of accessed mistake.
  4. 4. the method that one of requires according to aforesaid right, wherein
    Information about the algorithm (ALG_1) that will use is notified to element (RAM).
  5. 5. the method that one of requires according to aforesaid right, wherein
    At least be at least temporary transient access element (RAM, part ROM) alternately.
  6. 6. the method that one of requires according to aforesaid right, wherein
    The part of described at least element relates to volatile storage (RAM) and nonvolatile memory (ROM).
  7. 7. data handling system, it has
    A) control device (STE), it has memory block (SPE_STE), in order to the address (ADR_RAM_ALT) of the data of accessed mistake before at least one of at least one element of temporary transient storage (RAM),
    B) have a plurality of electronic component (ROM of single addressable data (DAT), RAM), wherein, at least one element (RAM) has memory block (SPE_RAM), address (ADR_RAM_ALT) in order to temporary transient storage data of accessed mistake before at least one, and also have integrated control device (STE_RAM), be used for according to a kind of pre-defined algorithm from temporary address (ADR_RAM_ALT), draw the data that will visit address (ADR_RAM_NEU) and
    C) number bus system, control device (STE) visits single addressable data (DAT) with it, and be used for from control device (STE) to the relevant information of using algorithm of at least one element (RAM) transmission, so that the address (ADR_RAM_NEU) of the definite data that will visit.
  8. 8. according to the data handling system of claim 7,
    Wherein, if need visit data address (ADR_RAM_NEU) can according to a kind of pre-defined algorithm from before obtain the address (ADR_RAM_ALT) of accessed data, then the address (ADR_RAM_NEU) of the data of this need visit is not to transmit to element (RAM) from control device (STE), but the address (ADR_RAM_NEU) of the data of should need visiting in element (RAM) according to a kind of pre-defined algorithm from before draw the address (ADR_RAM_ALT) of data of accessed mistake.
  9. 9. according to the data handling system of one of claim 7 to 8,
    Wherein, the information of the relevant algorithm that will use also transmits at least one element (RAM) from control device (STE) by the number bus system.
  10. 10. according to the data handling system of one of claim 7 to 9,
    Wherein, be at least temporary transient access element (RAM, part ROM) alternately at least.
  11. 11. according to the data handling system of one of claim 7 to 10,
    Wherein, the part of described at least element relates to volatile storage (RAM) and nonvolatile memory (ROM).
CN99806653A 1998-05-26 1999-05-03 Method for accessing individually addressable and data processing system Pending CN1303498A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19823478.3 1998-05-26
DE19823478 1998-05-26

Publications (1)

Publication Number Publication Date
CN1303498A true CN1303498A (en) 2001-07-11

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EP (1) EP1080412A1 (en)
CN (1) CN1303498A (en)
WO (1) WO1999061988A1 (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4479178A (en) * 1981-07-02 1984-10-23 Texas Instruments Incorporated Quadruply time-multiplex information bus
WO1995028677A1 (en) * 1994-04-13 1995-10-26 Ericsson Inc. Efficient addressing of large memories

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EP1080412A1 (en) 2001-03-07
WO1999061988A1 (en) 1999-12-02

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