CN1303055A - System control chip with multiplex pattern bus structure and computer system - Google Patents
System control chip with multiplex pattern bus structure and computer system Download PDFInfo
- Publication number
- CN1303055A CN1303055A CN 00100069 CN00100069A CN1303055A CN 1303055 A CN1303055 A CN 1303055A CN 00100069 CN00100069 CN 00100069 CN 00100069 A CN00100069 A CN 00100069A CN 1303055 A CN1303055 A CN 1303055A
- Authority
- CN
- China
- Prior art keywords
- bus
- control chip
- external
- system control
- graphics
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Image Generation (AREA)
Abstract
A system control chip and computer system with multiplex graphics bus structure is disclosed. Said system control chip can be connected to an external graphic processor via an external graphics bus (AGP, for example) and has an internal graphic process which is connected to the extended part of external graphics bus in the system control chip via a virtual graphics bus. A snooper is included to snoop the requests between graphic processor and system so as to integrate the resources of external and internal graphics processors.
Description
The present invention relates to a kind of system control chip and computer system with multiplex pattern bus structure, particularly at the state-of-the-art graphics/video bus structure of present PC---advanced graphics port (Advanced Graphic Port, be called for short AGP) bus, a kind of improved digraph shape bus structure are proposed, under the situation that does not change former bus protocol, improve the performance of graphics/video subsystem and fully use resource in the different video processor.
In the traditional electrical brain system, general figures subsystem (graphic subsystem) is that the mode with plug-in unit (plug-in card) is connected in the system.The approach that graphics subsystem is connected computer system is realized by expansion bus (expansion bus), and change gradually along with the improvement of technology, from early stage industry standard architecture (Industry Standard Architecture, be called for short ISA) bus, to peripheral cell interface (Peripheral Component Interface, be called for short PCI) bus, to up-to-date AGP bus.
Fig. 1 is that content shown in Figure 1 is the situation that graphics subsystem passes through the AGP bus connection system in order to the system block diagram of graphics subsystem relevant position in computer architecture in the explanation prior art.As shown in the figure, north bridge (north bridge) system control chip 12 is the main medium that system data or control information are transmitted, it utilizes inner cpu interface circuit, memorizer control circuit, pci controller and AGP controller respectively, is connected with graphics/video subsystem 20 with CPU10, storer 16, south bridge (southbridge) system control chip 14 in the computer.The AGP bussing technique mainly is the graphics/video bus of being dominated by Intel Company, and based on original PIC bus protocol and signal, so as to (dedicated), the passage of pipeline system (pipelined) that a special use is provided, make the figure speed-up chip can obtain various graph datas in the system storage apace.As for its detailed technology part, can be not repeated with reference to the relevant specification recommendation of AGP herein.As for the situation of pci bus and isa bus, then be pci bus or the isa bus (being connected in south bridge system control chip 14) that utilizes among the figure, its main difference is that PCI or isa bus are not man-to-man private buss, and its operating clock is also far below AGP.
Though the traditional graph subsystem mostly is to utilize the plug-in unit mode to be connected in system, but had at present more and more computers be with graphics subsystem integrated (integrated) to motherboard, be called comprehensive graphics subsystem (integrated graphic subsystem).For example shown in Figure 2, it is the system block diagram of computer system when adopting comprehensive graphics subsystem, wherein represents with same-sign with Fig. 1 components identical.Comprehensive figure/the subsystem of video of 22 expressions, it places within the motherboard 1, and is connected north bridge system control chip 12 by the bus on the motherboard (for example pci bus).In addition, CPU10, storer 16 and south bridge system control chip 14 on motherboard 1, have also been comprised.
Graphics subsystem is integrated in the same motherboard, its advantage is arranged in practice really.Yet,, just be faced with sizable problem when the user wants to upgrade for graphic system.Because graphics subsystem is to be integrated in the motherboard, exactly graph processing chips and frame buffer (frame buffer) are freezed on motherboard from the viewpoint of hardware, can't separate separately and upgrade.Therefore, the mode of the comprehensive graphics subsystem of upgrading has only the whole motherboard of replacing, and cost is very high.Another kind of mode is inserted the graphics/video subsystem 24 of plug-in unit by AGP slot (slot), then as shown in Figure 2 to improve the graphics process performance.By this mode,, also can reach the purpose that improves the graphics process performance even under the situation of not changing whole motherboard.
System architecture shown in Figure 2 no doubt can solve the problem of comprehensive figure sub-system staging, but this structure is also drawn the problem of another wasting of resources.Comprehensive figure/subsystem of video 22 on motherboard 1 or be connected in the graphics/video subsystem 24 of system by AGP slot (slot) all is the process chip of independent operation, has the resource of many repetitions between the two, makes that naturally system cost increases.
Therefore, fundamental purpose of the present invention is to provide a kind of system control chip and computer system with multiplex pattern bus structure, can be when utilizing the AGP slot to improve the graphics process performance, also can carry out effective configuration, to reach best system performance for the resource of two circular subsystems.
According to above-mentioned purpose, the present invention proposes a kind of system control chip with multiplex pattern bus, and this system control chip is arranged in the computer system, as the processing enter of each interelement exchanges data.System control chip has an external graphics bus, can be used for connecting an external graphics processor.Inside at system control chip then comprises an internal graphics processor, and it utilizes a virtual pattern bus, is connected in the extension of external graphics bus in system control chip; One multiplexer group places between external graphics bus and the virtual pattern bus, is used for controlling the data transfer between other parts of external graphics processor, internal graphics processor and system control chip; An and audiomonitor (snooper), be mounted on the extension of external graphics bus in system control chip, can be used for monitoring the externally request between other parts of graphic process unit, internal graphics processor and system control chip, so as to the resource of integrated external graphics processor and above-mentioned internal graphics processor.
In addition, above-mentioned external graphics bus then can be the AGP bus, and the virtual pattern bus then is to remove the signal section of sideband signal in the advanced graphics port bus and in order to the control signal of control multiplexer group.When system start-up, external graphics processor and internal graphics processor can be disposed at different system resources space, for example the external graphics processor still then disposes the address space of a PCI for AGP external device internal graphics processor.And audiomonitor just can determine it to transmit target according to transmitting the desired system resources space of data.By this mode, graphics process resources effective configuration be can be obtained according to audiomonitor information, realized by internal graphics processor.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and in conjunction with the accompanying drawings, be described in detail below:
Fig. 1 represents to comprise in the known technology system block diagram of the computer architecture of graphics subsystem.
Fig. 2 represents to comprise in the known technology system block diagram of the computer architecture of comprehensive graphics subsystem.
Fig. 3 represents to have in the embodiment of the invention the bus-structured computer system block scheme of multiplex (MUX) AGP.
Fig. 4 represents the more detailed block diagram in the north bridge system control chip in the embodiment of the invention.
Fig. 5 represents the circuit diagram that multiplexer group deal with data is transmitted in the embodiment of the invention.
Fig. 6 represents the circuit diagram that the processing of multiplexer group is asked and control signal is transmitted in the embodiment of the invention.
Multiplex pattern bus structure of the present invention mainly is a Virtual Access Gateway P (Virtual AGP in the parallel connection in traditional AGP, be called for short VAGP) the inner comprehensive graphics subsystem of connection, and check all transmission data or requests by the audiomonitor (snooper) that is arranged in the north bridge System on Chip/SoC, so as to the resource in effective configuring external and the enclose pattern subsystem.Following conjunction with figs. describes content of the present invention in detail with an embodiment.Be to be the frame mode of example explanation multiplex pattern bus with AGP in this embodiment, but go for equally on other different figures or video bus.
Fig. 3 represents to have in the present embodiment computer system block scheme of multiplex (MUX) AGP video structure, wherein then represents with same-sign with Fig. 1 components identical.As shown in Figure 3, north bridge system control chip 30 inside have comprehensive figure/subsystem of video 32, are the motherboard integrated structure, and comprehensive figure/subsystem of video 32 then can be connected to outside display 36, and the demonstration of video/graphics is provided.In the present embodiment on the structure most important characteristics be that promptly comprehensive figure/subsystem of video 32 is to utilize general AGP bus in Virtual Access Gateway P (the being VAGP) parallel connection.The effect of this VAGP bus can be described below: when not having plug-in unit on the general AGP slot when figure auxiliary processor 34 (that is do not have among Fig. 3), then the VAGP bus then can be finished the work by standard A GP bus protocol, enjoy whole bandwidth of AGP bus, and comprehensive figure/subsystem of video 32 is promptly the same with graphics subsystem on traditional AGP, has the relational graph data of the passage access memory 16 of dedicated stream line type; When on general AGP slot, inserting other graphics video plug-in units (when being connected figure auxiliary processor 34 as shown in Figure 3) then VAGP and AGP share same bandwidth, and by audiomonitor and moderator (aftermentioned) in the bus structure, can effectively use the resource of inside and outside graph processing chips, make the graphics process performance improve.
Below describe AGP and VAGP bus structure in the present embodiment in detail.Fig. 4 represents the part more detailed block diagram in the north bridge system control chip 30 in the present embodiment, wherein only indicates relevant AGP and VAGP bus structure part.As shown in the figure, in north bridge system control chip 30, comprise impact damper 301, scrambler 303, multiplexer group 305, audiomonitor 307 and multiplexer 309.Impact damper 301 and scrambler 303 are the original elements of general AGP interface circuit, and the function of data buffering and signal encoding is provided.
Audiomonitor 307 is mounted on the extension of AGP in north bridge system control chip 30, that is between impact damper 301 and the scrambler 303, be used between other parts (for example cpu interface circuit, Memory Controller or the like) of the figure auxiliary processor 34 on the AGP, comprehensive figure/subsystem of video 32 on the VAGP and north bridge system control chip 30, monitoring the request of transmitting to each other.The mode of monitoring mainly is by figure auxiliary processor 34 is disposed at different system spaces with comprehensive figure/subsystem of video 32.When not inserting plug-in unit on the AGP slot, system can be set at the AGP space with comprehensive figure/subsystem of video 32 when starting, and the mode of operation of therefore comprehensive figure/subsystem of video 32 is used all resources of AGP just as the plug-in unit that inserts the AGP slot.And when system when start the time detects the AGP slot insertion plug-in unit (figure auxiliary processor 34) is arranged, then comprehensive figure/subsystem of video 32 is disposed in the untapped PCII/O address space.Audiomonitor 307 can check just whether request (request) belongs to inner comprehensive figure/subsystem of video 32 handled requests in the outlet in snoop procedure; If, then produce the HIT/MISS signal by multiplexer 309, make the data in the impact damper 301 not pass through general AGP line concentration, and handled by comprehensive figure/subsystem of video 32.By such mechanism, the purpose that can make comprehensive figure/subsystem of video 32 in north bridge system control chip 30 and outside figure auxiliary processor 34 accomplish resource sharing.
The effect of multiplexer group 305 is between AGP, VAGP and other parts of system, the transmission of control data, request and control signal.Multiplexer group 305 is made of each multiplexer.Fig. 5 represents the circuit diagram that deal with data (data) is transmitted in the multiplexer group 305 in the present embodiment.For doing explanation, must dispose the multiplexer of relative populations in content shown in Figure 5 according to the actual data signal line at general exchanges data.In Fig. 5, the 323rd, input FIFO (First-In-First-Out) register, the 321st, the output fifo register is as the input-output register of comprehensive figure/subsystem of video 32 on the VAGP bus.34 of figure auxiliary processors are by general AGP bus inputoutput data.Multiplexer M1 is used for controlling the data that AGP and VAGP are sent to system; Multiplexer M2 is used for control system and AGP to be sent to the data of VAGP.Multiplexer M3 is used for control system and AGP to be sent to the data of VAGP.Fig. 6 represents that multiplexer group 305 is being handled the circuit diagram that request (request) and control signal are transmitted in the present embodiment.Similarly, the request from figure auxiliary processor 34 and comprehensive figure/subsystem of video 32 can optionally enter system by the multiplexer M4 that is controlled by moderator (arbiter) 322.Moderator 322 can be arranged in comprehensive figure/subsystem of video 32 or the audiomonitor 307.By the effect of this multiplexer group 305, can control data and the transmission direction of request.
Comprehensive figure/subsystem of video 32 in north bridge system control chip 30 is because can monitoring and the resource of managing internal and outside relevant graphics process, so the particular importance that seems on function.Figure auxiliary processor 24 in the present embodiment for example, its purpose is to improve the performance that or several special patterns are handled, and for example how much (geometry) graphics process, front end figures produce (front rendering), the rear end figures produce (back rendering) or the like.Therefore, comprehensive figure/subsystem of video 32 can be with in addition pipelining (pipelined) of graphic presentation work, so that being separated into several sons handles, transfers to figure auxiliary processor 24 or comprehensive figure/subsystem of video 32 is handled respectively itself.For instance, figure auxiliary processor 24 can be geometric figure processor (geometry processor), then plays the part of the role that figure produces engine (rendering engine) at comprehensive figure/subsystem of video 32; Also can produce processing and produce processing as the rear end figure as the front end figure by figure auxiliary processor 24 by comprehensive figure/subsystem of video 32; Even both all can be as the usefulness of figure generation, and be connected respectively to outside display.Therefore utilize the bus structure of present embodiment, can make graphics processing pipelineization, and its performance is improved.
In addition, though in the present embodiment comprehensive figure/subsystem of video 32 is placed system control chip, with its extraction and place on the motherboard, also can reach the purpose of the system integration, above-mentioned illustrated bus structure also can be suitable equally.In addition, because the destination that audiomonitor needs the time judgment data to transmit, therefore the write buffer (write buffer) (not shown) at AGP then can increase one or more layers extra data buffer, so as to remedying the needed processing time of above-mentioned monitoring.Because AGP is a pipeline processes, the data buffer that is increased can't have influence on system performance.
The advantage of the present invention's multiplex pattern bus structure is:
1. can fully use resource in the computer system.Because AGP and VAGP multiplex's bus structure are provided, so when improving system's figure handling property, do not need to change whole motherboard, can utilize on the AGP expansion slot the new graphic process unit of adding to implement, effectively reduce the system upgrade cost.Graphic process unit on AGP and VAGP then can be shared its internal resource, and for example storer makes system data more effectively to be used.
2. the graphics subsystem in motherboard or the system control chip can utilize the auxiliary pattern processor on the AGP expansion slot, strengthens the graphics process performance.For example, on the AGP expansion slot, can add the very strong geometric figure processor of performance, make general personal computer system also can be increased to the graphics/video handling property of ASs such as graphics workstation.
3. the pipelining of graphics process can be guided out different graphics process hardware design modes, the graphics system of a complexity can be divided into several simple graphics process squares, the graphic process unit of transferring on AGP and the VAGP is carried out work respectively, so the user can optionally set up graphics system.
Though the present invention with a preferred embodiment openly as above; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the invention; can do suitable change and retouching, so protection scope of the present invention should be as the criterion with the scope that claim was defined.
Claims (13)
1. system control chip with multiplex pattern bus, this system control chip has an external graphics bus, and in order to connect an external graphics processor, it comprises:
Internal graphics processor, it utilizes a virtual pattern bus, is connected in the extension of said external graphics bus in the said system control chip; And
Audiomonitor, be mounted on the extension of said external graphics bus in the said system control chip, in order to monitor the request between said external graphic process unit, above-mentioned internal graphics processor and other parts of said system control chip, so as to the resource of integrated said external graphic process unit and above-mentioned internal graphics processor.
2. the system as claimed in claim 1 control chip, wherein also comprise a multiplexer group, place between the extension and above-mentioned virtual pattern bus of said external graphics bus in the said system control chip, in order to the data transfer between control said external graphic process unit, above-mentioned internal graphics processor and other parts of said system control chip.
3. the system as claimed in claim 1 control chip, wherein the said external graphic process unit is disposed at different system resources space with above-mentioned internal graphics processor, above-mentioned audiomonitor determines it to transmit target then according to transmitting the desired system resources space of data.
4. the system as claimed in claim 1 control chip, wherein the said external graphics bus is advanced graphics port (AGP) bus, above-mentioned virtual pattern bus then in the advanced graphics port in order to control the control signal of above-mentioned multiplexer group.
5. system control chip with multiplex pattern bus, it has an external graphics bus, in order to connect an external graphics processor; The said system control chip provides a virtual pattern bus, places internal graphics processor on the motherboard in order to connection, and wherein the said external graphics bus is connected in the said system control chip with above-mentioned virtual pattern bus; Has an audiomonitor in the said system control chip, be mounted on the extension of said external graphics bus in the said system control chip, in order to monitor the request between said external graphic process unit, above-mentioned internal graphics processor and other parts of said system control chip, so as to the resource of integrated said external graphic process unit and above-mentioned internal graphics processor.
6. system control chip as claimed in claim 5, wherein also comprise a multiplexer group, place between the extension and above-mentioned virtual pattern bus of said external graphics bus in the said system control chip, in order to the data transfer between control said external graphic process unit, above-mentioned internal graphics processor and other parts of said system control chip.
7. system control chip as claimed in claim 5, wherein the said external graphic process unit is disposed at different system resources space with above-mentioned internal graphics processor, above-mentioned audiomonitor determines it to transmit target then according to transmitting the desired system resources space of data.
8. system control chip as claimed in claim 5, wherein the said external graphics bus is advanced graphics port (AGP) bus, above-mentioned virtual pattern bus then is in order to control the control signal of above-mentioned multiplexer group in the advanced graphics port bus.
9. computer system with multiplex pattern bus, the system control chip of above-mentioned computer system has an external graphics bus, and in order to connect the external graphics processor on the plug-in unit, it comprises:
Internal graphics processor is arranged on the motherboard of above-mentioned computer system, and it utilizes a virtual pattern bus, is connected in the said external graphics bus in the said system control chip; And
Audiomonitor, be arranged in the said system control chip, be mounted on the extension of said external graphics bus in the said system control chip, in order to monitor the request between other elements in said external graphic process unit, above-mentioned internal graphics processor and above-mentioned computer system, so as to the resource of integrated said external graphic process unit and above-mentioned internal graphics processor.
10. computer system as claimed in claim 9, wherein in the said system control chip, also comprise a multiplexer group, place between the extension and above-mentioned virtual pattern bus of said external graphics bus in the said system control chip, in order to the data transfer between other elements in control said external graphic process unit, above-mentioned internal graphics processor and the above-mentioned computer system.
11. computer system as claimed in claim 9, wherein above-mentioned internal graphics processor places in the said system control chip.
12. computer system as claimed in claim 9, wherein the said external graphic process unit is disposed at different system resources space with above-mentioned internal graphics processor, and above-mentioned audiomonitor determines it to transmit target then according to transmitting the desired system resources space of data.
13. computer system as claimed in claim 9, wherein the said external graphics bus is advanced graphics port (AGP) bus, and above-mentioned virtual pattern bus then is in order to control the control signal of above-mentioned multiplexer group in the advanced graphics port bus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 00100069 CN1228722C (en) | 2000-01-04 | 2000-01-04 | System control chip with multiplex pattern bus structure and computer system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 00100069 CN1228722C (en) | 2000-01-04 | 2000-01-04 | System control chip with multiplex pattern bus structure and computer system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1303055A true CN1303055A (en) | 2001-07-11 |
| CN1228722C CN1228722C (en) | 2005-11-23 |
Family
ID=4575208
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 00100069 Expired - Lifetime CN1228722C (en) | 2000-01-04 | 2000-01-04 | System control chip with multiplex pattern bus structure and computer system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1228722C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100335996C (en) * | 2005-02-04 | 2007-09-05 | 威盛电子股份有限公司 | Chipset maintaining screen display method and its computer system |
| CN1952979B (en) * | 2005-10-14 | 2012-06-27 | 威盛电子股份有限公司 | Multiple graphics processor systems and methods |
-
2000
- 2000-01-04 CN CN 00100069 patent/CN1228722C/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100335996C (en) * | 2005-02-04 | 2007-09-05 | 威盛电子股份有限公司 | Chipset maintaining screen display method and its computer system |
| CN1952979B (en) * | 2005-10-14 | 2012-06-27 | 威盛电子股份有限公司 | Multiple graphics processor systems and methods |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1228722C (en) | 2005-11-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6675248B1 (en) | Apparatus, method and system for accelerated graphics port bus bridges | |
| JP3431149B2 (en) | Peripheral device interface system and method using virtual FIFO | |
| US5923860A (en) | Apparatus, method and system for remote peripheral component interconnect bus using accelerated graphics port logic circuits | |
| US6553446B1 (en) | Modular input/output controller capable of routing packets over busses operating at different speeds | |
| EP1325417B1 (en) | Shared address translation and caching | |
| US5625829A (en) | Dockable computer system capable of symmetric multi-processing operations | |
| US7663633B1 (en) | Multiple GPU graphics system for implementing cooperative graphics instruction execution | |
| US7228382B2 (en) | Storage control apparatus and method thereof | |
| US20020087614A1 (en) | Programmable tuning for flow control and support for CPU hot plug | |
| CN1892586B (en) | Centralized hot-pluggable video controller and redirectional logic unit | |
| US20070143546A1 (en) | Partitioned shared cache | |
| US7185127B2 (en) | Method and an apparatus to efficiently handle read completions that satisfy a read request | |
| US6044207A (en) | Enhanced dual port I/O bus bridge | |
| US6449677B1 (en) | Method and apparatus for multiplexing and demultiplexing addresses of registered peripheral interconnect apparatus | |
| CA2564601A1 (en) | Gpu rendering to system memory | |
| US20060095593A1 (en) | Parallel processing mechanism for multi-processor systems | |
| CN100445965C (en) | Information processing device and data control method in information processing device | |
| JP2004503859A (en) | Memory controller hub | |
| US7725664B2 (en) | Configuration definition setup method for disk array apparatus, and disk array apparatus | |
| WO2023124304A1 (en) | Chip cache system, data processing method, device, storage medium, and chip | |
| CN114860329A (en) | Dynamic consistency biasing configuration engine and method | |
| JPH08115289A (en) | Data-processing system with write-through cache at every request to be executed in forced sequence | |
| CN1228722C (en) | System control chip with multiplex pattern bus structure and computer system | |
| WO2001016743A2 (en) | Shared memory disk | |
| US20070106826A1 (en) | Method and computer system using PCI-Express |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20051123 |