CN1302540C - Method for promoting memory cell confining force of silicon nitride ROM - Google Patents
Method for promoting memory cell confining force of silicon nitride ROM Download PDFInfo
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- CN1302540C CN1302540C CNB031463533A CN03146353A CN1302540C CN 1302540 C CN1302540 C CN 1302540C CN B031463533 A CNB031463533 A CN B031463533A CN 03146353 A CN03146353 A CN 03146353A CN 1302540 C CN1302540 C CN 1302540C
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Abstract
The present invention relates to a method of enhancing the holding capability of the storage unit of a silicon nitride read only memory, wherein the silicon nitride read only memory is formed on a wafer. The method makes a baking process to the wafer after making a last plasma process on the wafer and before making a classified test on the wafer.
Description
Technical field
The invention relates to a kind of manufacture method of internal memory, and particularly relevant for a kind of method of promoting the memory cell confining force of silicon nitride ROM.
Background technology
In Nonvolatile memory able to programme and erasable, flash memory wherein is able to programme except having, still can preserve the advantage of data after can erasing and cut off the power supply, have more can be in circuit (in-circuit) carry out the advantage that electricity programming and electromigration remove, therefore become extensively a kind of Nonvolatile memory assembly of employing of personal computer and electronic equipment institute.
The form of flash memory for example is with the doped polycrystalline silicon read-only memory of making the floating boom utmost point and the silicon nitride ROM with silicon nitride electric charge capture layer etc., wherein silicon nitride ROM has the zone that the electronics that flows into the silicon nitride electric charge capture layer only concentrates on the part, susceptibility for its defective of tunnel oxide is less, be not easy to produce leakage current, and silicon nitride ROM can store two advantages such as (1cell 2bit) data in a memory cell, therefore, can be by using silicon nitride ROM to ask for better components performance.
For silicon notride ROM module, except the general reliability (reliability) for memory subassembly requires, more require its data to store and reach more than 10 years, and can also regular event after through the programming that repeats and erase operation, therefore, must when carrying out reliability test, just carry out the test of data confining force (data retention) to silicon notride ROM module.This memory cell confining force test (cell retention check) was carried out in the stage of wafer class test (wafer sort test), its practice for example be with wafer finished product (finished product) be heated to Celsius 250 the degree and kept 24 hours, during and apply high voltage to carry out sequencing.
In the manufacture process of above-mentioned silicon nitride ROM, be positioned at outermost two character lines of memory cell arrays (Wordline) and will be subjected to polytechnic destruction quite easily, wherein tunnel oxide is also destroyed thereby cause, and, in technology, have some steps must use plasma to handle, and these a little plasma process will make hole (hole) be absorbed in impaired tunnel oxide.In known technology, when the wafer of this silicon nitride ROM is accepted test (Wafer Acceptance Test carrying out wafer, WAT), after quality control (QC) visual inspection, be to enter the wafer class test stage with that, yet, when this wafer because of the impaired hole that in tunnel oxide, has been absorbed in, and when this wafer is carried out the test of memory cell confining force, the electric charge that this hole will be caused in the electric charge capture layer enters in the substrate through the tunnel oxide tunnelling, thereby caused the loss of electric charge, the decline of internal memory confining force, and and then make the reduction of start voltage state.
Summary of the invention
Therefore, purpose of the present invention is providing a kind of method of promoting the memory cell confining force of silicon nitride ROM, can avoid the loss of the electric charge in the electric charge capture layer and the reduction of electric charge hold facility, and then avoids the reduction of start voltage.
The present invention proposes a kind of method of promoting the memory cell confining force of silicon nitride ROM, wherein this silicon nitride ROM has been formed on the wafer, the method is carried out a baking process to wafer, and wherein this baking process carries out after the last plasma process that carries out this wafer and before this wafer carries out a wafer class test.
From the above, because the present invention after carrying out the last plasma process of this wafer and before wafer carries out the wafer class test, carries out a baking process to this wafer, therefore, through after the baking process, just the hole that is absorbed in tunnel oxide can be removed.
And, because the hole that is absorbed in tunnel oxide in this wafer is removed, therefore, even this wafer is after carrying out follow-up memory cell confining force test, also can not produce a large amount of problems that run off of the electric charge that causes in the hole, thus the electric charge hold facility that can effectively promote silicon notride ROM module.
For above and other objects of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and cooperate appended graphicly, elaborate.
Description of drawings
Fig. 1 illustrate is promoted the schematic flow sheet of method of the memory cell confining force of silicon nitride ROM for first embodiment of the invention a kind of.
Fig. 2 illustrate is promoted the schematic flow sheet of method of the memory cell confining force of silicon nitride ROM for second embodiment of the invention a kind of.
Fig. 3 illustrate is promoted the schematic flow sheet of method of the memory cell confining force of silicon nitride ROM for third embodiment of the invention a kind of.
Fig. 4 illustrate is the characteristic schematic diagram of previously baked 8 hours wafer finished product with the bias voltage of the wafer finished product of testing according to general confining force.
Indicate explanation:
S100、S102、S104、S106、S108、S110、S112、S200、S202、S204、S206、S208、S210、S212、S300、S302、S304、S306、S308、S310、S312：
Step
Embodiment
First embodiment
Fig. 1 illustrate is the schematic flow sheet of the method for the memory cell confining force of a kind of silicon nitride ROM of first embodiment of the invention.
At first, please refer to the step S100 of Fig. 1, on wafer, form patterned protective layer (Passivation layer) with silicon nitride ROM.The step that wherein forms the patterning protective layer comprises: form protective layer on whole wafer, form patterned light blockage layer again, then be that mask etching is removed protective layer partly with the formation patterned protective layer with the photoresist layer, and then remove photoresist layer.And wherein the method for etching removal partial protection layer for example is to use the dry-etching method of plasma, and the method for removal photoresist layer for example is to use the dry type of plasma to divest method and uses the wet type of solution to divest method.
Then; please refer to the step S102 of Fig. 1; the wafer that is formed with the patterning protective layer is carried out inspect after the etching of protective layer (After Etch Inspection, whether AEI) step is correct in order to inspect by the pattern of the formed patterning protective layer of etching method.
Then, please refer to the step S104 of Fig. 1, after wafer is carried out etching, inspect step after, then this wafer is carried out baking (bake) technology, to remove the hole that in the silicon notride ROM module of wafer, is absorbed in tunnel oxide.Wherein this baking process for example is that the wafer finished product is placed heater, feeds nitrogen as environmental gas, is toasted with a proper temperature of being scheduled to and through a predetermined appropriate time.Wherein the temperature of this baking process for example is about 170 degree Celsius are spent to 300, and its stoving time for example is about 8 hours to 24 hours.
Then, please refer to the step S106 of Fig. 1, wafer is carried out an alloy (Alloy) step, so that have preferable interface between the metal material in the silicon nitride ROM, and repair the quality of the boundary defect of tunnel oxide with the lifting tunnel oxide.
Then, please refer to the step S108 of Fig. 1, to wafer carry out a wafer be accepted test (WaferAcceptance Test, WAT), to confirm that this wafer is by the yield (yield) of wafer manufactory (Fab) when manufacturing is come out.
Then, please refer to the step S110 of Fig. 1, wafer is carried out quality control (QC) visual inspection, with the outward appearance that detects this wafer defectiveness or stained whether.Generally speaking, the wafer by quality control promptly becomes the wafer finished product and can send wafer manufactory.
Then, please refer to the step S112 of Fig. 1, this wafer finished product is carried out a series of wafer class test (wafer sort test), wherein the wafer class test for example is to carry out in testing factory, and, in the wafer class test, comprise the memory cell confining force test of the memory cell hold facility of testing this wafer finished product.Wherein this memory cell confining force test case in this way the wafer finished product is heated to Celsius 250 the degree kept 24 hours, during and apply high voltage to carry out sequencing.
Second embodiment
And the present invention still has other embodiment except above-mentioned first embodiment, and Fig. 2 illustrate is the schematic flow sheet of the method for the memory cell confining force of a kind of silicon nitride ROM of second embodiment of the invention.
The present embodiment and the first embodiment difference be baking process after the alloy step and wafer carry out before being accepted testing procedure, therefore, the administration step of the memory cell confining force of the enhancement silicon nitride ROM of present embodiment is as described below:
At first; on wafer, form patterned protective layer (step S200) with silicon nitride ROM; again the wafer that is formed with the patterning protective layer is carried out inspecting step (step S202) after the etching of protective layer; then wafer is carried out an alloy step (step S204); again this wafer is carried out a baking process, to remove the hole (step S206) that in the silicon notride ROM module of wafer, is absorbed in tunnel oxide.Then, wafer is carried out a wafer be accepted test (step S208), again this wafer is carried out a quality control visual inspection step (step S210), thereafter the wafer finished product is carried out a series of wafer class test (step S212).
The 3rd embodiment
And the present invention still has other embodiment except above-mentioned first, second embodiment, and Fig. 3 illustrate is the schematic flow sheet of the method for the memory cell confining force of a kind of silicon nitride ROM of third embodiment of the invention.
Present embodiment and first, second embodiment difference, be in the present embodiment, baking process carries out after wafer is accepted testing procedure and before the wafer class test, and therefore, the administration step of the memory cell confining force of the enhancement silicon nitride ROM of present embodiment is as described below:
At first; on wafer, form patterned protective layer (step S300) with silicon nitride ROM; again the wafer that is formed with the patterning protective layer is carried out inspecting step (step S302) after the etching of protective layer; then wafer is carried out an alloy step (step S304); again wafer is carried out a wafer and be accepted test (step S306); then this wafer is carried out a baking process; to remove the hole (step S308) that in the silicon notride ROM module of wafer, is absorbed in tunnel oxide; again this wafer is carried out a quality control visual inspection step (step S310), again this wafer finished product is carried out a series of wafer class test (step S312) thereafter.
And in the 3rd embodiment, baking process can also carry out after quality control visual inspection step with before the wafer class test.
In above-mentioned step S104, S206, S308, generally speaking, as long as temperature is spent above up to Celsius 170 and was toasted about 8 hours, just (detrap) can be removed in the hole that is trapped in the tunnel oxide, therefore, baking process of the present invention need not done special qualification, can look on the actual process need be to set suitable baking temperature and stoving time.And, the employed heater of this baking process can also be various form, it for example can be hot boiler tube (furnace), or aging test furnace (burn-in oven), or the device that uses ultraviolet light to heat, also or use test (cell retention check) identical heater with the follow-up memory cell confining force that carries out.
In above-mentioned preferred embodiment, baking process after etching, inspect individually after the step with the alloy step before, be accepted before the test with wafer after the alloy step, wafer is accepted after the test with the quality control visual inspection before or implement after the quality control visual inspection with before the wafer class test, yet the present invention is not limited thereto.In fact, the main cause that is absorbed in the hole in tunnel oxide is because due to the plasma process, hence one can see that, as long as afterwards at last one plasma process of wafer (being step 100,200,300 dry type photoresistance divesting technology in preferred embodiment of the present invention), and before the wafer class test, carry out baking process of the present invention, promptly be included in the technical characterictic of the present invention, remove with the electric charge that will be absorbed in tunnel oxide and can reach purpose of the present invention.
Please refer to Fig. 4, Fig. 4 illustrate is the schematic diagram of the bias voltage difference that measured before and after previously baked 8 hours wafer finished product and the memory cell confining force test according to the wafer finished product of general test program.Wherein in the result shown in Fig. 2, in previously baked 8 hours wafer finished product (8HR Wafer) and memory cell arrays according to the wafer finished product (STD Wafer) of general test program (unbaked), to outermost two character line (L1 wherein, L32) result schematic diagram of testing with the character line (L16) in centre position, and the longitudinal axis is represented with cumulative probability (cumulative probability), wherein A represents to toast the centre position character line of 8 hours wafer finished product, B represents the centre position character line of the wafer finished product of unbaked, C, E represents to toast two side position character lines of 8 hours wafer finished product, and D, F represents two side position character lines without the wafer finished product of overbaking.As shown in Figure 2, for for the wafer of baking process of the present invention, especially be positioned at character line D, the F in the array outside, its character line is before and after the test of memory cell confining force, and its bias voltage that measures gained has bigger difference, yet, for 8 hours wafer of baking, especially be positioned at character line C, the E in the array outside, its character line is before and after the test of memory cell confining force, and what its bias voltage difference that measures gained can be suitable is little.
Therefore, by the result of above-mentioned Fig. 4 as can be known, the wafer finished product of the baking process of process preferred embodiment of the present invention, make the start voltage that is positioned at the character line of position, both sides in the memory cell arrays of wafer finished product, can keep almost consistent with the start voltage of the character line that is positioned at the centre position, that is it is extremely low to be that baking process of the present invention can make the loss of electric charge drop to, thereby the electric charge hold facility of effectively promoting this wafer finished product (silicon notride ROM module).
In sum, the invention is characterized in the testing process of the wafer that forms silicon notride ROM module, after wafer carries out last plasma process and before wafer carries out the wafer class test, this wafer is carried out a baking process, therefore, after carrying out the baking process of preferred embodiment of the present invention, just the hole that is absorbed in tunnel oxide can be removed with suitable baking temperature and stoving time.
And, because the hole that is absorbed in tunnel oxide in this wafer is removed, therefore, even this wafer is after carrying out follow-up memory cell confining force test, also can not produce a large amount of problems that run off of the electric charge that causes in the hole, and the state of start voltage also only can be kept good state for slight decline, thereby effectively promotes the electric charge hold facility of this wafer finished product (silicon notride ROM module).
Though the present invention with a preferred embodiment openly as above; right its is not in order to limiting the present invention, anyly is familiar with this operator, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (16)
1. a method of promoting the memory cell confining force of silicon nitride ROM is characterized in that, this silicon nitride ROM has been formed on the wafer, and the method for the memory cell confining force of this enhancement silicon nitride ROM comprises the following steps:
This wafer is carried out a baking process, and wherein this baking process carries out after a last plasma process that carries out this wafer and before this wafer carries out a wafer class test.
2, the method for the memory cell confining force of enhancement silicon nitride ROM as claimed in claim 1, it is characterized in that, after this last plasma process that carries out this wafer, before this wafer class test step, comprise that also carrying out inspecting after the etching step, an alloy step, a wafer is accepted a testing procedure and a quality control visual inspection step.
3, the method for the memory cell confining force of enhancement silicon nitride ROM as claimed in claim 2 is characterized in that, this baking process is inspected step after this etching after, and implements before this alloy step.
4, the method for the memory cell confining force of enhancement silicon nitride ROM as claimed in claim 2 is characterized in that, this baking process is after this alloy step, and execution before this wafer is accepted testing procedure.
5, the method for the memory cell confining force of enhancement silicon nitride ROM as claimed in claim 2 is characterized in that, this baking process is after this wafer is accepted testing procedure, and execution before this quality control visual inspection step.
6, the method for the memory cell confining force of enhancement silicon nitride ROM as claimed in claim 2 is characterized in that, this baking process is after this quality control visual inspection step, and execution before this wafer class test.
7, the method for the memory cell confining force of enhancement silicon nitride ROM as claimed in claim 1 is characterized in that, this wafer class test comprises memory cell confining force test.
8, the method for the memory cell confining force of enhancement silicon nitride ROM as claimed in claim 7 is characterized in that, this baking process uses the heater identical with this memory cell confining force test to carry out.
9. method of promoting the memory cell confining force of silicon nitride ROM, this silicon nitride ROM has been formed on the wafer, and the method for the memory cell confining force of this enhancement silicon nitride ROM comprises the following steps:
On this wafer, form a photoresist layer of a protective layer and patterning in regular turn;
With this photoresist layer is mask, and this protective layer of part is removed in etching;
Remove this photoresist layer;
This wafer is carried out inspecting step after the etching;
This wafer is carried out an alloy step;
This wafer is carried out a wafer be accepted testing procedure;
This wafer is carried out a quality control visual inspection step; And
This wafer is carried out a wafer class test;
It is characterized in that also comprising and carry out a baking process that wherein this baking process and was implemented before the step of this wafer being carried out this wafer class test after removing the step of this photoresist layer.
10, the method for the memory cell confining force of enhancement silicon nitride ROM as claimed in claim 9 is characterized in that, the step that removes this photoresist layer comprises uses the dry type of plasma to divest method.
11, the method for the memory cell confining force of enhancement silicon nitride ROM as claimed in claim 9 is characterized in that, this baking process is inspected step after this etching after, and implements before this alloy step.
12, the method for the memory cell confining force of enhancement silicon nitride ROM as claimed in claim 9 is characterized in that, this baking process is after this alloy step, and execution before this wafer is accepted testing procedure.
13, the method for the memory cell confining force of enhancement silicon nitride ROM as claimed in claim 9 is characterized in that, this baking process is after this wafer is accepted testing procedure, and execution before this quality control visual inspection step.
14, the method for the memory cell confining force of enhancement silicon nitride ROM as claimed in claim 9 is characterized in that, this baking process is after this quality control visual inspection step, and execution before this wafer class test.
15, the method for the memory cell confining force of enhancement silicon nitride ROM as claimed in claim 9 is characterized in that, this wafer class test comprises memory cell confining force test.
16, the method for the memory cell confining force of enhancement silicon nitride ROM as claimed in claim 15 is characterized in that, this baking process uses the heater identical with this memory cell confining force test to carry out.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB031463533A CN1302540C (en) | 2003-07-10 | 2003-07-10 | Method for promoting memory cell confining force of silicon nitride ROM |
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| CNB031463533A CN1302540C (en) | 2003-07-10 | 2003-07-10 | Method for promoting memory cell confining force of silicon nitride ROM |
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| CN1567573A CN1567573A (en) | 2005-01-19 |
| CN1302540C true CN1302540C (en) | 2007-02-28 |
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| CNB031463533A Expired - Fee Related CN1302540C (en) | 2003-07-10 | 2003-07-10 | Method for promoting memory cell confining force of silicon nitride ROM |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1396652A (en) * | 2001-07-12 | 2003-02-12 | 旺宏电子股份有限公司 | Process for preparing silicon nitride ROM |
| CN1404141A (en) * | 2001-09-04 | 2003-03-19 | 旺宏电子股份有限公司 | Making process of charging-preventing nitride ROM |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1396652A (en) * | 2001-07-12 | 2003-02-12 | 旺宏电子股份有限公司 | Process for preparing silicon nitride ROM |
| CN1404141A (en) * | 2001-09-04 | 2003-03-19 | 旺宏电子股份有限公司 | Making process of charging-preventing nitride ROM |
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| CN1567573A (en) | 2005-01-19 |
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