CN1300004A - Command defining method for microcontroller with simplified command set streamline structure - Google Patents
Command defining method for microcontroller with simplified command set streamline structure Download PDFInfo
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Abstract
The instruction definition method of microcontroller for reduced instruction set pipeline structure is characterized by that said method utilizes three instruction definition regions, in which uses same instruction definition region to define immediate operand, operand address or target address, uses another instruction definition region to define operating code with different operation, and uses more instruction definition region to define to operand address or position and target address or position in the instruction so as to control the identification control code of data-transfer between all stages of pipeline in the reduced instruction set pipeline structure.
Description
The present invention relates to a kind of command defining method that is applied to microcontroller (MCU) or central processing unit various microcontrollers such as (CPU), relate in particular to a kind of MCU of simplified command set streamline structure or command defining method of CPU of being applied to.
The instruction length of most of simplified command set streamline structure microcontrollers of having made known to the world at present is 32 (asking for an interview list of references 1,2,3).Typical instruction definition is shown in following table one.
Table one
| 2 | 6 | 8 | 8 | 8 |
| ????IT | ????OP | ????WR | ????RA | ????RB |
The meaning of each field is as follows in the table one.
IT: regulation instruction type.
For example: the instruction of IT=" 00 " expression mathematical operation class;
The instruction of IT=" 01 " presentation logic computing class; IT=" 10 " expression displacement or the instruction of circulation class; The instruction of IT=" 11 " expression jump class.OP: predetermined operation sign indicating number.
For example: OP=" 000101 " represents A-B; OP=" 010001 " expression A and B; OP=" 000011 " represents A+1.WR: the address of regulation deposit operation operation result is called destination address.
The address of RA: specifies operands A.
The address of RB: specifies operands B.
The instruction definition scheme of prior art is referring to following document:
List of references 1. U.S. AT﹠amp; The Principles of CMOS VLSI Design of the Neil H.E.Weste of T and Kamram Eshraghian, 1993.
The ARM Architectural reference Manual of the Advanced RISC Machines Ltd. of list of references 2. U.S. Prentice Hall, 1996.
The VerilogDigital Computer Design of the Mark Gordon Arnold of list of references 3. U.S. Prentice Hall, Algorithms into Hardware, 1999.
MCS 51 Micro-controllerFamily User ' the s Manual of list of references 4. American I ntel Corporation, 1994.
In sophisticated vocabulary microcontroller, the length of instruction is variable.For example, the instruction of INTEL 8051 can the variation (list of references 4) from 8 to 24.The execution of every instruction in time can not be overlapping with adjacent instructions, carries out and respectively instruct the required time also different.But in the simplified command set streamline structure microcontroller, the length of every instruction is the same, and the execution time also is the same, in each clock period, an instruction entry instruction " streamline " is all arranged, and all have an instruction from " streamline ", to come out.So the execution speed of microcontroller is to carry out an instruction (except individual instructions such as the redirect, instruction such as meter reading) average each clock period.The purpose of pipeline organization is to improve execution speed.For example, be 1 μ s if carry out an average required time of instruction, if do not take pipeline organization, then its execution speed is average 1 instruction/1 μ s; If adopt the pipeline organization in 5 stages, then its execution speed is average 5 instruction/1 μ s.
The existing principle of work of free flow line structure microcontroller so that 4 stage streamlines are example:
Phase one, the instruction fetch phase: programmable counter provides an address to command memory; This storer will be exported an instruction of address correspondence therewith.This instruction comprises the information such as operational code, operand, operand address and destination address of mathematical logic unit.
Subordinate phase, the stage is counted in read operation: read corresponding operand according to the operand address that is provided in the instruction from random access memory, and operand is added to the input end of mathematical logic unit.
Phase III, carry out operation stages: the operation of mathematical logic unit executable operations sign indicating number defined, and obtain a result.
The quadravalence section is write the stage as a result: operation result is write in the storage unit of destination address regulation.
The operation free list two of above-mentioned quadravalence section pipeline organization is observed.
Table two
| Cycle | Instruction fetch phase | The stage is counted in read operation | Execute phase | Write the stage as a result |
| ????0 | Instruction 1 | |||
| ????1 | | Instruction 1 | ||
| ????2 | | | Instruction 1 | |
| ????3 | | | | Instruction 1 |
| ????4 | Instruction 5 | | | |
In the cycle 0, instruction 1 is in the instruction fetch phase, and instruct 1 to take out from command memory this moment, and in the cycle 1, instruction 1 moves on to read operation and counts the stage, according to the address of regulation in the instruction, read operands A, B; At this moment, instruction 2 enters the instruction fetch phase.In the cycle 2, instruction 1 enters the execute phase, operational code is offered the mathematical logic unit and with the operation that puts rules into practice; Instruction 2 moves on to read operation and counts the stage; Instruction 3 enters the instruction fetch phase.At last, in the cycle 3, instruction 1 enters the stage as a result of writing, and the operation result of mathematical logic unit is written in the storage unit of destination address regulation.
From above-mentioned streamline chart, can see that when the operand in the instruction 2 and 3 or had been read, the result of instruction 1 was written in the storage unit.2 and 3 need be with the operation result of instruction 1 if instruct in stage of read operation number or execution command, instruct 1 operation result just must be delivered to the input end of mathematical logic unit in advance so, otherwise, " data disaster " (DATA HAZARD) will take place or obtain wrong result.For example, if instruction 2 will be with the result of instruction 1, so in the cycle 3, the result of instruction 1 must be transferred to the execute phase of instruction 2 forward when being written into storer.(this data are passed on and are realized by following method: read operation is counted operand address or the position of stage and execute phase and write as a result the destination address or the position in stage compare, and with one group of multidiameter option switch suitable service data is passed to the mathematical logic unit.
Consider the follow procedure fragment:
SUB A, B, C----A-B, the result is stored in C
ADD D, C, F----D+C, the result is stored in F
Instruction X
Instruction Y
The execution order of said procedure fragment can be represented with the streamline chart of following table three.
Table three
| Cycle | Instruction fetch phase | The stage is counted in read operation | Execute phase | Write the stage as a result |
| ????0 | ?SUB?A,B,C?? | |||
| ????1 | ?ADD?D,C,F??? | ?SUB?A,B,C???? | ||
| ????2 | Instruction X | ?ADD?D,C,F??? | ?SUB?A,B,C??? | |
| ????3 | Instruction Y | Instruction X | ?ADD?D,C,F??? | ?SUB?A,B,C???? |
In the cycle 3 of last table three, the result of A-B is written into C.In the execute phase, C but is used to calculate D+C.Therefore, normal read operation is counted the path and must be got around, and must will write the input end that C value in the stage as a result is delivered to the mathematical logic unit of execute phase.Otherwise, just can not get expected result.
In sophisticated vocabulary microcontroller, because the execution of adjacent instructions is non-overlapping copies in time, promptly after current this instruction is finished, next bar instruction is just taken out from command memory and is begun and carried out, but in the simplified command set streamline structure microcontroller, because the execution of adjacent instructions is overlapped in time, if the operand of a certain instruction is the execution result (it is relevant that this situation is called data) of adjacent last or two instruction, so just this result must be delivered to the execute phase forward; Otherwise, so-called " data disaster " (data hazard) will take place, also the operation result that just can not obtain expecting.In order to realize the correct transmission of data between each stage, read operation need be counted the instruction in stage and the operand address in the instruction of execute phase and compare with destination address in the instruction of writing stage as a result; Control one group of multidiameter option switch with the signal that the result produced relatively then, thereby suitable operand is sent to the data input port of mathematical logic unit.In order to realize this data transfer like clockwork, in instruction definition, must manage strict difference operand address and destination address.That is, generally the method for Cai Yonging is exactly the define method shown in the table one, promptly utilizes different instruction definition zones to come specifies operands address and destination address respectively.
The objective of the invention is to shorten the length of the instruction of adopting the traditional instruction define method, but still can be completely achieved and the traditional instruction identical functions by a kind of command defining method of simplification.
The invention provides a kind of command defining method of new simplified command set streamline structure microcontroller, this method is utilized three instruction definition zones, wherein stipulate number, operand address or destination address immediately with same instruction definition zone, come the operational code of regulation different operating computing with another instruction definition zone, thereby and with also having an instruction definition zone to be given for the identification control sign indicating number of the data transfer of streamline between each stage in operand address in the recognition instruction or position and destination address or the position control simplified command set streamline structure.
According to one aspect of the present invention, a kind of command defining method that is used for the microcontroller of simplified command set streamline structure is provided, its instruction length comprises 17, lacked 15 than above-mentioned instruction definition, thereby wherein three in the instruction identification control sign indicating numbers of controlling the data transfer of streamline between each stage in the described simplified command set streamline structure as the operand address in the recognition instruction or position and destination address or position; Eight in this instruction as performed several immediately, operand address of instruction or destination address; And six in this instruction operational codes as the computing of regulation different operating.
The instruction definition of the reduced instruction pipeline organization microcontroller that the present invention proposes shortens to 17 and needn't distinguish operand address and destination address with instruction length from original 32, has so not only shortened instruction length but also can realize same function fully.Thereby, dwindled the area of command memory, can dwindle the area of microcontroller chip then.In fact, the area of command memory can dwindle 47%.
Fig. 1 is the synoptic diagram that illustrates according to the principle of command defining method of the present invention.
Fig. 2 is the block scheme that adopts according to the simplified command set streamline structure microcontroller of the inventive method.
Also objects and advantages of the present invention will be become more obviously from following detailed description.
In following table four, the least-significant byte in the instruction (the 0th to the 7th) both can be used for definition number, operand address immediately, also can be used for the objective definition address; Middle 6 (the 8th to the 13rd) are operational code, the different operating computing of regulation CPU; The highest 3 (the 14th to the 16th) is the identification control sign indicating number, is used for operand address or position and destination address or position in the recognition instruction, thereby accurately controls the data transfer of streamline between each stage.For clear, below the order format with table four is that example is described command defining method of the present invention, but those skilled in the art should be understood that should be this as limitation of the present invention.
Table four
In table four, when being ' 1 ' for the 16th, expression has an operand to read from totalizer; When being ' 0 ' for the 16th, expression does not have operand from totalizer; When being ' 1 ' for the 15th, expression has an operand to read from RAM (random access memory); When being ' 0 ' for the 15th, expression does not have operand to read from RAM.When being ' 1 ' for the 14th, the target that the result is write in expression is RAM, and when being ' 0 ' for the 14th, the target that the result is write in expression is totalizer A.Various combination according to the 14th to the 16th this tribute signal different phase in streamline, and the numerical value by the different phase in streamline of least-significant byte in the comparison order, whether the data that just can accurately differentiate adjacent instructions are relevant, thereby realize the correct transmission of data between each stage in the streamline.Certainly, can also stipulate with different modes for above-mentioned three, but, below adopt this to stipulate to describe the present invention for clear.
With reference now to Fig. 1, the principle of work of this method is described.
In Fig. 1, length is instruction vector 1 various microcode vector of output after command decoder 2 decodings of 17.Wherein microcode vector 3 is address (instructions minimum eight), is defeated by random access memory 10 (reading the address as data) and data correlation discriminating circuit 11 respectively.In data correlation discriminating circuit 11, the two-level address register is arranged, vector 3 at first enters first order register, exports to second level register then.Vector 3 is the address of reading to visit the stage of counting before entering the data correlation discriminating circuit; Behind first order register, be output as the address of execute phase; Behind the register of the second level, be output as and write the address in stage as a result.Vector 5 is Senior Three positions (promptly the 14th to the 16th) of instruction.Similar to vector 3, vector 5 also will pass through the two-stage register.In the information of different phase and by relatively vectorial 3 numerical value, pass through required logical combination according to vector 5 again, output control vector 15 in different phase.Data select transfer circuit 16 according to control vector 15, select 2 suitable data and pass to mathematical logic unit 19 by its output terminal 17 and 18 from following 5 different input data:
(1) output of the operation result of mathematical logic unit 19 12;
(2) output 13 of totalizer 9;
(3) write the output 7 of result register;
(4) output of the data of random access memory 10 14;
(5) output vector 4 of command decoder 2 (counting immediately).
The instruction definition of the simplified command set streamline structure microcontroller that the present invention proposes shortens to 17 and have the character that realizes original all functions with instruction length from 32 of past.Compare with background technology, largest benefit of the present invention is to have dwindled the area of command memory among the RAM widely, thereby has reduced the production cost of simplified command set streamline structure microcontroller chip, and reliability of products also improves thereupon.The area of fabrication order storage array can reduce 47% like this.
The present invention can be applicable to require fast operation, simplified command set streamline structure microcontroller that chip area is little.Now the block scheme (Fig. 2) with the simplified command set streamline structure microcontroller illustrates in fact mode now.
Below with reference to Fig. 2, the principle of work in each stage of simplified command set streamline structure microcontroller of using command defining method of the present invention is described:
(1) instruction fetch phase (clock period 0): programmable counter 1 is according to the control signal 6 of control module 7 outputs, output order address 2.Command memory 3 is according to the corresponding instruction vector 4 (instruction length is 17) of address 2 outputs.
(2) (clock period 1) counted the stage in read operation: instruction vector 4 becomes instruction vector 10 (postponing a clock period than instruction vector 4) behind order register 5.Instruction vector 10 is output various microcode vector (12,13,15 and 16) after command decoder 11 decodings.According to these microcode vectors, read corresponding operand.
(3) execute phase: mathematical logic unit 30 carries out corresponding computing according to 31 pairs of input operands 28,29 of operation control code vector, and operation result 22 flowed to writes result register 18.
(4) write the stage as a result: the operation result that existence is write in the result register writes in random access memory 21 or the totalizer 20 by its output terminal 17.
Illustrate that now the application of the present invention in the simplified command set streamline structure microcontroller realizes principle of work.
Length is instruction vector 10 output microcode vector 12,13,15,16 after command decoder 11 decodings of 17.Wherein vector 12 is the Senior Three position (the 14th to the 16th) of instruction, and vector 15 is address (minimum 8).Vector 16 expressions are counted immediately, and vector 13 is operational code (inferior high 6).Vector 12,15 all enters the input end of data correlation discriminating circuit 25.In data correlation discriminating circuit 25, secondary register and two address comparators are arranged, two address comparators are used for the comparison read operation and count stage address and execute phase address, and read operation is counted the stage address and is write stage address as a result.Vector 12,15 all will be through the secondary register in the data correlation discriminating circuit 25.Vector 12,15 is before entering data correlation discriminating circuit 25, for the stage is counted in read operation.First order register is output as the execute phase address in the data correlation discriminating circuit 25; Second level register is output as writes stage address as a result.According to vector 12 information, and, pass through required logical combination again, control vector 26 of data correlation discriminating circuit 25 outputs by the value of compare address vector 15 in different phase in different phase.According to control vector 26, data are selected transfer circuit 27 to select 2 suitable data from the input data of 5 different phases, separate sources and by its output terminal 28,29, are transported to the input end of mathematical logic unit 30.Mathematical logic unit 30 carries out arithmetic operations such as mathematics, logic, circulation or displacement according to operation control vector 31 to input data 28,29, and operation result 22 flowed to writes result register 18 and select transfer circuit 27 with data.
Below continue to be described with reference to Figure 2 two specific embodiment of the present invention.
Example one, consider following 2 instructions:
MOV[m1],A
ADD?A,[m1]
Article one, Zhi Ling implication is that the data among the totalizer A are sent to m1 is in the storage unit of address.A+[m1 is carried out in second instruction] computing and give totalizer A with the result.
In this example, the operand [m1] of second instruction is the operation result of article one instruction.When second instruction was in read operation and counts the stage, article one instruction was in the execute phase, and it is in the storage unit of address that the latter's result does not write as yet with m1, so second instructs required operand [m1] directly not read from this storage unit; Thereby the execution result of article one instruction directly must be sent to the input end of mathematical logic unit 30, thus in the next clock period, promptly instructing when being in the execute phase when second, the input end of mathematical logic unit 30 can obtain correct operand.This correct data transfer realizes by data correlation discriminating circuit 25.At first, operand address (the stage address is counted in read operation) during address comparator in the data correlation discriminating circuit 25 instructs destination address (execute phase address) in article one instruction and second compares, because these two addresses are identical, so [the 16th is totalizer A for ' 1 ' expression has an operand for ' 101 ' for comparer output ' 1 ' signal, Senior Three position (the 14th to the 16) signal of article one instruction; The 15th is that ' 0 ' expression does not have operand from RAM; The 14th is that ' 1 ' expression is write result's target in RAM].[the 16th has an operand from totalizer A for ' 1 ' expression to the highest tribute signal of second instruction for ' 110 '; Represent that another operand is from RAM for ' 1 ' for the 15th; The 14th is totalizer A for ' 0 ' expression target location].According to the signal of the Senior Three position of the output signal and instruction of comparer in different phase, the data correlation discriminating circuit 25 output control corresponding amounts of asking 26.Data select transfer circuit 27 according to control vector 26, and the input end 28,29 that the operating result and the content in the totalizer of article one instruction is sent to mathematical logic unit 30 respectively carries out ADD to be operated.
Example two, please see following three instructions:
SUB[m1],A
DEC[m2]
ADD?A,[m1]
Article one, Zhi Ling implication is to be that data in the ram cell of address and the data in the totalizer are subtracted each other with m1, and it is in the ram cell of address that operation result exists with m1.The performed computing of second instruction is to be that data in the ram cell of address deduct 1 with m2, and it is in the ram cell of address that operation result exists with m2.Article three, the performed computing of instruction be in the totalizer data with m1 be data addition in the ram cell of address, operation result exists in the totalizer.In this example, article one instruction is relevant with second instruction no datat; Second instruction instructs with the 3rd that also no datat is relevant, but article one instructs and exist data relevant with the 3rd instruction, because the operand [m1] of the 3rd instruction is the operating result that article one is instructed.When the 3rd instruction was in read operation and counts the stage, article one instruction is in write the stage as a result, but the result not write as yet with m1 be the ram cell of address.So the operand [m1] of the 3rd instruction can not directly be read in RAM; Thereby the output 17 that must will write result register 18 directly transfers to the input end of mathematical logic unit 30.This routine data selection transfer principle and example one are similar.
Should be understood that above-mentioned example only is a particular instance of the present invention, must not be considered as limitation of the present invention.
Claims (9)
1. the command defining method of the microcontroller of a simplified command set streamline structure, it is characterized in that this method utilizes three instruction definition zones, wherein stipulate number, operand address or destination address immediately with same instruction definition zone, come the operational code of regulation different operating computing with another instruction definition zone, thereby and with also having an instruction definition zone to be given for the identification control sign indicating number of the data transfer of streamline between each stage in operand address in the recognition instruction or position and destination address or the position control simplified command set streamline structure.
2. the method for claim 1, it is characterized in that described three instruction definition zones comprise 17, thereby the identification control sign indicating number of wherein controlling the data transfer of streamline between each stage in the described simplified command set streamline structure as operand address in the recognition instruction or position and destination address or position comprises three; Operational code as the computing of regulation different operating comprises six; And as instructing performed number, operand address or destination address immediately to comprise eight.
3. method as claimed in claim 2 is characterized in that described three Senior Three positions for described instruction.
4. method as claimed in claim 3 is characterized in that described six is the inferior high six of described instruction.
5. method as claimed in claim 4 is characterized in that described eight for described instruction minimum eight.
6. as each described method in the claim 2 to 4, it is characterized in that described three value represent respectively whether to have an operand from totalizer, whether an operand is arranged is totalizer or RAM from RAM and the target of writing the result.
7. method as claimed in claim 6, it is characterized in that the most significant digit in described three represents whether to have an operand from totalizer, whether the inferior high bit representation in described three has an operand from RAM, and the target that the lowest order in described three represents to write the result is totalizer or RAM.
8. method as claimed in claim 6 is characterized in that if the most significant digit in described three is ' 1 ', and then expression has an operand from totalizer, if be ' 0 ', then expression does not have operand from totalizer; If time high position in described three is ' 1 ', expression has an operand from RAM, if be ' 0 ', then expression does not have operand from RAM; If the lowest order in described three is ' 1 ', then the expression target of writing the result is RAM, if be ' 0 ', the target of then representing to write the result is a totalizer.
9. method as claimed in claim 6 is characterized in that if the most significant digit in described three is ' 0 ', and then expression has an operand from totalizer, if be ' 1 ', then expression does not have operand from totalizer; If time high position in described three is ' 0 ', expression has an operand from RAM, if be ' 1 ', then expression does not have operand from RAM; If the lowest order in described three is ' 0 ', then the expression target of writing the result is RAM, if be ' 1 ', the target of then representing to write the result is a totalizer.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102270112A (en) * | 2010-06-03 | 2011-12-07 | 边立剑 | Reduced instruction-set computer (RISC) microprocessor command decoding circuit |
| CN111651199A (en) * | 2016-04-26 | 2020-09-11 | 中科寒武纪科技股份有限公司 | Apparatus and method for performing vector circular shift operation |
-
1999
- 1999-12-13 CN CN 99124244 patent/CN1300004A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102270112A (en) * | 2010-06-03 | 2011-12-07 | 边立剑 | Reduced instruction-set computer (RISC) microprocessor command decoding circuit |
| CN111651199A (en) * | 2016-04-26 | 2020-09-11 | 中科寒武纪科技股份有限公司 | Apparatus and method for performing vector circular shift operation |
| CN111651199B (en) * | 2016-04-26 | 2023-11-17 | 中科寒武纪科技股份有限公司 | Apparatus and method for performing vector cyclic shift operation |
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