CN1296980C - Method of forming a pad having a recess - Google Patents

Method of forming a pad having a recess Download PDF

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Publication number
CN1296980C
CN1296980C CNB028178254A CN02817825A CN1296980C CN 1296980 C CN1296980 C CN 1296980C CN B028178254 A CNB028178254 A CN B028178254A CN 02817825 A CN02817825 A CN 02817825A CN 1296980 C CN1296980 C CN 1296980C
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CN
China
Prior art keywords
copper
layer
top surface
dielectric layer
semiconductor substrate
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Expired - Lifetime
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CNB028178254A
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Chinese (zh)
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CN1554116A (en
Inventor
托马斯·S·小林
斯科特·K·波兹德
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Nxp American Corp
Vlsi Technology Co ltd
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Freescale Semiconductor Inc
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Publication of CN1554116A publication Critical patent/CN1554116A/en
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Publication of CN1296980C publication Critical patent/CN1296980C/en
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Abstract

A bond pad (100) is formed by first providing a planarized combination of copper (18) and silicon oxide features (14) in a pad region. The silicon oxide features (14) are subjected to an etching process to form a plurality of recesses (15) in the copper over the pad area. A corrosion barrier layer (22) is formed on the copper and on the silicon oxide features in the recesses. Probing of the wafer (10) is performed by attaching probes directly to the copper. A wire bond (24) is directly attached to the copper (18). Due to the presence of the recessed feature (15), the probe (80) is prevented from completely piercing the copper (18). With the recess (15) in the copper, the wire bond (24) is more prone to damage and puncture the corrosion barrier and is less prone to slip on the pad (100).

Description

Formation has the method for the pad of groove
Technical field
The present invention belongs to technical field of semiconductors generally, more particularly belongs to the pad technical field on the semiconductor.
Background technology
Utilize copper to replace aluminium along with in the semiconductor machining industry, developing into, need copper wire to be welded portion (copper wire bond) and be affixed on the copper pad.Follow a problem of copper pad to be, when they are carried out chemico-mechanical polishing (CMP), surperficial depressed phenomenon can take place.A solution is the oxidation trough that is shaped on copper pad, improves evenness.But oxidation trough can make and be difficult to reliably metal and probe or wire bond portion are come in contact.Do not have grooving, not only more be difficult to carry out CMP technology, and probe can damage described pad, thereby infringement is to the engagement capacity of wire bond portion.Therefore, need a kind of pad structure, it allows to exist grooving, and not only can be with the copper wire wire bond to copper pad, and can come in contact with probe reliably.
Summary of the invention
The objective of the invention is to satisfy above-mentioned needs, a kind of method of producing pad on Semiconductor substrate is provided.
According to a first aspect of the invention, provide a kind of method of on Semiconductor substrate, producing pad, having comprised: on this Semiconductor substrate, formed a dielectric layer; Dielectric layer is carried out patterned process, to form a plurality of functional parts in the welding disking area on this dielectric layer; At copper layer of deposit above the dielectric layer, between a plurality of functional part and on a plurality of functional part; The copper layer is carried out chemical mechanical polish process, and with the even curface that is shaped, this surface is made up of the top surface that appears top surface and copper layer of a plurality of functional parts, and the top surface of copper layer is used for directly receiving a probe after through etching in dark; Described a plurality of functional parts are carried out dark interior etching, in through etched copper layer in dark, to form groove; And barrier layer of formation on through etched copper layer in dark and in the described groove.
According to a second aspect of the invention, provide a kind of method that is used to produce semiconductor structure, having comprised: a Semiconductor substrate is provided; A dielectric layer is shaped on this Semiconductor substrate; Dielectric layer is carried out etch processes, in a welding disking area, to form a plurality of functional parts; Cement copper on dielectric layer, on this dielectric layer, forming a copper layer, and between the described functional part with and on form copper gasket; Remove part copper layer and copper gasket, to form an even curface, this surface comprises the top surface of copper gasket and the top surface of each functional part; To the processing of caving in of described a plurality of functional parts, be lower than the groove of copper gasket top surface with formation; And a lead is directly connected on the top surface of copper gasket.
According to a third aspect of the present invention, provide a kind of method that is used to produce semiconductor structure, having comprised: a Semiconductor substrate is provided; On this Semiconductor substrate, form a dielectric layer; Dielectric layer is carried out etching, in a welding disking area, to form a plurality of functional parts; Cement copper on dielectric layer, on this dielectric layer, forming a copper layer, and between the described functional part with and on form copper gasket; Copper layer and copper gasket are carried out planarizing process, and to form an even curface, this surface comprises the top surface of copper gasket and the top surface of each functional part, and wherein the top surface of copper gasket is used for directly receiving a probe; And, form the groove of the top surface that is lower than copper gasket to the processing of caving in of a plurality of functional parts.
The accompanying drawing summary
By means of example the present invention is carried out illustration below, but the present invention is not limited to content shown in the accompanying drawing, in the accompanying drawings, similar Reference numeral is indicated similar member, wherein:
Fig. 1 shows the sectional elevation of a Semiconductor substrate part, shows grooving according to an embodiment of the invention;
Fig. 2 shows that part of Semiconductor substrate shown in Fig. 1, is formed with a metal level on it;
Fig. 3 shows the state of Semiconductor substrate shown in Fig. 2 after planarizing process;
Fig. 4 shows the state of Semiconductor substrate shown in Fig. 3 after passivation layer forms;
Fig. 5 shows the state of Semiconductor substrate shown in Fig. 4 after passivation layer is applied pattern and etch processes;
Fig. 6 shows the state of Semiconductor substrate shown in Fig. 5 after the corrosion barrier layer that is shaped;
Fig. 7 shows the state of a part after the wire bond operation of described Semiconductor substrate; And
Fig. 8 is a vertical view of pad according to an embodiment of the invention.
The skilled artisan in the art will be appreciated that, the member in the accompanying drawing is in view of simplification and sharpening and illustrate, and need not proportionally to draw.For example, the size of some member may be amplified with respect to other member in the accompanying drawing, to help to promote the understanding to embodiments of the invention.
Embodiment
In one embodiment, form an open flume type pad that comprises dielectric regions and copper gasket, in order to improve with copper wire reliably wire bond on copper pad and probe.The present invention is limited by claim, and is understood better by the reference accompanying drawing.
As shown in fig. 1, be formed with a dielectric layer on a surface of Semiconductor substrate 10, this dielectric layer forms certain pattern, forms grooving 14 and area of isolation 12.As used in this, term " substrate surface " the top that is used to refer to functional part (features) on the substrate 10 appears the surface.Substrate 10 is a kind of Semiconductor substrate, and it has been processed to the formation pad, but does not comprise pad, and the formation operation of pad occurs in the process that final metal layer is handled.Therefore, substrate 10 can have transistor, bit line, word line and the similar device that is formed in it.Substrate 10 has a semiconductor layer, such as silicon layer, gallium arsenide layer, silicon germanide layer and similar material layer, and can comprise an insulator, such as silicon-on-insulator (SOI).Described dielectric layer is the dielectric layer that is used for final metal layer, and can utilize chemical vapor deposition (CVD), spin (spin on), similar technology or their combination and form.Described dielectric layer is a kind of dielectric material that can not react basically in being exposed to air the time, and such as being silicon dioxide by utilizing the former silane of tetraethyl (TEOS) gas to make.In one embodiment, the thickness of dielectric layer is 0.1 to 1 micron.In one embodiment, the thickness of the opening 9 between grooving 14 and the grooving 14 is identical, and in another embodiment, the Breadth Maximum of grooving 14 is no more than about 4 microns.In one embodiment, grooving 14 is a kind of insulating material.Useful is that described grooving and area of isolation 12 are same material, because so only need to carry out a deposition run and a patterned process.If grooving 14 is a different materials with area of isolation 12, can need so more than a kind of dielectric material is carried out deposition run and patterned process, increased the cycle of manufacturing process.
After be shaped grooving 14 and area of isolation 12, one first barrier layer (not shown) can be shaped on described substrate surface.In one embodiment, first barrier layer is the right thick tantalum layer of 400 Izods that utilizes PVD technology to make.Other refractory metal and their nitride such as TiN, Ti and TaN, also can be used as first barrier layer.Selectively, can use atomic layer deposition (ALD) technology or alternate manner.An inculating crystal layer (seed layer) (not shown) can be shaped on first barrier layer.In one embodiment, described inculating crystal layer is the copper layer that utilizes PVD to form, and its thickness is approximately 800 to 1500 dusts.
As shown in Figure 2, be formed with a metal level 16, preferably copper layer on the area of isolation 12, between the grooving 14 and on the grooving 14.If select to have used first barrier layer and inculating crystal layer, metal level 16 also will be positioned on them so.In one embodiment, metal level 16 is copper layer and copper gasket, and they are deposited between described functional part or the grooving 14 and on them.Also can use other electric conducting material, such as the alloy of tungsten and copper.Metal level 16 utilizes to be electroplated or other appropriate process formation.The thickness of metal level 16 must be made into to equal at least the height of opening 9.In one embodiment, the deposition thickness of copper is 8000 dusts.
After the metal level 16 that has been shaped, part metals layer 16 is removed such as utilizing planarizing process, so as to go out as shown in Figure 3 like that, form mosaic texture 18 or metallic region 18.In general, metal level 16 obtains metallic region 18 through chemical mechanical polish process, and metallic region 18 has together formed pad 100 with grooving 14.Selectively, metal level 16 can obtain metallic region 18 through etch processes in dark.At metal level 16 is among the embodiment of copper layer and copper gasket, and copper layer and copper gasket form an even curface basically through planarizing process, and this flat surface comprises the top surface of copper gasket and the top surface of each grooving 14.Metallic region 18 and grooving 14 are the parts in pad 100 or the welding disking area 100.
As shown in Figure 4, after the pad 100 that has been shaped, a passivation layer 20 is shaped on pad 100 and area of isolation 12.This passivation layer 20 can be silicon nitride, silicon oxynitride, similar material or their combination, and can utilize CVD, PVD, similar technology or their combination and form.Have been found that the thick silicon oxynitride of silicon nitride that 500 dusts are thick and 4500 dusts is very effective as passivation layer 20.Next, what go out as shown in Figure 5 is such, utilizes photoresist that passivation layer 20 is carried out patterned process, and it is carried out etch processes, comes to form on the part of pad 100 at least opening 90.A kind of fluorine-containing chemical substance is such as CF 4, can be used to passivation layer 20 is carried out etching.In one embodiment, opening 90 utilizes a kind of etching-ashing-etch process (etch-ash-etch process) to form, and means at first to carry out etching for the first time, carries out ashing subsequently, then carry out etching for the second time, etching for the second time can be identical with the etching first time or different.Also can use the method for other opening 90 that is suitable for being shaped.
In one embodiment, carrying out after photoresist that etching for the first time forms the part of opening 90 and will be used for etching for the first time removes, on the whole surface of substrate 10, form a polyimide layer (not shown), and patterned processing comes on the pad 100 and can form opening on other zone.In order to form the remainder of opening 90, carry out etching for the second time.Can use with etching for the first time in the identical or different etch chemistries of used etch chemistries.Etch process will carry out etching to any zone that is not covered by polyimide layer for the second time.
As shown in Figure 5, in shaping opening 90, in order to make grooving 14 be depressed in the below of the top surface of metallic region 18, carried out etching (over etch), in one embodiment, metallic region 18 is a copper gasket.In the embodiment that has passivation layer 20, cross etching and be used for guaranteeing that passivation layer 20 is removed from opening 90 fully, so that carry out follow-up wire bond operation.The height of described copper gasket is greater than the height of described a plurality of functional parts or grooving 14, and at the groove 15 that forms on the grooving 14 between grooving height and copper gasket height.Groove 15 is at least the 100 Izod right sides, and more particularly, is at least the 600 Izod right sides.Can be sure of that as those of ordinary skill in the art the degree of depth of groove 15 can not surpass the height of grooving 14.In one embodiment, the degree of depth of described groove is between 100 dust to 2000 dusts, perhaps more particularly, is between 600 dusts and 2000 dusts.
Desirablely be, the degree of depth of groove 15 is enough to make that probe will slide along the top of grooving 14, and come in contact with metallic region 18 when probe 80 is applied on the part of pad 100, and what go out as shown in Figure 5 is such.Described groove also can allow any chip that is accumulated on the probe 80 to split away off, and falls at least one groove 15 or struck off from the top of grooving 14.In addition, the existence of grooving 14 has prevented to come in contact as the bottom of the metallic region 18 in probe in the prior art 80 and the pad 100, and to the metallic region 18 parts removal that the major general touched, in described prior art, do not use grooving and can cause being used for the contact area of wire bond operation less.
Use the pad of grooving and metallic region coplane to prevent that pad from thoroughly being pierced through, fully contact between probe and the metallic region in order to guaranteeing.In addition, grooving and probe come in contact can form non-conductive chip, they can adhere on the tip of probe, and increase the ability that impaired possibility of pad or reduction and metallic region 18 electrically contact.
As can be as seen from Figure 5, in one embodiment, probe 80 directly and the parts of pad 100 come in contact, mean that probe will can not come in contact via the described part on intermediate layer and the pad 100.
After the groove 15 that has been shaped, optionally be shaped on grooving 14 and metallic region 18 one second barrier layer 22 or corrosion barrier layer 22 prevent that pad 100 is subjected to oxygen-containing atmosphere or corrosive environment.In one embodiment, second barrier layer 22 is the thin glass materials by CVD or spin deposit.For example, second barrier layer 22 can be a kind of material that comprises silicon, carbon, oxygen and hydrogen, such as with Kulicke ﹠amp; The film that the anti-oxidation process combination of the OP2 (SM) of Soffa Industries Inc. is sold.The thickness on second barrier layer 22 is less than the height of groove 15.In one embodiment, second barrier layer 22 is less than about 100 dusts.
Selectively, second barrier layer 22 can be a kind of corrosion inhibitor that is solid, colloid or liquid form.When using the corrosion inhibitor of liquid, this corrosion inhibitor is stored local at least groove 15 of filling on the grooving 14.By using a kind of corrosion inhibitor of liquid, groove 15 can be as the memory of described liquid, because the wettability of described liquid and metallic region 18, described liquid can disappear as time goes by.Therefore, the corrosion inhibitor that evaporates from metallic region 18 top surfaces can be replenished by the liquid corrosion inhibitor that comes from groove 15 as time goes by, up to there not being liquid.The amount that can be kept at the liquid corrosion inhibitor in each groove 15 is a function of groove 15 volumes on the grooving 14.The time that need prevent metallic region 18 catalytic oxidation environment is long more, just need many more liquid corrosion inhibitor, and the volume of groove 15 just must be big more.Will recognize that as those of ordinary skill the volume of groove 15 depends on the height of groove 15 and the diameter or the width of groove 15.
In another embodiment, second barrier layer 22 is a kind of flux (flux), and it can comprise chloride or fluoride.Usually, described flux is heated, and remove any corrosion phenomenon that on metallic region 18, has taken place by etching operation.Then, as what will be explained further below, described flux can evaporate in the wire bond operation or be replaced by spheroid basically, and described spheroid is the part in the wire bond portion.
If do not form second barrier layer 22, so can be before wire bond operation under nitrogen, hydrogen, argon gas or similar atmosphere the pre-clean process of operative norm.Selectively, opening 90 can keep completely cutting off with oxygen or being exposed in the oxygen in minimum mode.
After the be shaped pad 100 and second barrier layer 22, if desired, Semiconductor substrate 10 is connected on the enclosed chip (not shown), and heated, so that with at least one pad 100 wire bond on Semiconductor substrate 10, perhaps be molded on the pad that is positioned on the enclosed chip, be electrically connected so that between them, form.In one embodiment, in order to form wire bond portion, squeeze out a wires, and heated subsequently, so that form a spheroid in the end of this metal wire.Then, using an anvil or annulus pin that described spheroid and metal wire are pulled is pulled on the pad 100.Utilize described annulus pin in wire bond portion 24, to apply ultrasonic energy and pressure,, mean that metal wire or wire bond portion 24 can not come in contact via the described part on intermediate layer and the pad 100 so that wire bond portion 24 is directly bonded on the pad 100.In one embodiment, wire or wire bond portion 24 directly are connected on the top surface of copper gasket, wherein " directly " have and aforesaid identical implication.Final structure is shown in Figure 7.Wire bond portion 24 can be spherical in shape, wedge shape or any other suitable shape.
If used second barrier layer 22 and be a kind of corrosion inhibitor, so its can be only before the wire bond operation or among exist.Selectively, if used a kind of flux as second barrier layer 22, so this flux can be before wire bond operation, among or exist afterwards.Usually, flux disappears in the process with the corrosion inhibitor removal in wire bond operation and heating.But, if use a kind of glass as second barrier layer 22, so this glass will be before wire bond operation or among exist.In this embodiment, when wire bond portion 24 is applied on second barrier layer 22, can chap in the corner of metallic region 18 in second barrier layer 22, and as time goes by, the remainder on second barrier layer 22 also can chap, and progressively splits away off from metallic region 18 or grooving 14.Can be so that final products have second barrier layer 22 after the wire bond operation, even second barrier layer 22 is used in the procedure.Therefore, in one embodiment, second barrier layer 22 or corrosion barrier layer are pierced through by wire or wire bond portion 24 in the process that wire is connected.In another embodiment, corrosion barrier or barrier layer 22 are carrying out being removed in the attended operation to wire or wire bond portion 24.
Figure 8 illustrates " landformization " view of pad 100, this pad 100 comprises that a plurality of functional parts and one are looped around the metal level around described a plurality of functional part, and this metal level can be a copper.In shown embodiment, the grooving 14 that reveals is made into to be arranged as the pattern of row, and surrounded by metallic region 18; Also can use the grooving 14 of any other pattern or any number.But the area of the metallic region 18 that comes in contact with wire bond portion 24 must be at least 34% of pad 100.In addition, grooving 14 can be Any shape, such as rectangle, square or cylindrical.
The metal pad that finally has the grooving that caves in that is shaped is useful, because groove 15 has increased the reliability of probe and wire bond operation, alleviated because the polishing depressed phenomenon that chemico-mechanical polishing caused, and the thorn in-degree of control probe 80 in pad 100 limits pad 100 thus and is damaged in detection process.Described groove also allows any chip that accumulates on the probe 80 to fall at least one groove, thus probe 80 is cleaned.In addition, can to allow metal to still have after repeatedly repeating to survey residual for groove 15.After surveying, especially repeatedly survey the afterwards still residual metal that has, increased the reliability and the simplicity of wire welding tech.In addition, because the landform pattern that caused of groove 15 helps to carry out the wire bond operation,, groove 15 can be attached to metal surface area on the metallic region 18 admittedly because having increased wire bond portion 24.Also have, described landform pattern allows the glass barriers on metallic region 18 and the grooving 14 to be easier to rupture, and has strengthened the electrically contacting property of weld strength and weld part.
In the description in front, invention has been described with reference to specific embodiment.But those skilled in the art will be appreciated that, under the condition that does not break away from the protection range of the present invention of stating in the claims, can carry out various improvement and change.Therefore, specification and accompanying drawing should be counted as purpose of illustration, and are not in a limitative way, and wish all this improvement are included within protection scope of the present invention.
Benefit, other advantage and issue-resolution are described in front at specific embodiment.But, benefit, advantage, issue-resolution and any meeting cause producing or the member of clear and definite any benefit, advantage or solution, all are not used in key, necessity or the essential characteristic or the member that constitute in any claim or all authority requirement.As used in this, term " comprises " " comprising " or any similar term, all being used to cover a kind of non-exclusionism comprises, such as a kind of technology, method, article or equipment that comprises one group of member, not only comprise these members, and can comprise and clearly not listing or intrinsic other member for this technology, method, article or equipment.

Claims (6)

1. method of producing pad (100) on Semiconductor substrate (10) comprises:
On this Semiconductor substrate, form a dielectric layer (12);
Dielectric layer (12) is carried out patterned process, to form a plurality of functional parts (14) in the welding disking area on this dielectric layer (12);
A copper layer of deposit (16) between the top of dielectric layer (12), a plurality of functional part (14) and on a plurality of functional part (14);
Copper layer (16) is carried out chemical mechanical polish process, to form an even curface, this surface is made up of the top surface that appears top surface and copper layer (18) of a plurality of functional parts (14), and the top surface of copper layer (18) is used for directly receiving a probe (80) after through etching in dark;
Described a plurality of functional parts (14) are carried out dark interior etching, in through etched copper layer in dark, to form groove (15); And
On through etched copper layer in dark and in the described groove, form a barrier layer (22).
2. the method for claim 1 also comprises:
On described Semiconductor substrate, form a passivation layer (20); With
In carrying out deeply, before the etch processes, form at least one local opening (90) in the passivation layer on described welding disking area (20).
3. method as claimed in claim 2 also comprises:
On described passivation layer, form a polyimide layer; With
In carrying out deeply, before the etch processes, form at least one local opening in the polyimide layer on described welding disking area.
4. method that is used to produce semiconductor structure comprises:
A Semiconductor substrate (10) is provided;
Go up the dielectric layer (12) that is shaped in this Semiconductor substrate (10);
Dielectric layer (12) is carried out etch processes, in a welding disking area, to form a plurality of functional parts (14);
Go up cement copper (16) at dielectric layer (12), form a copper layer (16) to go up at this dielectric layer (12), and between described functional part (14) with and go up and form copper gasket (18);
Remove part copper layer (16) and copper gasket (18), to form an even curface, this surface comprises the top surface of copper gasket (18) and the top surface of each functional part (14);
To described a plurality of functional parts (14) processing of caving in, be lower than the groove (15) of copper gasket (18) top surface with formation; And
A lead (24) is directly connected on the top surface of copper gasket (18).
5, a kind of method that is used to produce semiconductor structure comprises:
A Semiconductor substrate (10) is provided;
Go up a formation dielectric layer (12) in this Semiconductor substrate (10);
Dielectric layer (12) is carried out etching, in a welding disking area, to form a plurality of functional parts (14);
Go up cement copper (16) at dielectric layer (12), form a copper layer (16) to go up at this dielectric layer (12), and between described functional part (14) with and go up and form copper gasket (18);
Copper layer (16) and copper gasket (18) are carried out planarizing process, to form an even curface, this surface comprises the top surface of copper gasket (18) and the top surface of each functional part (14), and wherein the top surface of copper gasket (18) is used for directly receiving a probe (80); And
To a plurality of functional parts (14) processing of caving in, form the groove (15) of the top surface that is lower than copper gasket (18).
6. method as claimed in claim 5 also comprises a probe (80) is directly affacted on the top surface of copper gasket (18).
CNB028178254A 2001-09-14 2002-08-20 Method of forming a pad having a recess Expired - Lifetime CN1296980C (en)

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TW559965B (en) 2003-11-01
CN1554116A (en) 2004-12-08
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KR100896141B1 (en) 2009-05-12
US20030054626A1 (en) 2003-03-20
US6531384B1 (en) 2003-03-11
JP2005522019A (en) 2005-07-21
WO2003025998A2 (en) 2003-03-27
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KR20040035779A (en) 2004-04-29
JP4451134B2 (en) 2010-04-14

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