CN1294495C - Simulator structure method - Google Patents
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- CN1294495C CN1294495C CNB2004100091045A CN200410009104A CN1294495C CN 1294495 C CN1294495 C CN 1294495C CN B2004100091045 A CNB2004100091045 A CN B2004100091045A CN 200410009104 A CN200410009104 A CN 200410009104A CN 1294495 C CN1294495 C CN 1294495C
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Abstract
The present invention provides a simulator structure method which belongs to the field of simulators of computer software. The method provides a universal simulator frame which does not depend on a target hardware platform; the frame can describe files according to simulators provided by users, and automatically judge and execute the needed action for the simulators. The users only need to input the files described by the simulators to the simulators, and the simulators can completely simulate the action executed on the target hardware platform. The simulators describe the files by description language which calculates on the basis of attributes to compile; the description language is divided into two layers which are respectively used for the description of attribute trees of the target hardware platform and the attributes of nodes on the attribute trees; the users can freely change and expand the attribute trees and the attributes of the nodes of the attribute trees; and thereby, the extendibility and the flexibility of the simulators are greatly improved.
Description
Technical field
The invention belongs to field of computer software simulator technology, be specifically related to a kind of simulator structure method that is used for the simulated target hardware platform.
Background technology
Simulator technology is an important technology that is used for new hardware platform exploitation and new operating system exploitation.It is to simulate the hardware capability of realizing target platform by software.At present, known simulator structure is made up of instruction fetch, decoding and three parts of instruction execution.Target program is offered simulator program as input, and target program is carried out in the behavior of simulator program simulation real hardware, makes execution result with the same on real hardware.But, present simulator often can only be simulated at a kind of architecture, that is to say, if the target hardware platform of change simulation, just need significantly revise at this new target platform the simulator source program, regenerate new simulator then, the non-constant of extensibility.Though there is the simulator of minority that the target platform configurability can be provided, need recompilate the simulator code according to the target configuration file, very flexible is unfavorable for user's development.
Summary of the invention
The present invention overcomes existing simulator poor expandability, shortcomings such as dirigibility deficiency, a kind of simulator structure method is provided, the user only needs to provide the target hardware platform description document to the simulator generation module, need not change the code of simulator generation module itself, just can carry out all types of target program, and can on simulator, move complete operating system at the real hardware exploitation.
Technology contents of the present invention: a kind of simulator structure method, its step comprises:
(1) user writes the target hardware platform description document according to the target hardware platform that simulated, this description document comprises: the description of the description of target hardware platform attribute tree and the nodal community of this attribute tree, it is target hardware platform information instruction components of system as directed, attribute tree with target hardware platform is described, and the characteristic of target hardware platform information as attribute definition on the node of attribute tree;
(2) the simulator generation module is analyzed the description of the target hardware platform attribute tree in the target hardware platform description document, obtains the target hardware platform attribute tree, generates the decoding framework of simulator and carries out framework according to this attribute tree;
(3) the simulator generation module carries out property calculation according to the description of the attribute tree nodal community in the target hardware platform description document, generates actual decoding action and carries out action;
(4) the simulator generation module will be deciphered action and carry out action and be filled into the decoding framework of simulator and carry out in the framework and generate simulator.
OR rule and AND rule are adopted in the description of described attribute tree, from the root definition, set up subtree according to the OR rule, set up the orderly tuple of intranodal according to the AND rule.
Described attribute tree nodal community comprises: the semanteme time of running of operation, the grammer of assembly language and the value that each territory of instruction word is set.
The target hardware platform description document is carried out following description to target hardware platform, comprising:
(1) whole storage system classification comprises internal memory, register file etc.;
(2) data type that can directly support of machine;
(3) the various situations of alignment constraint;
(4) form of all instructions and effect;
(5) all addressing mode;
(6) use of machine conditions sign indicating number;
(7) the various possibility situations of program control flow;
(8) structural unit of inter-process.
Be provided with the decoding buffer zone in the decoding framework, the instruction after the decoding is left in this buffer zone with certain representation, when carrying out this instruction once more, only need directly to use, reach once decoding, nonexpondable function.
The Simulation execution of carrying out in the framework partly adopts the code chain connection technology, and in the instruction simulation implementation, an instruction is finished, and directly jumps to next bar instruction (continuing to carry out), realizes the link of instruction.
Technique effect of the present invention: the present invention has adopted a universal simulator generation module that does not rely on target hardware platform, the simulator generation module generates simulator decoding framework and carries out framework by the attribute tree definition of analyzing in the description document, and the action in this simulator decoding framework and the execution framework, then according to the attribute definition of each node of attribute tree in the description document, utilize property calculation dynamically to generate, with decoding action with carry out action and be filled into the decoding framework of simulator and carry out in the framework, just can realize whole simulations of goal systems hardware.Because this simulator generation module can be simulated target hardware platform automatically according to the target hardware platform description document that the user provided, the everything of simulated target hardware is with the hardware platform onrelevant.For any target hardware that needs simulation, do not need the simulation generation module is partly done any change, only need provide the corresponding target hardware platform description document of target platform to get final product.That is to say that all target platforms all only need this identical simulator generation module, it can carry out the simulation of target platform automatically according to the target hardware platform description document that the user provides.Need not the work that any recompility and code generate.Simultaneously, the target hardware platform description document adopts and writes based on the description of property calculation, this description document is respectively applied for the description to each nodal community on target hardware platform attribute tree and this attribute tree, the user can freely change and extended attribute is set and the attribute of each node of attribute tree, thus the extensibility and the dirigibility that have improved simulator greatly.
Description of drawings
Below in conjunction with accompanying drawing, the present invention is made detailed description.
Fig. 1 is a simulator attribute tree synoptic diagram;
Fig. 2 is the automatic generating portion process flow diagram of simulator;
Fig. 3 is a simulator application example synoptic diagram.
Embodiment
Adopt the present invention, user can independently select the hardware that simulated, only need write a target hardware platform description document,, both can carry out simulation target platform as the input that simulator generates to target platform.The present invention need obtain the following information content of target platform: whole storage system classifications comprises internal memory, register file etc.; The data type that machine can directly be supported; The various situations of alignment constraint; The form of all instructions and effect; All addressing modes; The use of machine conditions sign indicating number; The various possibility situations of program control flow; The structural unit of inter-process, for example streamline.According to the hardware description of these target platforms, the description of the system features that gets instruction, instruction classification and every instruction feature.Wherein, target hardware platform information instruction relevant portion can describe with the attribute tree of target hardware platform, and other characteristic of target hardware platform can be used as attribute definition on the node of this attribute tree.Target hardware platform description document of the present invention has adopted a kind of simulator based on property calculation to describe, and this description provides two main rules: OR rule and AND rule, they provide orthogonalized portrayal ability to description.The AND rule definition combined effect of each characteristic, and the OR rule definition diversity performance of single characteristic, be reflected in the former is a plurality of Attribute domains of instruction word in the description of order set, the OR rule then shows as the different values of individual domain, and for example operational code is add or sub etc.The grammer of this description is not allow recursive definition, like this, from the angle of grammer, this descriptive language must have terminal point about any derivation of a nonterminal symbol, and terminal symbol has been represented four class things in this language: data expression form, storage class, class of operation and addressing mode.This is quite representative, because this four category feature is quite abundant for the semanteme of describing order set, thereby all strings that this description is derived are exactly the order set definition that is described system.Described a series of property values, they are endowed the nonterminal symbol of description, have reflected the different aspect of instruction semantic.These property values are expressed by similar C linguistic expression or some statement sequences, are called the attribute expression formula.Wherein can quote property value by the parameter-definition of AND rule.
Description to the attribute tree of target hardware platform among the present invention defines from root op, set up subtree according to the OR rule, set up the orderly tuple of inter-node according to the AND rule, each leaf node is exactly the instruction of a reality, from a leaf node to the path of root, each node all comprises some attributes that are mutually related, and certain attribute successively is deployed into this attribute description that leaf node just can obtain command adapted thereto according to describing from root.Description is divided into two-layer, and the attribute tree that the upper strata is described target hardware platform is described; The attribute that lower floor is described each node on the attribute tree is described.
By the description of the target hardware platform attribute tree in the target hardware platform description document is analyzed, can obtain the target hardware platform attribute tree, with reference to figure 1, this attribute tree is mainly used in the structure of describing the target platform order set.Its representation can adopt following method definition, the beginning of Tree representation attribute tree definition, and the title of this attribute tree root node is followed in the back, and the title back is [] or (), the definition of this node of content representation in the bracket.For each node (comprising root node) on the attribute tree, or be a leaf node, represent, or be a subtree, add () or [] expression with node name with node name.If it is a node that expression connects, with () expression, each child node that the usefulness ", " of () the inside connects is an annexation, and this node is formed by connecting by the part in the bracket in other words; If it is a node that expression is selected, then use [] expression, the content representation choice relation that the usefulness ", " of [] the inside connects, this node is one of them of each several part in the bracket in other words.For leaf node, its lower floor no longer includes node.
Each node on each simulator attribute tree can have the attribute of oneself, and the user can be according to the nodal community of the autonomous defined attribute tree of the characteristic of target platform.Three kinds of base attributes that the present invention has described predefine: with action, syntax and image, expression respectively: the semanteme time of running of operation, the grammer of assembly language and the value that each territory of instruction word is set.Because each nodal community is extendible, the user is used to represent oneself special-purpose by adding new attribute.Adopt double-layer structure owing to describe, be respectively applied for the structure of description target hardware platform attribute tree and the attribute definition of each node on this tree, in the target hardware platform description document, the definition of attribute tree and the definition of attribute separate, both changes and expansion all are independent of each other like this, have improved the extensibility and the dirigibility of simulator greatly.
According to above-mentioned target hardware platform attribute tree, the simulator generation module can generate simulator decoding framework and simulator is carried out framework, but the action in the framework is not filled, but property calculation is carried out in the description of the attribute tree nodal community in the target hardware platform description document, result according to property calculation generates actual decoding action and carries out action then again, with decoding action with carry out action and be filled into the decoding framework of simulator and carry out in the framework, thereby form simulator.Be provided with the decoding buffer zone in the decoding framework, the instruction after the decoding is left in this buffer zone with certain representation, when carrying out this instruction once more, only need directly to use, reach once decoding, nonexpondable function.The Simulation execution of carrying out in the framework partly adopts the code chain connection technology, and in the instruction simulation implementation, an instruction is finished, and directly jumps to next bar instruction (continuing to carry out), realizes the link of instruction.
With reference to figure 2, the basic procedure of simulator structure of the present invention is as follows:
1, writes the target hardware platform description document according to the target hardware platform that simulated;
2, the simulator generation module is analyzed the description of the attribute tree in the target hardware platform description document, generates the decoding framework and carries out framework according to attribute tree, but action is not wherein filled;
3, the simulator generation module carries out property calculation to the attribute section in the target hardware platform description document, and generate actual decoding action and carry out action,
4, the simulator generation module will be deciphered action and carry out action and be filled into the decoding framework of simulator and carry out in the framework, and like this, the simulator of target platform has just generated substantially.
With reference to figure 3, the user with compiled operating system map with elf formatted file 1 and the target hardware platform description document 2 that is used to describe target hardware platform offer simulator generation module 4, and undertaken alternately by external debugger 3 and simulator generation module.After the simulator generation module obtains the target hardware platform description document, according to the simulator 5 that in the description document description of simulator and attribute is generated corresponding target hardware platform.The simulator 5 that generates is input with operating system image file 1, target hardware platform is simulated the executive operating system code.Debugging and performance evaluation module 6 obtain the data that need alternately by simulator generation module 4 and the simulator 5 that generates, and return to user's execution result and analysis data 7 by simulator generation module 4.
Claims (6)
1, a kind of simulator structure method, its step comprises:
(1) user writes the target hardware platform description document according to the target hardware platform that simulated, this description document comprises: the description of the description of target hardware platform attribute tree and the nodal community of this attribute tree, it is target hardware platform information instruction components of system as directed, attribute tree with target hardware platform is described, and the characteristic of target hardware platform information as attribute definition on the node of attribute tree;
(2) the simulator generation module is analyzed the description of the target hardware platform attribute tree in the target hardware platform description document, obtains the target hardware platform attribute tree, generates the decoding framework of simulator and carries out framework according to this attribute tree;
(3) the simulator generation module carries out property calculation according to the description of the attribute tree nodal community in the target hardware platform description document, generates actual decoding action and carries out action;
(4) the simulator generation module will be deciphered action and carry out action and be filled into the decoding framework of simulator and carry out in the framework and generate simulator.
2, simulator structure method as claimed in claim 1 is characterized in that: OR rule and AND rule are adopted in the description of attribute tree, from the root definition, set up subtree according to the OR rule, set up the orderly tuple of intranodal according to the AND rule.
3, simulator structure method as claimed in claim 1 is characterized in that: the attribute of attribute tree node comprises: the semanteme time of running of operation, the grammer of assembly language and the value that each territory of instruction word is set.
4, simulator structure method as claimed in claim 1 is characterized in that: the target hardware platform description document is carried out following description to target hardware platform, comprising:
(1) whole storage system classification comprises internal memory, register file etc.;
(2) data type that can directly support of machine;
(3) the various situations of alignment constraint;
(4) form of all instructions and effect;
(5) all addressing mode;
(6) use of machine conditions sign indicating number;
(7) the various possibility situations of program control flow;
(8) structural unit of inter-process.
5, simulator structure method as claimed in claim 1 is characterized in that: be provided with the decoding buffer zone in the decoding framework, the instruction after the decoding is left in this buffer zone.
6, as claim 1 or 5 described simulator structure method, it is characterized in that: the code on-link mode (OLM) is adopted in the execution of carrying out dummy instruction in the framework.
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| CNB2004100091045A CN1294495C (en) | 2004-05-20 | 2004-05-20 | Simulator structure method |
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| CNB2004100091045A CN1294495C (en) | 2004-05-20 | 2004-05-20 | Simulator structure method |
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| CN1294495C true CN1294495C (en) | 2007-01-10 |
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Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100347683C (en) * | 2005-04-15 | 2007-11-07 | 清华大学 | Structure-irrelevant micro-processor verification and evaluation method |
| CN100407665C (en) * | 2005-07-19 | 2008-07-30 | 中兴通讯股份有限公司 | Analogue method based on custom-made multiple type net element |
| CN101408877B (en) * | 2007-10-10 | 2011-03-16 | 英业达股份有限公司 | System and method for loading tree node |
| CN103164305B (en) * | 2013-03-20 | 2018-03-13 | 青岛中星微电子有限公司 | A kind of method and device for automatically generating image processing module verification platform |
| CN114398086B (en) * | 2020-08-29 | 2022-11-25 | 华为技术有限公司 | Drive configuration management method, device, medium, equipment and system |
| CN112416571A (en) * | 2020-10-19 | 2021-02-26 | 杭州未名信科科技有限公司 | Resource management method, operating system and management device for industrial Internet of things nodes |
| CN113608823B (en) * | 2021-06-25 | 2024-05-17 | 天津津航计算技术研究所 | Reusable terminal simulator for file description |
| CN113515348B (en) * | 2021-07-16 | 2023-11-14 | 江苏师范大学 | Simulator modeling method and device based on opportunity action flow |
| CN115237807B (en) * | 2022-08-11 | 2024-02-06 | 小米汽车科技有限公司 | Program testing method, device and readable storage medium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1266513A (en) * | 1997-06-13 | 2000-09-13 | 艾利森电话股份有限公司 | Simulation of computer processor |
| CN1270348A (en) * | 1998-10-21 | 2000-10-18 | 富士通株式会社 | Dynamic optimizing target code translator for structure simulation and translating method |
| CN1482541A (en) * | 2002-09-10 | 2004-03-17 | 华邦电子股份有限公司 | Test model generating method and apparatus |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1266513A (en) * | 1997-06-13 | 2000-09-13 | 艾利森电话股份有限公司 | Simulation of computer processor |
| CN1270348A (en) * | 1998-10-21 | 2000-10-18 | 富士通株式会社 | Dynamic optimizing target code translator for structure simulation and translating method |
| CN1482541A (en) * | 2002-09-10 | 2004-03-17 | 华邦电子股份有限公司 | Test model generating method and apparatus |
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