CN1283057A - Single-carrier-frequeney transmitter of GSM base station - Google Patents
Single-carrier-frequeney transmitter of GSM base station Download PDFInfo
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- CN1283057A CN1283057A CN 99117048 CN99117048A CN1283057A CN 1283057 A CN1283057 A CN 1283057A CN 99117048 CN99117048 CN 99117048 CN 99117048 A CN99117048 A CN 99117048A CN 1283057 A CN1283057 A CN 1283057A
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Abstract
A single-carrier transmitter of GSM base station is composed of a GMSK signal modulation part consisting of FPGA, DUC, CPU, DAC and LPF, and upper mixing, filtering and amplifying part, and antenna. Said DUC consists of internal controller, shaping filter, digital frequency modulator, gain controller, interpolation filter, NCO2 unit, and orthogonal frequency mixer. SAid FPGA is composed of address latch and decoder, address, data and writing signal selector, test signal generator and differential encoder. It can eliminate the DC error and unbalanced amplitude and phase between I and Q, improve spectral quality, and increase system performance.
Description
The invention belongs to field of mobile communication, is the single-carrier-frequeney transmitter in the sender of a kind of GSM base station.
Gsm mobile communication system uses GMSK signal modulation system.The modulation system of the GSM base station single-carrier-frequeney transmitter in the prior art is divided into analog-and digital-two kinds of forms again.
Adopting the GMSK modulator in the GSM base station single-carrier-frequeney transmitter of full analogue modulation system is (the seeing K, Murota, K.Hirade, GMSKModulation for Digital Mobile Radio Telephony) that adopts phase-locked loop (PLL) mode to finish.After downlink data carried out pi/2 phase shift two-phase keying (BPSK) modulator to intercarrier signal, the phase-locked loop that meets certain requirements through a transfer function (PLL) had just obtained the GMSK modulated intermediate frequency signal again.Wherein the BPSK of the pi/2 phase shift phase change that makes each code element is ± π 2, then pass through the filtering of PLL after, obtain needed GMSK signal.Most critical is the transfer function of wanting well-designed PLL in this implementation method, makes the power spectrum of output satisfy the requirement of GSM standard.The effect of PLL is that the pi/2 phase shift bpsk signal is carried out phase place is level and smooth, the PLL output signal spectrum equals the frequency spectrum of pi/2 phase shift bpsk signal and the product of PLL transfer function, so the power output spectral shape of this GMSK modulator depends on the transfer function characteristic of PLL to a great extent, and because the discreteness of component parameter, the debugging of analog PLL is cumbersome, circuit stability is relatively poor, and the consistency of output GMSK modulation signal quality is difficult to control.
Making now with the most use in the single-carrier-frequeney transmitter of GSM base station is so-called " half digital modulation mode ".Its principle and the course of work are: downlink data is introduced into GMSK digital baseband formation circuit and forms digital I, Q signal, then I, Q signal obtain analog signal through corresponding D AC circuit respectively, obtain Simulation with I, Q baseband signal more respectively after LPF circuit low-pass filtering.By analogue quadrature moducator I, Q signal quadrature modulation are obtained the GMSK intermediate-freuqncy signal to intermediate frequency then.With respect to full analog-modulated, the advantage of this modulation system is because the GMSK baseband signal is to produce with the form of digital signal, and power spectrum can precise design, to satisfy the standard of GSM.And owing to directly be transferred to intermediate frequency by baseband signal and get on, signal center frequency can not produce drift yet.But it still has some intrinsic shortcomings:
1. the imbalance that before quadrature modulation, has amplitude and phase place between two parallel simulation branch roads of I, Q inevitably, and two branch roads all can have dc error;
2. quadrature modulator also can be introduced the unbalanced error of amplitude and phase place between I, the Q inevitably.The performance of these errors on intermediate-freuqncy signal after the modulation is: dc error can bring carrier residual, and amplitude and phase equilibrium error can be brought mirror image (monolateral property) remnants with respect to carrier wave.This can cause that all the whole transceiver error rate rises decreased performance.
3. owing to there are these errors, in the conventional modulated method, usually before quadrature modulation, the adjustment circuit of special dc error and amplitude phase error is arranged.This has just increased debugging work load.And because the discreteness of the components and parts electric parameter of each transmitter, can cause the inconsistent of quality between the product.
The purpose of this invention is to provide a kind of new GSM base station single-carrier-frequeney transmitter, this emission function overcomes the shortcoming of above-mentioned conventional modulated method, the imbalance of amplitude and phase place between the dc error of elimination I, Q and I, the Q.Improve the frequency spectrum quality of transmitter output, thereby improve system performance index.
GSM of the present invention base station single-carrier-frequeney transmitter, comprise GMSK signal modulating part, uppermixing, filtering, amplifier section, antenna, described GMSK signal modulating part comprises: FPGA is used for downlink data is carried out differential coding and Data Format Transform and has certain test function; DUC is used for the input data are modulated, and forms the GMSK signal; CPU is used for the various parameters of described DUC and transmitter are provided with; DAC is used for converting digital signal to analog signal; LPF is used for analog signal is amplified, and sends into uppermixing, filtering, amplifying circuit then.
Wherein DUC comprises internal controller, formed filter, frequency shift keying, gain controller, interpolation filter, plural NCO, quadrature mixing unit, I, Q adder after quadrature mixing, the adder of a level coupling.
Wherein the internal circuit of FPGA comprises: the address latch decoder, and selection control, address, data, write signal selector, the data/address bus transducer, machine sign indicating number generator, 0/1 alternate yard generator, four select a selector, differential encoder, 1to16 transducer.
Transmitter of the present invention also has one by the PLL chip, and another LPF, and the special-purpose phase-locked loop of 52MHz formed as oscillation source of the good VCXO of phase noise are used to DUC and DAC circuit that work clock is provided.
In the single-carrier-frequeney transmitter of GSM of the present invention base station, downlink data is introduced into the conversion that FPGA carries out differential coding and data format, enter the DUC circuit again and form the GMSK digital medium-frequency signal, digital medium-frequency signal converts analog if signal to through DAC, again after low-pass filtering, enter uppermixing, filtering, amplifying circuit and carry out mixing, filtering, amplification, last feed antenna emission.
Below in conjunction with accompanying drawing, describe the present invention.
Fig. 1 is the GSM base station single-carrier-frequeney transmitter block diagram that adopts full analog modulator.
Fig. 2 is the GSM base station single-carrier-frequeney transmitter block diagram that adopts half digital modulation mode.
Fig. 3 is a GSM of the present invention base station single-carrier-frequeney transmitter block diagram.
Fig. 4 is the detailed structure view of the DUC in the single-carrier-frequeney transmitter of GSM of the present invention base station.
Fig. 5 is the FPGA cut-away view in the single-carrier-frequeney transmitter of GSM of the present invention base station.
Fig. 1 is that the GSM base station single-carrier-frequeney transmitter of the full analog modulator of employing is that the signal that adopts phase-locked loop (PLL) mode to finish is transferred.Circuit comprises pi/2 phase shift two-phase keying (BPSK) modulator 101, local oscillator 102, by the phase-locked loop (PLL) that frequency mixer 103, low pass filter (LPF) 104, voltage controlled oscillator (VCO) 105 and feedback line are formed, uppermixing, filtering, amplifying circuit 106, antenna 107.Downlink data is after the intermediate frequency point-frequency signal of 101 pairs of local oscillators of pi/2 phase shift two-phase keying (BPSK), 102 outputs carries out pi/2 phase shift two-phase keying (BPSK) modulator, the phase-locked loop that meets certain requirements through a transfer function (PLL) has just obtained the GMSK modulated intermediate frequency signal again.Wherein to be the phase change that guarantees each code element be ± pi/2 to the BPSK of pi/2 phase shift, then pass through the filtering of PLL after, obtain needed GMSK signal.
Making now with the most use in the GSM base station transmitter is so-called " half digital modulation mode ", as shown in Figure 2.This transmitter comprises: the GMSK base band forms circuit 201, to DAC202/204 and the low pass filter 203/205 that I, Q signal carry out digital-to-analogue conversion, filtering respectively, quadrature modulator 206, uppermixing, filtering, amplifying circuit 207, antenna 208.Its course of work is: downlink data is introduced into the GMSK digital baseband and forms the digital I of circuit 201 formation, Q signal, then I, Q signal obtain Simulation with I, Q signal through corresponding D AC202/204 circuit conversion respectively, obtain Simulation with I, Q baseband signal more respectively after LPF circuit 203/205 low-pass filtering.By analogue quadrature moducator 206 I, Q signal quadrature modulation are obtained the GMSK intermediate-freuqncy signal to intermediate frequency then, behind uppermixing, filtering, amplifying circuit 207, be fed to antenna 208 emissions.
The shortcoming of above-mentioned two kinds of transmitters is pointed out in front, no longer repeats here.
Shown in Figure 3 is GSM of the present invention base station single-carrier-frequeney transmitter block diagram, and it comprises: GMSK signal modulating part, uppermixing, filtering, amplifier section 306, antenna 307, wherein GMSK signal modulating part comprises: FPGA 301, and DUC 303, CPU 302, and DAC 304, and LPF 305.
In the single-carrier-frequeney transmitter of GSM of the present invention base station, downlink data is introduced into FPGA 301 and carries out the conversion of differential coding and data format, enter DUC circuit 303 again and form the GMSK digital medium-frequency signal, digital medium-frequency signal converts analog if signal to through DAC 304, again after LPF 305 low-pass filtering, enter uppermixing, filtering, amplifying circuit 307 and carry out mixing, filtering, amplification, last feed antenna 307 emissions.
The signal quality of transmitter depends on the phase noise index of DUC 303 and DAC 304 work clocks to a great extent, and the frequency of this work clock is fixed, and need not change.The present invention has selected the good VCXO 310 of phase noise to produce this work clock as a special-purpose phase-locked loop of oscillation source and PLL 308 and LPF 309 compositions.In one embodiment, getting the intermediate-freuqncy signal frequency is 190MHz, and DUC 303 output signal frequency are elected 13MHz as.The frequency of DUC 303 and DAC 304 circuit working clocks is elected 52MHz as.The 13MHz reference clock input of the special-purpose phase-locked loop of this 52MHz is provided by system.When transmitter powers on, promptly be configured by the special-purpose phase-locked chip of 301 couples of 52MHz of FPGA by PU 302.After treating the phase-locked loop locking, just can begin DUC 303 has been configured.
In the single-carrier-frequeney transmitter of GSM of the present invention base station, DUC 303 is the keys that realize the modulation of GMSK digital intermediate frequency.The inside detailed structure of DUC 303 comprises internal controller 410 as shown in Figure 4, formed filter 401, frequency shift keying 402, gain controller 403, interpolation filter 404, plural number NCO 407, quadrature mixing unit 405,406, adder 408, cascade adder 409.
The operation principle of DUC 303 is: what provide control word and descending modulating data for DUC 303 is shared address and data/address bus, so before the downlink data modulation, will be provided with all DUC 303 internal control registers earlier.Formed filter 401 in DUC 303, frequency shift keying 402, gain controller 403, respectively there is a register plural NCO 407 inside, each register all has address separately, and setting up procedure is exactly to write required content by CPU302 in these registers.In these registers, write the different various parameters that word just can change output signal that are provided with, and need not change hardware circuit.(this is the origin of software radio title just, also is the advantage of software radio).These parameters comprise: control modulation system, signal frequency, signal amplitude, formed filter coefficient.
In case after setting is finished, just begin downlink data has been modulated.Its modulated process is:
1. downlink data is delivered to formed filter 401 through internal controller 410 earlier and is obtained instantaneous numerical frequency, and formed filter 401 is Gaussian filters of a band interpolation function.Signal by gaussian filtering filtering the time percent of pass also improved N doubly.N=2～16 are optional, are provided with by CPU, in a specific embodiment, choose N=16.Gaussian filter can be referring to the GSM05.04 standard.
2. this numerical frequency is added on the digital linear frequency modulator (FM MOD) 402 and produces I, Q digital baseband signal.If instantaneous numerical frequency is f (nT), then be output as:
i(nT)=cos(φ(nT)+θ)；
Q (nT)=sin (φ (nT)+θ); Wherein: φ (nT)=φ ((n-1) T)+T * f (nT); θ is a first phase, and T is the sampling period of numerical frequency, in a specific embodiment, gets T=3.69 μ s/16.
3. I, the Q digital signal of 402 generations of digital chirp device all multiply by mutually with the gain controlling word of gain controlling 403 and finish gain controlling;
4. the I after gain controlling, Q digital signal are delivered to an interpolation filter 404 and are made digital interpolation, and to improve data pass rate d doubly, promptly its sampling period becomes T from T
s: T
s=T/d, its interpolation d=2～128 of counting are adjustable, in a concrete example, get d=12.
5. the digital local oscillation signal of the I behind filtering interpolation, Q digital signal and plural NCO 407 outputs multiplies each other, and digital baseband signal is moved on the digital intermediate frequency, obtains the digital intermediate frequency signal of GMSK modulation;
Plural number NCO output:
Homophase road (real part): cos (2* π * f
c* nT
s)
Positive cross-channel (imaginary part): sin (2* π * f
c* nT
s) f wherein
cFor the digital intermediate frequency frequency, get 13MHz.It is as follows that digital baseband signal is moved (to digital intermediate frequency) computing in number:
Y (nT
s)=i (nT
s) * cos (2* π * f
c* nT
s)-q (nT
s) * sin (2* π * f
c* nT
s) y (nT
s) promptly be the tabular form of the digital signal of the last output of DUC.
6. the digital intermediate frequency signal of this road GMSK modulation can also and the digital intermediate frequency signal of the modulated GMSK modulation in other roads by 409 additions (being cascade function), obtain the GMSK digital intermediate frequency signal of overloading frequency.
Fig. 5 is the internal circuit configuration of FPGA 301, comprise: address latch decoder 501, selection control 502, address, data, write signal selector 509, data/address bus transducer 503, random code generator 504,0/1 alternate sign indicating number (0,1 yard alternately occurs) generator 505, four select a selector 506, differential encoder 507,1to16 transducer 508.
Downlink data carries out the conversion of differential coding and data format at FPGA301 detailed operation principle is:
1. finish 302 pairs of DUC 303 circuit of CPU Data Format Transform between necessary address latch, decoding and CPU 302 and the DUC 303 is set.
Because the address that word (comprising the coefficient of various control words and formed filter etc.) is set that DUC 303 is inner different is all different, so FPGA 301 will latch the address signal of CPU 302, decipher, these are finished by address latch decoder 501.Data format owing to CPU302 is 8BIT again, and the data of DUC 303 are 16BIT, so the transducer (be data/address bus transducer in Fig. 5) 503 of a 8BIT to 16BIT arranged between the two.
2. finish the switching of " pattern is set " and " data-modulated pattern ".
This switching is finished jointly by selection control among the FPGA 502 (a special 1BIT register) and address, data, write signal multichannel alternative selector 509.In selection control 502, write " 0 ", " pattern is set ", be provided with by 302 pairs of DUC 303 circuit of CPU; In this register, write " 1 ", " data-modulated pattern ", DUC 303 circuit are modulated input data signal.
3. finish the switching of " test pattern " and " mode of operation ".
According to what modulate is that test data or downlink data are divided into " test pattern " and " mode of operation " with " data-modulated pattern " again.Total following three kinds " test patterns " and a kind of " mode of operation ", this will select one MUX 506 to finish by one four, and its switching controls is finished by the S1S0 selector switch.
SlS0=00: select complete " 0 " sign indicating number or complete " l " sign indicating number test signal input (target is 0 among Fig. 5).According to the GSM05.04 standard, this moment, the output signal of DUC 303 circuit should be f
cThe point-frequency signal of+67.7kHz, f
cBe the digital signal IF-FRE that DUC 303 circuit are exported, f
cBe 13MHz.
S1S0=01: the test signal input of selecting 0/1 alternate yard generator 505 to produce.According to the GSM05.04 standard, this moment, the output signal of DUC 303 circuit should be f
cThe point-frequency signal of-67.7kHz, f
cBe the digital signal IF-FRE that DUC 303 circuit are exported, f
cBe 13MHz.
SlS0=10: the pseudo-random code test signal input of selecting random code generator 504 to produce.
S1S0=11: select downlink data to import as signal.Promptly work in " mode of operation ".
4. the conversion of the differential coding of downlink data and data necessary form.Differential coding is carried out according to the GSMO5.04 standard by differential encoder 507, and setting line data is d (n), and the signal behind the differential coding is
, then
Signal behind the differential coding remains the signal of 1BIT, and the DUC circuit can only receive the input of 16BIT, so also will there be a 1BIT to change to the transducer 508 of 16BIT.
The advantage of GSM of the present invention base station single-carrier-frequeney transmitter is:
1. formation and the orthogonal modulation owing to I, Q signal all is to finish with the form of data signal, Eliminate dc error and the width of cloth error that balances each other fully, improved performance indications;
2. the GMSK modulating part realizes with " Digital Way ", has reduced debugging work load, And improved the uniformity of product quality;
3. because the control portion of gain branch is that data signal is processed, make power control electricity Greatly simplify on the road.
Claims (4)
1. GSM base station single-carrier-frequeney transmitter, comprise GMSK signal modulating part, uppermixing, filtering, amplifier section (306), antenna (307), it is characterized in that, described GMSK signal modulating part comprises: FPGA (301), carry out differential coding and Data Format Transform and have certain test function the input data; DUC (303) modulates the input data, forms the GMSK signal; CPU (302) is provided with other parameters of various parameters of described DUC and transmitter; DAC (304) converts digital signal to analog signal; LPF or BPF (305), analog signal carried out filtering after, send into uppermixing, filtering, amplifying circuit (306).
2. the described GSM of claim 1 base station single-carrier-frequeney transmitter is characterized in that described DUC comprises: internal controller (410), and CPU (302) is provided with by the various parameters of internal controller (410) to DUC inside; Formed filter (401), described formed filter (401) are the Gaussian filters of a band interpolation function, are used for downlink data gaussian filtering that internal controller (410) is come out, convert the numerical frequency that the digital signal percent of pass is improved to; Frequency shift keying (402) becomes I, Q digital baseband signal with numerical frequency; Gain controller (403) is finished the gain controlling to digital signal; Interpolation filter (404) is made digital interpolation with digital signal, further improves data pass rate; Plural number NCO (407) and quadrature mixing unit (405,406), adder (408) is used for the digital modulation function to digital baseband signal is finished in the I of this DUC unit, Q signal digital quadrature modulation back addition, obtains the digital intermediate frequency signal of GMSK modulation; Cascade adder (409) can obtain overloading GMSK digital intermediate frequency signal frequently with the GMSK digital intermediate frequency signal addition (being cascade function) of a plurality of DUC chip outputs.
3. the described GSM of claim 1 or claim 2 base station single-carrier-frequeney transmitter, it is characterized in that the internal circuit of described FPGA comprises: address latch decoder (501) is used for the address of CPU (302) is latched, deciphered; Selection control (502), address, data, write signal selector (509) are that data, address signal, write signal (promptly " pattern being set ") or the modulating data, address, the modulating data that receive CPU squeezed into clock (i.e. " data-modulated pattern ") and switched to the DUC circuit; Data/address bus transducer (503) converts 8 bit data of CPU to 16 required bit data of DUC circuit; Random code generator (504) produces the random code test signal under " test pattern "; 0/1 alternate yard generator (505) produces 0 under " test pattern ", 1 alternate yard test signal; Four select a selector (506), finish the switching between three kinds " test patterns " and a kind of " mode of operation "; Differential encoder (507) is finished the differential coding of GSM05.04 standard defined; 1to16 transducer (508) is finished the format conversion of digital signal from 1BIT to 16BIT.
4. claim 3 requires described GSM base station single-carrier-frequeney transmitter, it is characterized in that, also has one by PLL chip (308), another LPF (309), the special-purpose phase-locked loop of the 52MHz that VCXO (310) forms, the 13MHz clock generating 52MHz point-frequency signal that it utilizes system to provide is for DUC (303) and DAC (304) provide work clock.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 99117048 CN1115909C (en) | 1999-08-26 | 1999-08-26 | Single-carrier-frequeney transmitter of GSM base station |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 99117048 CN1115909C (en) | 1999-08-26 | 1999-08-26 | Single-carrier-frequeney transmitter of GSM base station |
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| CN1115909C CN1115909C (en) | 2003-07-23 |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100438673C (en) * | 2006-03-21 | 2008-11-26 | 北京北方烽火科技有限公司 | Base station signalling generator and utilization for testing WCDMA system |
| CN101834818A (en) * | 2010-04-20 | 2010-09-15 | 广州市广晟微电子有限公司 | GMSK (Guassian Minimum Shift Keying) modulation device and method |
| CN102281068A (en) * | 2010-06-09 | 2011-12-14 | 承景科技股份有限公司 | System and method for generating test pattern with roaming reference line |
| CN101338665B (en) * | 2008-06-25 | 2012-04-18 | 中国海洋石油总公司 | High-frequency electromagnetic wave sending machine |
| CN103281092A (en) * | 2013-06-20 | 2013-09-04 | 阳光凯讯(北京)科技有限公司 | Modulating system and method for achieving multi-mode intelligent soft base station |
| CN103475413A (en) * | 2013-09-12 | 2013-12-25 | 成都成电光信科技有限责任公司 | Optical network data card capable of being configured by FPGA |
| CN106170779A (en) * | 2014-04-11 | 2016-11-30 | 高通股份有限公司 | For bus being carried out by superposition the system and method for FREQUENCY CONTROL |
| CN107659272A (en) * | 2017-09-21 | 2018-02-02 | 天津光电通信技术有限公司 | A kind of new up-converter circuit |
| CN115776429A (en) * | 2022-11-23 | 2023-03-10 | 苏州市江海通讯发展实业有限公司 | Method and system for generating 406MHz position indication intermediate frequency phase modulation signal |
-
1999
- 1999-08-26 CN CN 99117048 patent/CN1115909C/en not_active Expired - Fee Related
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100438673C (en) * | 2006-03-21 | 2008-11-26 | 北京北方烽火科技有限公司 | Base station signalling generator and utilization for testing WCDMA system |
| CN101338665B (en) * | 2008-06-25 | 2012-04-18 | 中国海洋石油总公司 | High-frequency electromagnetic wave sending machine |
| CN101834818A (en) * | 2010-04-20 | 2010-09-15 | 广州市广晟微电子有限公司 | GMSK (Guassian Minimum Shift Keying) modulation device and method |
| CN101834818B (en) * | 2010-04-20 | 2013-04-10 | 广州市广晟微电子有限公司 | GMSK (Guassian Minimum Shift Keying) modulation device and method |
| CN102281068A (en) * | 2010-06-09 | 2011-12-14 | 承景科技股份有限公司 | System and method for generating test pattern with roaming reference line |
| CN102281068B (en) * | 2010-06-09 | 2014-03-12 | 承景科技股份有限公司 | System and method for generating test pattern with roaming reference line |
| CN103281092B (en) * | 2013-06-20 | 2015-08-05 | 阳光凯讯(北京)科技有限公司 | A kind of modulating system and method realizing multi-mode intelligent soft base station |
| CN103281092A (en) * | 2013-06-20 | 2013-09-04 | 阳光凯讯(北京)科技有限公司 | Modulating system and method for achieving multi-mode intelligent soft base station |
| CN103475413A (en) * | 2013-09-12 | 2013-12-25 | 成都成电光信科技有限责任公司 | Optical network data card capable of being configured by FPGA |
| CN106170779A (en) * | 2014-04-11 | 2016-11-30 | 高通股份有限公司 | For bus being carried out by superposition the system and method for FREQUENCY CONTROL |
| CN107659272A (en) * | 2017-09-21 | 2018-02-02 | 天津光电通信技术有限公司 | A kind of new up-converter circuit |
| CN115776429A (en) * | 2022-11-23 | 2023-03-10 | 苏州市江海通讯发展实业有限公司 | Method and system for generating 406MHz position indication intermediate frequency phase modulation signal |
| CN115776429B (en) * | 2022-11-23 | 2024-04-30 | 苏州市江海通讯发展实业有限公司 | 406MHz position indication mark intermediate frequency phase modulation signal generation method and system |
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| Publication number | Publication date |
|---|---|
| CN1115909C (en) | 2003-07-23 |
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