CN1280881C - Deep infra micro MOS devices and its manufacturing method - Google Patents
Deep infra micro MOS devices and its manufacturing method Download PDFInfo
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- CN1280881C CN1280881C CN 02107868 CN02107868A CN1280881C CN 1280881 C CN1280881 C CN 1280881C CN 02107868 CN02107868 CN 02107868 CN 02107868 A CN02107868 A CN 02107868A CN 1280881 C CN1280881 C CN 1280881C
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Abstract
The present invention relates to a deep infra micro MOS device and a manufacturing method thereof. The manufacturing method comprises the following steps: a plurality of areas are formed in a silicon substrate and a first dielectric layer. Then, a second dielectric layer and a third dielectric layer are deposited on the silicon substrate fully. The third dielectric layer can be etched oppositely and selectively to form a plurality of side walls. The side walls are light covers, so a plurality of through holes are formed on the base part of the second dielectric layer. The through holes are filled by a filling dielectric layer and then etched again to form a plurality of dielectric columns. After the first dielectric layer and the second dielectric layer are removed, the dielectric columns are the light covers to form a plurality of electrically conductive grid electrodes. The manufactured grid electrodes by the manufacturing method have better accurate dimensions than grid electrodes manufactured by a manufacturing technique.
Description
Technical field
The present invention relates to a kind of deep sub-micron MOS device and manufacture method thereof, especially refer to that a kind of limiting value of present optics development manufacturing technology of utilizing expands it to the dimension of deep-submicron, can make the grid pattern size change in the mos device deposit more accurate manufacture method.
Background technology
In semi-conductor industry, the manufacturer of semiconductor device is faced with a pressure, because the electric loop design is more and more little in the integrated circuit, thereupon promptly is upgrading manufacture method and equipment thereof.In order to make transistor use existing manufacturing technology to make transistor reach the dimension of deep-submicron on manufacture method, thus, described transistorized qualification rate will become and be difficult to control.
The emphasis that improves optics developing technique commonly used is (phase-shift mask) such as the photoresistance that concentrates on the light source that uses shorter wavelength, improvement, phase shifting masks.These technology have their independent and advantage separately; Yet, inquire into other and still use at present and optics developing apparatuses of existing are very important, can make the semiconductor maker need not bear to buy the permium that new equipment brought and may interrupt problem such as production at present.
Summary of the invention
Main purpose of the present invention provides the modification method of a manufacturing deep sub-micron MOS device.Described method is to utilize the limiting value of present optics development manufacturing technology that it is expanded to the dimension of deep-submicron, can make the grid pattern size in the mos device become more accurate.Described method has disclosed the present invention can make the manufacturer of semiconductor device delay the update time of manufacture method equipment, and or can in general manufacture method device upgrade demand, save one or more middle fabrication schedules, thus, can lower the fund and the operating cost of purchase of equipment.
Below with a preferred embodiment so that the manufacture method of present invention to be described, its manufacture method is summed up and is summarized as follows described several steps:
(1) on wafer, forms a plurality of first active areas, and be spaced from each other with an insulation layer;
(2) form an interlayer dielectric layer, a conductive layer and one first dielectric layer in regular turn;
(3) utilize described first dielectric layer of optics development etching that a plurality of second active areas that correspond to each first active area are revealed;
(4) deposit second and third dielectric layer on wafer, wherein the rate of etch of the 3rd dielectric layer is for being different from first and second dielectric layer, and the gross thickness of second and third dielectric layer is the thickness less than first dielectric layer comprehensively;
(5) optionally etching the 3rd dielectric layer forms many oppose side walls (sidewall spacer), uses sidewall (sidewall spacer) to form a plurality of perforation as mask at second dielectric layer then;
(6) one of deposition is filled dielectric layer and is filled up the perforation that institute's second dielectric layer that is set forth in forms, and then etch-back is filled dielectric layer till bottom the described sidewall (sidewall spacer);
(7) optionally first and second dielectric layer is removed in etching, and described interlayer dielectric layer is not filled till the dielectric layer covering;
(8) utilizing remaining filling dielectric layer is as etching mask, makes described conductive layer change and forms a plurality of conductive grids; And
(9) remove filling dielectric layer and interlayer dielectric layer, utilize conductive grid to be masked in first active area then and carry out source electrode and drain electrode injection as one.
As mentioned above, major advantage of the present invention is the limiting value of extending common optics development manufacture method, and utilizes this method can make more common more accurate mos device.
Then, a plurality of extra dielectric layers are to be deposited on wafer surface in regular turn and comprehensively, the section of the dielectric layer of each comprehensive deposition is to be a plurality of hat-shaped structures, and its structure includes a protuberance that is positioned between two shoulders, and described protuberance is that first dielectric layer presents through first step etching; The sidewall of the dielectric layer of each comprehensive deposition can shorten the space between two adjacent dielectric teats.
Necessary condition of the present invention is the thickness that can not surpass first dielectric layer for the gross thickness of the dielectric layer of all comprehensive depositions.Another necessary condition be connect the back, outermost comprehensive dielectric layer has the rate of etch that differs from the dielectric layer that remains.To complete and the dielectric layer property deposition carries out multiple tracks class step, wherein can make the base portion of adjacent dielectric more approaching, can make the semiconductor device of making provide more common optics development manufacture method limiting value more excellent precise measure.Outermost each dielectric layer comprehensively can be selected, and annotates and anisotropy ground etching formation pair of sidewalls (described sidewall is positioned at the base portion of the second comprehensive dielectric layer).Afterwards, utilize described sidewall to be positioned at the residual comprehensive dielectric layer of described sidewall below with etching, to form a perforation as a mask.
At last, a filling dielectric layer that differs from the dielectric layer etch rate of comprehensive deposition is deposition and the space of filling up described perforation and two comprehensive deposit dielectric interlayers.Utilize sidewall to make the base portion of comprehensive dielectric layer change a plurality of stringers (for being lower than each sidewall bottom) of knowing into as the described filling dielectric layer of mask etch-back.After optionally etching removed described comprehensive dielectric layer, first dielectric layer and interlayer dielectric layer, each short stringer width was less than the defined active area of common optics development manufacture method.
The dielectric layer that uses described weak point then is as the mask that forms afterwards mos device, and manufacture method promptly of the present invention can be utilized the more accurate mos device of common optics development manufacture method.
For further understanding aforementioned creation purpose and detailed construction, the conjunction with figs. explanation as after.
Description of drawings
Fig. 1 is the generalized section of a part of manufacture method of the present invention, and it discloses first active area that a wafer is formed with a plurality of wellblocks, and wherein active area is to be separated by insulation layer;
Fig. 2 is the generalized section of another part manufacture method of the present invention, and its announcement is formed on grid conducting layer, conductive layer, interlayer dielectric layer and one first dielectric layer on the wafer; Wherein first dielectric layer utilizes the etching of optics development manufacture method to form a plurality of second active areas above first active area;
Fig. 3 is the generalized section of another part manufacture method of the present invention, it discloses a plurality of dielectric layers and is deposited on the wafer comprehensively, wherein each comprehensive dielectric layer is made up of hat-shaped structure, and each hat-shaped structure is to include a protuberance that is positioned at two shoulders of described comprehensive dielectric layer (for being formed by first dielectric layer);
Fig. 4 is the generalized section of a part of manufacture method more of the present invention, it is disclosed in the ground etching of outermost comprehensive deposit dielectric layer-selective and anisotropy and forms pair of sidewalls, and etching be positioned at residue in the sidewall below comprehensive dielectric layer to form a plurality of perforation;
Fig. 5 is another generalized section of manufacture method partly of the present invention, and it discloses one and fills dielectric layer deposition on wafer and fill up described perforation;
Fig. 6 is the generalized section of another part manufacture method of the present invention, and it discloses selectivity and anisotropy ground etch-back and removes the stringer (shoulder by comprehensive dielectric layer defines) that described filling dielectric layer and described the 3rd dielectric layer form the weak point of a plurality of filling dielectric layers;
Fig. 7 is the generalized section of a part of manufacture method more of the present invention, and after it was disclosed in the interlayer dielectric layer that removes comprehensive dielectric layer, first dielectric layer and below, a plurality of dielectric stringers were formed at the interlayer dielectric layer of described filling dielectric layer and below;
Fig. 8 is the generalized section of another part manufacture method of the present invention, and it discloses conductive layer and utilizes the dielectric stringer to form a plurality of dielectrics/conduction stringer as mask;
Fig. 9 is the generalized section of another part manufacture method of the present invention, and after its announcement removed the dielectric layer part, a plurality of conduction stringers formed a plurality of mos devices.
Embodiment
The present invention discloses a new deep sub-micron MOS device and a manufacture method thereof, is that to make the manufacturing dimension of deep sub-micron MOS (metal-oxide semiconductor) device have more common optics development manufacture method more accurate.Described method in the present invention can be to manufacturing equipment constantly under the upgrade requirement, make semiconductor manufacturer's delay to upgrade demand of manufacture method equipment, or in general upgrade requirement, save one or more how mesne uses, reach and save operation cost and cost of investment.
As mentioned above, one of major advantage of the present invention is the limiting value when extending the optics developing technique and be applied to make mos device, makes that described mos device will be better than former optics development manufacturing technology made mos device.Main important document of the present invention is summarized as follows:
(1) desires to reach purpose of the present invention, at first form multiple-active-region (that is: perforation at first dielectric layer, first dielectric layer of position above a conductive layer be long-pending in), these active areas form mos devices (as grid) and vertically opposite in silicon base the active area of mos device;
(2) a plurality of extra dielectric layers (or title " comprehensive dielectric layer ") are comprehensive in regular turn being deposited on the wafer surface, each comprehensive dielectric layer has the structure of a plurality of hats, and described structure is to include a protuberance that is positioned at two shoulders of described comprehensive dielectric layer (for being formed by first dielectric layer); The side wall layer of the comprehensive dielectric layer of each layer can make the space between between two dielectric layer insulating barriers dwindle gradually again, and the thickness that another important document of the present invention is described comprehensive dielectric layer can not surpass the thickness of first dielectric layer.
(3) another important document of the present invention be in the end, outermost comprehensive part dielectric layer must have and differ from lower floor dielectric layer residue rate of etch partly.Comprehensive dielectric layer of described outer most edge is selectively and the etching of incorgruous ground, and in order to form pair of sidewalls, described sidewall is the shoulder that is positioned at second comprehensive dielectric layer.Then, be positioned at the residual comprehensive dielectric layer of described sidewall below as mask etching, can form a plurality of perforation with sidewall.
(4) last; one fills dielectric layer; its rate of etch is different from those comprehensive dielectric layer (except that the dielectric layer of outer most edge); its deposition is also filled up in the described perforation and in the space of comprehensive deposit dielectric interlayer; utilize sidewall to be the described filling dielectric layer of mask etch-back; and change a plurality of short stringers in the base portion of comprehensive dielectric layer and (wherein be lower than the bottom of each sidewall; in the described comprehensive dielectric layer of etching optionally; behind first dielectric layer and the interlayer dielectric layer, the width of each weak point stringer (for residue part and the transformation of interlayer gasification layer by comprehensive dielectric layer form) is the optics development manufacture method dimension less than the active area of use in first dielectric layer.
Use these short dielectric layers as the mask that forms afterwards mos device then, manufacture method promptly of the present invention can utilize common optics development manufacture method to make mos device preferably.
So that the manufacture method of present invention to be described, its summary is summarized as follows several step with a preferred embodiment:
(a) form a plurality of first active areas on wafer, two adjacent first active areas are to intercept with insulation layer;
(b) on wafer, form an interlayer dielectric layer, a conductive layer and one first dielectric layer in regular turn;
(c) utilize described first dielectric layer of optics development etching to form second active area of a plurality of positions in the first active area vertical direction, first dielectric layer;
(d) second and third dielectric layer that on wafer, deposits comprehensively, wherein the rate of etch of the 3rd dielectric layer differs from first and second dielectric layer, and the gross thickness of second and third dielectric layer is the thickness less than first dielectric layer, moreover, these comprehensive dielectric layer have a plurality of hat-shaped structures, and these structures are to include a protuberance that is positioned at base portion top;
(e) tool anisotropy and optionally etching the 3rd dielectric layer is to form a plurality of sidewalls, each sidewall is in the upper end of the side and the base portion thereof of the second dielectric layer protuberance;
(f) utilize sidewall as mask, form a plurality of perforation in the second dielectric layer base portion;
(g) deposition one is filled dielectric layer between each perforation;
(h) etch-back is filled dielectric layer below described sidewall bottom;
(i) optionally first and second dielectric layer is removed in etching, anti-described interlayer dielectric layer is covered the unlikely dielectric layer that is filled;
(j) utilize remaining filling dielectric layer as etching mask, make conductive layer change a plurality of conductive grids into;
(k) remove filling dielectric layer and interlayer dielectric layer, utilize conductive grid then, to be pre-formed one source pole and drain electrode injection region at first active area as a mask;
The present invention will in following with reference to several examples to describe its more features.Only its illustrative purposes is described with preferred embodiment of the present invention, promptly with complete, correctly express the present invention the purpose being desired to reach.
Fig. 1 to Fig. 9 is disclosed in the main manufacture method step of mos device of the present invention, and the included detailed content of these accompanying drawings is as described below.
Fig. 1 discloses one and forms the wafer 10 of making mos device; It includes a plurality of first active areas 3 (promptly in silicon base 1 wellblock), and these first active areas 3 are separated by each insulating barrier 2.
Fig. 2 shows that gate dielectric 4, a conductive layer 5, an interlayer dielectric layer 6 and this first dielectric layer 7 are for being formed on the wafer; Be etched in described first dielectric layer etch is positioned at first active area, 3 tops with formation a plurality of second active areas 23 with an optics development manufacture method; Described gate dielectric is to be a silicon oxide layer, and described conductive layer is to be polysilicon layer, and described interlayer dielectric layer is to be silicon oxide layer, and described first dielectric layer is a silicon nitride layer.
Consult shown in Figure 3ly, disclose one second dielectric layer 8 and one the 3rd dielectric layer 9 is comprehensive being deposited on the wafer.Each comprehensive dielectric layer includes a plurality of hat-shaped structures, and described hat-shaped structure is to comprise that one is positioned at the protuberance 24 on the base portion 25.Being shaped as by first dielectric layer after the etching of described protuberance 24 formed, and wherein to be suitably for the material of silicon nitride layer and the 3rd dielectric layer be to be TEOS (tetraethylorthosilicate) to the material of the second layer.
Consult shown in Figure 4ly, show pair of sidewalls 26 by outermost comprehensive dielectric layer is formed with selectivity and anisotropy etching, and etching is positioned at the residual comprehensive dielectric layer in described sidewall below to form a plurality of perforation.
Consult shown in Figure 5, disclose one fill dielectric layer 11 for deposition on crystalline substance to fill up described perforation.The material of described filling dielectric layer 11 is suitably and is equal to the 3rd dielectric layer 9TEOS.
Consult shown in Figure 6, show that described filling dielectric layer is an etch-back optionally, (this defines for the shoulder 28 by comprehensive dielectric layer to stay a short stringer 27 after etch-back, the height of the short stringer 27 of meeting is also got rid of side wall layer for being lower than the sidewall bottom because filling dielectric layer and side joint layer are identical material, event etching manufacture method.
Consult shown in Figure 7, be disclosed in the interlayer dielectric layer 6 of removing described second dielectric layer, first dielectric layer and below after, a plurality of dielectric stringers 27 be erect type, each dielectric stringer 27 includes fills dielectric layer partly 12 and the interlayer dielectric layer part 6 of below.
Consult shown in Figure 8ly, show that described conductive layer 5 is to use dielectric stringer 27 as a mask, forms a plurality of dielectrics/conduction stringer 29 with etching.
Consult shown in Figure 9ly, after partly dielectric material partly is removed, promptly form dielectric side walls, see through ion and inject and form leakage/source area 21, a plurality of conduction stringers then form a plurality of mos devices 30.
In sum, be of the present invention specifying, but not in order to restriction the present invention, and the present invention really possessed aforementioned advantages, and also possessed obvious effect compared to existing method for semiconductor manufacturing and promote.
Claims (16)
1. deep sub-micron MOS device producing method is characterized in that it may further comprise the steps:
(a) on wafer, form a plurality of first active areas, and separate, then on silicon base, form a gate dielectric, a conductive layer, an interlayer dielectric layer and one first dielectric layer with a plurality of insulation layers;
(b) utilize described first dielectric layer of optics development etching to form a plurality of second active areas perpendicular to each first active area top;
(c) comprehensive deposition one second and third dielectric layer on silicon base, wherein the 3rd dielectric layer has a rate of etch that differs from first and second dielectric layer;
(d) selectivity and anisotropy ground etching the 3rd dielectric layer is to form a plurality of sidewalls;
(e) use described sidewall as mask, form a plurality of perforation with base portion at second dielectric layer;
(f) deposition one is filled dielectric layer to fill up described perforation, then optionally the described filling dielectric layer of etch-back to form a plurality of dielectric stringers;
(g) optionally the interlayer dielectric layer of described second and first dielectric layer and below is got rid of in etching; And
(h) use described dielectric stringer as etching mask so that conductive layer is transformed into a plurality of conductive grids.
2. deep-submicron MQS device producing method as claimed in claim 1, it is characterized in that, also include the filling dielectric layer and the interlayer dielectric layer that remove described conductive grid place, then re-use conductive grid as mask in order to form source electrode and drain electrode injection region at first active area.
3. deep sub-micron MOS device producing method as claimed in claim 1 is characterized in that, the gross thickness of described second and third dielectric layer is the thickness less than first dielectric layer.
4. deep sub-micron MOS device producing method as claimed in claim 1 is characterized in that described these comprehensive dielectric layer are formed by a plurality of hat-shaped structures, and each hat-shaped structure includes a protuberance that is positioned at base portion top.
5. deep sub-micron MOS device producing method as claimed in claim 4, it is characterized in that sidewall be formed at second dielectric layer protuberance sidewall and be positioned at the base portion top of described second dielectric layer.
6. deep sub-micron MOS device producing method as claimed in claim 1, it is characterized in that gate dielectric is that silicon gasification layer, described conductive layer are for a polysilicon layer, described interlayer dielectric layer are silicon oxide layers, and described first dielectric layer is a silicon nitride layer.
7. deep sub-micron MOS device producing method as claimed in claim 1, it is characterized in that second dielectric layer be for a silicon nitride layer and described the 3rd dielectric layer be to be a TEOS layer.
8. deep sub-micron MOS device producing method as claimed in claim 7, it is characterized in that filling dielectric layer is to be a TEOS layer, similar described the 3rd dielectric layer of rate of etch.
9. deep sub-micron MOS device is characterized in that including:
One wafer forms first active area, a gate dielectric, a conductive layer, an interlayer dielectric layer that separates with a plurality of insulation layers on it, and one first dielectric layer;
A plurality of second active areas perpendicular to each first active area top, get with optics development etching said first dielectric layer respectively;
One second and third dielectric layer is formed on the wafer in regular turn;
A plurality of sidewalls are formed at the second dielectric layer upper surface, get with selectivity and anisotropy ground etching the 3rd dielectric layer;
A plurality of perforation are formed at the base portion of this second dielectric layer, and the sidewall that its use is formed at second dielectric layer gets as mask;
One fills dielectric layer, is formed in the perforation of said second dielectric layer;
A plurality of dielectric stringers are formed on this conductive layer, with sequentially optionally etching part fill dielectric layer, second and first dielectric layer, up to described interlayer dielectric layer be not subjected to residue fill dielectric layer cover till and get; And
A plurality of conductive grids are formed on the wafer, and described dielectric stringer makes conductive layer be transformed into described a plurality of conductive grid as etching mask.
10. deep sub-micron MOS device as claimed in claim 9, each first active area that it is characterized in that wafer also includes one source pole injection region and drain electrode injection region, each injection region is by removing the filling dielectric layer and the interlayer dielectric layer at described conductive grid place, cooperate conductive grid as mask, inject and get at first active area.
11. deep sub-micron MOS device as claimed in claim 9 is characterized in that the thickness of the gross thickness of described second and third dielectric layer less than first dielectric layer.
12. deep sub-micron MOS device as claimed in claim 9 is characterized in that described second and third dielectric layer includes a plurality of hat-shaped structures, each hat-shaped structure includes a protuberance that is positioned at base portion top.
13. deep sub-micron MOS device as claimed in claim 12, it is characterized in that described sidewall be formed at second dielectric layer protuberance sidewall and be positioned at the base portion top of described second dielectric layer.
14. deep sub-micron MOS device as claimed in claim 9 is characterized in that described gate dielectric is a silicon oxide layer, described conductive layer is a polysilicon layer, and described interlayer dielectric layer is a silicon oxide layer, and described first dielectric layer is a silicon nitride layer.
15. deep sub-micron MOS device as claimed in claim 9 is characterized in that described second dielectric layer is that a silicon nitride layer and described the 3rd dielectric layer material are TEOS.
16. deep sub-micron MOS device as claimed in claim 15 is characterized in that described filling dielectric layer is a TEOS layer, similar described the 3rd dielectric layer of its rate of etch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02107868 CN1280881C (en) | 2002-03-25 | 2002-03-25 | Deep infra micro MOS devices and its manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02107868 CN1280881C (en) | 2002-03-25 | 2002-03-25 | Deep infra micro MOS devices and its manufacturing method |
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| CN1447403A CN1447403A (en) | 2003-10-08 |
| CN1280881C true CN1280881C (en) | 2006-10-18 |
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| CN 02107868 Expired - Lifetime CN1280881C (en) | 2002-03-25 | 2002-03-25 | Deep infra micro MOS devices and its manufacturing method |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8094846B2 (en) * | 2006-12-18 | 2012-01-10 | Epcos Pte Ltd. | Deep sub-micron MOS preamplifier with thick-oxide input stage transistor |
| CA2692595A1 (en) * | 2007-07-05 | 2009-01-08 | Peter Nilsson | Low resistance through-wafer via |
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- 2002-03-25 CN CN 02107868 patent/CN1280881C/en not_active Expired - Lifetime
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