CN1277182C - Programmable logic controller with auxiliary processing unit - Google Patents
Programmable logic controller with auxiliary processing unit Download PDFInfo
- Publication number
- CN1277182C CN1277182C CN 03158048 CN03158048A CN1277182C CN 1277182 C CN1277182 C CN 1277182C CN 03158048 CN03158048 CN 03158048 CN 03158048 A CN03158048 A CN 03158048A CN 1277182 C CN1277182 C CN 1277182C
- Authority
- CN
- China
- Prior art keywords
- module
- order
- unit
- counting
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Programmable Controllers (AREA)
Abstract
The present invention discloses a programmable logic controller with a first processing unit and a second processing unit for solving the problems of low execution speed of instructions, no improvement of count frequencies, insufficient frequency of pulse output, etc. because the existing programmable logic controller is provided with only one CPU. The second processing unit helps the operation of the first processing unit on instruction execution, counting and pulse output to enhance integral efficiency. In addition, when an expansion interface module is connected with another programmable logic controller, compared with the existing programmable logic controller, the programmable logic controller disclosed by the present invention has better performance.
Description
Technical field
The present invention is about a kind of logical circuit, particularly a kind of being applied in the programmable logic controller (PLC), the auxiliary processing unit of being made up of logical circuit.
Background technology
Automation equipment is used programmable logic controller (PLC) (Program-mable LogicController always at present, PLC, or be called Programmable Logic Controller) to control, especially process control, the control behavior of programmable logic controller (PLC) then use staircase chart (Ladder Diagram) software to design.The function of PLC is basic logical operation and timing counting, adds internal memory, and is required to satisfy industrial sequential control.The application instruction of data processing also can be transferred to the PLC CPU (central processing unit) and carry out.Along with the needs of analog signal processing, also has the analog digital modular converter.Further, because the demand of communication and networking also can increase mixed-media network modules mixed-media.
Basically, Programmable Logic Controller can be considered a micro computer with particular interface, the data processing of all is carried out in CPU (central processing unit) (CPU), load module is obtained the present state of outside controlled system, after the program judgement, decision activates those drivers on the output module, to drive controlled system.Programmable Logic Controller, basic as same small-size computer that designs for the system of process control specially.Through user's write-in program among reservoir, CPU is shining steering logic (Control Logic) monitoring that defines in the program and is handling input signal from equipment such as button, inductor or limit switches then, after logic determines, output signal is delivered to external loading, as relay, pilot lamp, motor etc.Sometimes can output signal be feedback as input signal according to user's needs, remove to control other output device again.
In traditional PLC, utilize a single-chip and simple logical integrated circuit to realize all functions mostly, in general process control and be acceptable on for the not high application of execution speed.But the problem that the performances such as frequency that still have frequency, the pulse output of for example instruction execution speed, counting can't improve.
In addition, with being connected of expansion machine, single-chip must be controlled the sequential and the data of output and input voluntarily, if be connected with the interface of another specific use integrated circuit (ASIC), seems inefficent on the writing and carry out of program.
And on the function of counting, the frequency of high counting is general only about 10kHz, thereby makes under the situation of using many batch totals number, and the frequency of high counting will descend thereupon, add different if desired output pattern pulses, the highest output frequency similarly can descend thereupon.
The method that solves at the problems referred to above is divided into two classes haply at present, and one is to use the more single-chip of high-order, but not only and then raising of cost thus, software design personnel also need learn new instrument.The second way is to use extra hardware to increase original function.
But diversification along with application mode, PLC is that requirement is higher for the performance of carrying out, no matter be on user's program execution speed, function is imported out in basic pulse, or expansion capacity etc., so the design that realizes all functions with a CPU (central processing unit) is not only not good when handling property, and can not meet the demand of user to the PLC function.
Summary of the invention
In view of above problem, fundamental purpose of the present invention is to provide a kind of programmable logic controller (PLC) with auxiliary processing unit, with the CPU (central processing unit) in the auxiliary processing unit collocation programmable logic controller (PLC), solving the not good problem of performance of existing programmable logic controller (PLC), thereby improve the performance of programmable logic controller (PLC).Originally the CPU (central processing unit) of programmable logic controller (PLC) mainly is responsible for instruction execution, counting and the pulse output of low speed, and auxiliary processing unit mainly is responsible for low speed and instruction execution at a high speed, counting and pulse output.
Therefore, to achieve these goals, the disclosed programmable logic controller (PLC) of the present invention with auxiliary processing unit, include one first processing unit and one second processing unit, in second processing unit, include an elementary instruction execution module, a pulse output module, an interrupt module, a counting module and a counting comparison module.In addition, also have an extended interface module,, use as expanding in order to be connected with other Programmable Logic Controller.Wherein elementary instruction execution module, pulse output module, interrupt module, counting module, counting comparison module and extended interface module connect by a data bus.
Under the framework of the disclosed programmable logic controller (PLC) with two processing units of the present invention, some commonly used commands are carried out by auxiliary processing unit, adopted reduced instruction set computer linear flow line type raising user's program execution speed during design and provide single step to carry out function.
In order to save the use of internal memory, user's program and related data are left in the shared storage module, added bus arbitration mechanism for this reason, when CPU (central processing unit) is wanted this shared storage element of access, counter module changes sign, or the counter comparison module when changing setting content the instruction execution can stop automatically then continuing carrying out.Plan that in addition state transitions offers first processing unit with instruction (STL order) and correlating markings and uses, so that second processing unit can be assisted first processing unit.
Technical scheme of the present invention is achieved in that
A kind of programmable logic controller (PLC) is characterized in that including:
One first processing unit is in order to carry out low speed pulse output, low speed counting and to carry out first group of instructions; And
One second processing unit in order to according to a look-at-me that is produced by this first processing unit, is carried out corresponding high-speed pulse output, high-speed counting and is carried out second group of instructions.
Wherein this second processing unit includes an elementary instruction execution module, in order to carry out this second group of instructions.
Wherein this elementary instruction execution module more includes:
One internal storage unit is in order to store this second group of instructions;
One arithmetic logic unit couples with this internal storage unit, in order to carry out this second group of instructions; And
The one sign unit that adds up couples with this arithmetic logic unit, after this second group of instructions is finished, changes add up value of statistical indicant in the unit of this sign.
Wherein this second processing unit includes a pulse output module, in order to export many group high-speed pulse signals.
Wherein this pulse output module includes:
One pulse output starts module, in order to export an enabling signal;
One pulse-length modulation module starts module with this pulse output and couples, when being a pulse-length modulation module enable signal, this enabling signal starts, and the output pulse width modulated pulse signal;
One pulse output module starts module with this pulse output and couples, when being the pulse output module enabling signal, this enabling signal starts, and output pulse signal; And
One deceleration pulse output module starts module with this pulse output and couples, when being a deceleration pulse output module enabling signal, this enabling signal starts, and output deceleration pulse output pulse signal.
Wherein this second processing unit includes an interrupt module, in order to the output look-at-me.
Wherein this interrupt module includes:
One interrupts the activation sign, interrupts the activation value of statistical indicant in order to record;
One positive negative edge is set sign, interrupts or the negative edge interruption in order to the record rising edge;
One start unit couples with this interruption activation sign, activates this start unit by the output and an interrupt source of this interruption activation sign, exports an enabling signal according to this;
One positive negative edge detecting device couples with this start unit, in order to receiving this enabling signal, and sets sign output one positive negative edge detection signal according to this positive negative edge;
One interrupt vector state working storage couples with this positive negative edge detecting device, in order to store the interrupt vector state;
One interruption status determining device judges that according to the output of this interrupt vector state and an interrupt vector seizure working storage rising edge interrupts or negative edge interrupts; And
One interruption status machine couples with this interruption status determining device, in order to the judged result output look-at-me according to this interruption status determining device.
Wherein this second processing unit includes a counting module, in order to carry out many group high-speed counting patterns.
Wherein this counting module includes:
One counter fiducial value record cell stores the counter fiducial value;
The present value record of one counter unit is worth now in order to storage counter;
One counting comparing unit couples with this counter fiducial value record cell, is worth now in order to compare counter fiducial value and this counter, whether arrives a predetermined value to judge number or following several numbers when last number;
One demultiplexer couples with this counting comparing unit, when the logical signal of this predetermined value is represented in the output of counting comparing unit, cooperates a count mode signal to export in the elementary instruction execution module;
One counts detecting unit up and down, couples with the present value record of this counter unit, is worth now in order to receive this counter, is last number or following number to detect present counting, and exports a testing result; And
One demultiplexer is counted detecting units up and down with this and is coupled, in order to according to this testing result and cooperate count mode to export signal to this elementary instruction execution module.
Wherein this second processing unit includes a comparison counting module.
Wherein this comparison counting module includes:
One comparative result OPADD unit is in order to store the comparative result OPADD;
One comparison pattern setup unit is set in order to store comparison pattern;
One counting is setpoint cell relatively, in order to store relatively setting value of counting;
One demultiplexer in order to the output signal of reception from this counting module, and is exported a count content according to this; And
One the 6th comparer couples with this comparative result OPADD unit, sets fiducial value in order to this count content relatively and this counting, and exports a comparative result to a multiplexer.
Description of drawings
Fig. 1 is the system architecture diagram of the disclosed auxiliary processing unit of the present invention
Fig. 2 is the system block diagram of the disclosed elementary instruction execution module of the present invention
Fig. 3 is the system block diagram of the disclosed pulse output module of the present invention
Interrupt module Fig. 4 is the system block diagram of disclosed PWM module and PLSY module
Fig. 5 is the system block diagram of disclosed PLSR module
Fig. 6 is the system block diagram of the disclosed interrupt module of the present invention
Fig. 7 is the system block diagram of the disclosed counting module of the present invention
Fig. 8 is the system block diagram of the disclosed counting comparison module of the present invention
Wherein, description of reference numerals is as follows:
100 first processing units
200 second processing units
10 elementary instruction execution modules
20 pulse output modules
30 interrupt modules
40 counting modules
50 counting comparison modules
60 extended interface modules
70 data buss
80 external memory units
11 arithmetic logic unit
12 internal storage units
13 indicate the unit that adds up
21 pulses output starts module
22 PWM modules
23 PLSY modules
24 PLSR modules
25 first demultiplexers
26 step-by-step counting unit
211 cell frequency generation units
212 cell frequency counters
213 mode initialization signs
214 first comparers
215 frequency dividers
216 cell frequency comparing units
221 PWM period setting unit
222 second comparers
223 the 3rd comparers
224 PWM export working storage
225 OffDuty sign
231 PLSY pulse setup units
232 the 4th comparers
241 frequency setting unit
242 pulse number setup units
243 PLSR treatment state unit
261 counting number setup units
262 the 5th comparers
31 interrupt the activation sign
32 positive negative edges are set sign
33 interrupt sources activate start unit
34 positive negative edge detecting devices
35 interrupt vector state working storages
36 interrupt vectors are caught working storage
37 interruption status determining devices
38 interruption status machines
41 counter fiducial value record cells
The present value record of 42 counters unit
43 counting comparing units
44 second demultiplexers
45A the 3rd demultiplexer
45B first multiplexer
46A the 4th demultiplexer
46B second multiplexer
47 count detecting unit up and down
48 the 5th demultiplexers
The 49A arithmetic logic unit
The 49B arithmetic logic unit
51 comparative result OPADD unit
52 comparison pattern setup units
53 countings are setpoint cell relatively
54 the 6th demultiplexers
55 the 6th comparers
56 comparative result working storages
57 the 3rd multiplexers
58 the 7th demultiplexers
IntCnt counts look-at-me
IntCmp relatively counts look-at-me
SYSclk system pulse signal
Embodiment
About feature of the present invention and practical function, existing conjunction with figs. is described in detail as follows most preferred embodiment of the present invention.
The disclosed programmable logic controller (PLC) of the present invention with auxiliary processing unit, first processing unit can be considered as a low-speed processing unit, and second processing unit is considered as the high speed processing unit, first processing unit mainly is responsible for instruction execution, counting operation and the pulse output of low speed, and second processing unit mainly is responsible for low speed and instruction execution at a high speed, counting operation and pulse output.Below just be described below respectively with the detailed content of upper module.
At first please refer to Fig. 1, be the block scheme of disclosed second processing unit of the present invention, second processing unit includes an elementary instruction execution module 10, a pulse output module 20, an interrupt module 30, a counting module 40 and a counting comparison module 50.In addition, still include an extended interface module 60, in order to be connected, as the use of expanding with other Programmable Logic Controller.Elementary instruction execution module 10, pulse output module 20, interrupt module 30, counting module 40, counting comparison module 50 and extended interface module 60 connect by a data bus 70.
Functional-block diagram in the elementary instruction execution module 10, please refer to Fig. 2, include an arithmetic logic unit 11, an internal storage unit 12 and the sign unit 13 that adds up, elementary instruction execution module 10 receives from the data-signal of first processing unit 100 and from the control signal of first processing unit, and internal storage unit 12 stores one second group of instructions.
After the start, will when finding specific instruction, promptly carry out specified instruction and operation at present immediately by the 60 periodic scannings and renewal of extended interface module.If all instructions all are stored in the storage unit, then in the time will carrying out specific instruction, first processing unit 100 so will reduce whole performance with reading of data execution in storage element constantly.Therefore, instruction that can some are commonly used or short instruction are stored in the internal reservoir unit 12 in second processing unit 200, just with required instruction of using in the programmable logic controller (PLC), divide into first group of instructions and second group of instructions according to a rule (for example frequency of utilization, instruction time etc.), first group of instructions is stored in the external memory unit 80 of programmable logic controller (PLC), and second group of instructions is stored in the internal reservoir unit 12 of second processing unit 200.External memory unit 80 can adopt Nonvolatile memory, for example static random access memory with internal storage unit 12.
When desire is carried out specific instruction when (belonging to the instruction in second group of instructions), then transferring to second processing unit 200 carries out, promptly carry out by the elementary instruction execution module 10 in second processing unit 200, and when instruction is finished, notify first processing unit 100, so, not only can reduce the computing load of first processing unit 100, more can improve whole operational performance.
Pulse output module 20 is in order to export able to programmeization pulse signal, in order to control controlled system, for example servo motor.Its system's square please refer to Fig. 3, pulse output module 20 comprises that mainly pulse output starts module 21, in order to export an enabling signal to start PWM module 22, PLSY module 23 or PLSR module 24, start after the module, the module that is activated is promptly exported corresponding pulse signal, and by one first demultiplexer 25 pulse is exported.The PWM module is pulse-length modulation, and PLSY is pulse output, and PLSR then for deceleration pulse output, is all the user and is used for controlling motor, according to the difference of motor driven mode, can do different settings.
Then cooperate Fig. 4 and Fig. 5 that the operation of PWM module 22, PLSY module 23 and PLSR module 24 is described.Include a cell frequency generation unit 211, a cell frequency counter 212 and a mode initialization sign 213 in the pulse output startup module 21, cell frequency generation unit 211 is given cell frequency counter 212 in order to export a cell frequency, again by cell frequency counter 212 output enabling signals, enabling signal is with two digital signal representation, for example " 01 " representative starts PWM module 22, " 10 " representative starts PLSY module 23, " 11 " representative starts PLSR module 24, and on behalf of pulse output, " 00 " then reset.
Cell frequency comparing unit 216 in the cell frequency generation unit 211, give first comparer 214 in order to export a frequency comparison signal, another of first comparer 214 is input as the pulse signal SYSclk of system, make the comparer 214 of winning export a comparison signal and give frequency divider 215 according to two signals, give cell frequency counter 212 by frequency divider 215 outputs one cell frequency signal, again by cell frequency counter 212 output enabling signals.
When the enabling signal of cell frequency counter 212 outputs is " 00 " (PWM module enable signal), pulse output module 20 will be exported pwm pulse signal this moment.22 have a PWM period setting unit 221 in the PWM module, give second comparer 222 in order to export a setting signal, another of second comparer 222 is input as enabling signal, make second comparer 222 export one second comparison signal according to this and export one the 3rd comparison signal to PWM output working storage 224 to 223 output signals of PWM output working storage 224, the three comparers according to enabling signal and OffDuty sign 225.224 of PWM output working storages are according to second comparison signal and the 3rd comparison signal output pwm pulse.
When the enabling signal of cell frequency counter 212 outputs is 10 (PLSY module enable signals), pulse output module 20 will be exported the PLSY pulse signal this moment, the PLSY pulse signal is by 231 outputs of the PLSY pulse setup unit in the PLSY module 23, export the 4th comparer 232 simultaneously to, another input of the 4th comparer 232 is the PLSY module enable signal then, makes the 4th comparer 232 outputs one replacement marking signal 00 to the mode initialization sign 213 in the pulse output startup module 21.
The system block diagram of PLSR module 24 please refer to Fig. 5.PLSR module 24 is started by the PLSR module enable signal (11) of cell frequency counter 212 outputs, and enabling signal inputs to step-by-step counting unit 26 simultaneously.Have a frequency setting unit 241 and a pulse number setup unit 242 in the PLSY module, frequency setting unit 241 stores more than at least one group can be for the frequency setting value of setting, and each frequency 242 stores a corresponding step-by-step counting number in the pulse setup unit.When setting the corresponding step-by-step counting number of a characteristic frequency and this frequency in the program, these setting values are exported in the PLSR treatment state unit 243 simultaneously, when PLSR treatment state unit 243 receives the PLSR module enable signal, then export the PLSR pulse.When all output settings dispose, then export a replacement marking signal 00 to the mode initialization sign 213 in the pulse output startup module 21.
Counting number setup unit 261 and cell frequency comparing unit 216 in the step-by-step counting unit 26 are exported to signal in PLSR treatment state unit 243, make the 5th comparer 262 in the step-by-step counting unit 26 to export one the 5th comparison signal, to judge whether that arriving next output of processing sets according to the output of PLSR enabling signal and counting number setup unit 261.
On the mode of setting, only need the frequency of input demand to get final product, do not need to be converted into number again and insert again, saved the time of first processing unit calculating like this and accelerated the performance of carrying out.
System block diagram about interrupt module 30 please refer to Fig. 6, and interrupt module 30 is responsible for handling the interrupt source from each module, and utilizes the interruption enable signal to trigger the interruption of first processing unit 100, comes handling interrupt to notify first processing unit 100.The disclosed interrupt mode of the present invention has the request type to interrupt interrupting with the pressure type, and each interrupt source can have rising edge, negative edge on setting, and reaches to start and waits sign for setting.
Interrupt recording in the activation sign 31 value of statistical indicant that interrupts activation, positive negative edge is set sign 32 and is then recorded rising edge interruption or negative edge interruption, when the output of interrupting activation sign 31 and interrupt source actuating start unit 33, it is positive and negative in detecting device 34 to activate that start unit 33 will be exported an enabling signal, and the output of positive negative edge detecting device 34 is coupled to an interrupt vector state working storage 35.Cooperate an interrupt vector to catch working storage 36, be judged as rising edge interruption or negative edge interruption by an interruption status determining device 37, and by interruption status machine 38 output look-at-mes.As long as have one to interrupt producing, 37 output of interruption status determining device look-at-me, if the result who detects is S1 for Zero and state then state is made as S0, this moment, look-at-me was output as 1, if the result who detects is not Zero and state to be S0 then state is made as S1, this moment, look-at-me was output as 0.
The system block diagram of counting module 40 please refer to Fig. 7, provides many groups independent high-speed counting pattern in the counting module 40, and when program needed high-speed counting, promptly by a look-at-me, notifications count module 40 was to carry out high-speed counting for first processing unit 100.
Include a counter fiducial value record cell 41 and the present value record of counter unit 42 in the counting module 40, storing counter fiducial value and counter respectively is worth now, counting comparing unit 43 comparisons counter fiducial value and counter are worth now, after the number of last number reaches, output logic 1 to second demultiplexer 44 then, when the number of Shuoing reaches instantly, then output logic 0 cooperates count mode that signal is exported to elementary instruction execution module 10 to separating second multiplexer, 44, the second demultiplexers 44 again.
42 outputs according to the 3rd demultiplexer 45A, the first multiplexer 45B and the 4th demultiplexer 46A, the second multiplexer 46B in the present value record of counter unit export the present value of counter to counts detecting units 47 up and down, for counting the present counting of detecting unit detection up and down is last number or following number, go up several then output logic 0 to the 5th demultiplexers 48, several then output logic 1 to the 5th demultiplexer 48, the five demultiplexers 48 cooperate count mode that signal is exported to elementary instruction execution module 10 down.
The present value cell 42 of counter output count content signal is in addition given the 6th demultiplexer 54.The present value cell 42 of counter is controlled by three control signals, is respectively reset signal, enabling signal and U/D sign, and reset signal is by AND arithmetic logic unit 49A output, and enabling signal is exported by AND arithmetic logic unit 49B.
The system block diagram of counting comparison module 50 please refer to Fig. 8, include comparative result OPADD unit 51, comparison pattern setup unit 52, and counting compares setpoint cell 53, comparative result OPADD unit 51 stores the comparative result OPADD, comparison pattern setup unit 52 stores comparison pattern and sets, counting relatively setpoint cell 53 stores relatively setting value of counting, four output signal (HSC0 that the 6th demultiplexer 54 receives from counter, HSC1, HSC2, HSC3), and export a count content according to this, compare count content by the 6th comparer 55 and compare setting value with counting, and export comparative result to the 3rd multiplexer 57 and the 7th demultiplexer 58, the three multiplexers 57 and 58 of the 7th demultiplexers operation result is exported in the elementary instruction execution module 10.Another comparative result output of the 6th comparer 55 is stored in the comparative result working storage 56.
In the application of reality, above-mentioned modular unit can be created a specific use integrated circuit (ASIC) with integrated circuit, so that a hardware independently to be provided, make on performance, can not descend along with using more resources.In addition, also above-mentioned module independently can be become the specific use integrated circuit separately.
Though the present invention discloses as above with aforesaid preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art should do some changes and retouching without departing from the spirit and scope of the present invention, so protection scope of the present invention is as the criterion with the appended scope of patent protection that claim was defined of this instructions.
Claims (6)
1. programmable logic controller (PLC) is characterized in that including:
First processing unit is in order to carry out low speed pulse output, low speed counting and to carry out first group of instructions; And
Second processing unit in order to according to the look-at-me that is produced by this first processing unit, is carried out corresponding high-speed pulse output, high-speed counting and is carried out second group of instructions;
Wherein, this second processing unit comprise by data bus connect with lower module:
The elementary instruction execution module is in order to carry out this second group of instructions;
Pulse output module is in order to export many group high-speed pulse signals;
Interrupt module is in order to the output look-at-me;
Counting module is in order to carry out many group high-speed counting patterns;
Compare counting module;
The extended interface module is used in order to be connected with other Programmable Logic Controller as expanding.
2. programmable logic controller (PLC) as claimed in claim 1 is characterized in that, wherein this elementary instruction execution module also includes:
Internal storage unit is in order to store this second group of instructions;
Arithmetic logic unit couples with this internal storage unit, in order to carry out this second group of instructions; And
The sign unit that adds up couples with this arithmetic logic unit, after this second group of instructions is finished, changes add up value of statistical indicant in the unit of this sign.
3. programmable logic controller (PLC) as claimed in claim 1 is characterized in that, wherein this pulse output module includes:
Pulse output starts module, in order to the output enabling signal;
The pulse-length modulation module starts module with this pulse output and couples, when being the pulse-length modulation module enable signal, this enabling signal starts, and the output pulse width modulated pulse signal;
Pulse output module starts module with this pulse output and couples, when being the pulse output module enabling signal, this enabling signal starts, and output pulse signal; And
The deceleration pulse output module starts module with this pulse output and couples, when being deceleration pulse output module enabling signal, this enabling signal starts, and output deceleration pulse output pulse signal.
4. programmable logic controller (PLC) as claimed in claim 1 is characterized in that, wherein this interrupt module includes:
Interrupt the activation sign, interrupt the activation value of statistical indicant in order to record;
Positive negative edge is set sign, interrupts in order to interruption of record rising edge or negative edge;
Start unit couples with this interruption activation sign, activates this start unit by the output and the interrupt source of this interruption activation sign, exports an enabling signal according to this;
Positive negative edge detecting device couples with this start unit, in order to receiving this enabling signal, and sets the positive negative edge detection signal of sign output according to this positive negative edge;
Interrupt vector state working storage couples with this positive negative edge detecting device, in order to store the interrupt vector state;
The interruption status determining device judges that according to the output of this interrupt vector state and interrupt vector seizure working storage rising edge interrupts or negative edge interrupts; And
The interruption status machine couples with this interruption status determining device, in order to the judged result output look-at-me according to this interruption status determining device.
5. programmable logic controller (PLC) as claimed in claim 1 is characterized in that, wherein this counting module includes:
Counter fiducial value record cell stores the counter fiducial value;
The present value record of counter unit is worth now in order to storage counter;
The counting comparing unit couples with this counter fiducial value record cell, is worth now in order to compare counter fiducial value and this counter, whether arrives a predetermined value to judge number or following several numbers when last number;
Demultiplexer couples with this counting comparing unit, when the logical signal of this predetermined value is represented in the output of counting comparing unit, cooperates the count mode signal to export in the elementary instruction execution module;
Counting detecting unit up and down, couple with the present value record of this counter unit, be worth now in order to receive this counter, is last number or following number to detect present counting, and the output testing result; And
Demultiplexer is counted detecting units up and down with this and is coupled, in order to according to this testing result and cooperate count mode to export signal to this elementary instruction execution module.
6. programmable logic controller (PLC) as claimed in claim 1 is characterized in that, wherein this comparison counting module includes:
Comparative result OPADD unit is in order to store the comparative result OPADD;
The comparison pattern setup unit is set in order to store comparison pattern;
Counting is setpoint cell relatively, in order to store relatively setting value of counting;
Demultiplexer in order to the output signal of reception from this counting module, and is exported a count content according to this; And
The 6th comparer couples with this comparative result OPADD unit, sets fiducial value in order to this count content relatively and this counting, and exports a comparative result to multiplexer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03158048 CN1277182C (en) | 2003-09-04 | 2003-09-04 | Programmable logic controller with auxiliary processing unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03158048 CN1277182C (en) | 2003-09-04 | 2003-09-04 | Programmable logic controller with auxiliary processing unit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1591323A CN1591323A (en) | 2005-03-09 |
| CN1277182C true CN1277182C (en) | 2006-09-27 |
Family
ID=34598588
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 03158048 Expired - Fee Related CN1277182C (en) | 2003-09-04 | 2003-09-04 | Programmable logic controller with auxiliary processing unit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1277182C (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8219781B2 (en) | 2008-11-06 | 2012-07-10 | Silicon Motion Inc. | Method for managing a memory apparatus, and associated memory apparatus thereof |
| CN102540954B (en) * | 2010-12-24 | 2015-03-11 | 深圳市合信自动化技术有限公司 | Programmable logic controller and control method thereof |
| CN105403726A (en) * | 2015-12-17 | 2016-03-16 | 滁州市博创电气有限公司 | Pulse velocity measurement module |
| CN112214244A (en) * | 2016-08-05 | 2021-01-12 | 中科寒武纪科技股份有限公司 | Arithmetic device and operation method thereof |
| CN106054758A (en) * | 2016-08-19 | 2016-10-26 | 上海鲍麦克斯电子科技有限公司 | Control system and method realizing multiple-input-multiple-output function |
-
2003
- 2003-09-04 CN CN 03158048 patent/CN1277182C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1591323A (en) | 2005-03-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1236392C (en) | Device and method for generating interrupt signals | |
| CN1028922C (en) | System to service processor interface for a tablet computer | |
| CN1292360C (en) | Device and method for implementing automatically reading and writing internal integrated circuit equipment | |
| CN1287256C (en) | Electronic device and power control method | |
| CN1549976A (en) | Generic serial port architecture and system | |
| CN101060412A (en) | Ethernet power supply system, control unit, master control module and Ethernet power supply method | |
| CN1862515A (en) | Data trnasfer apparatus, data transfer method, and program | |
| CN1740949A (en) | Information processor, starting method thereof | |
| CN100346285C (en) | Processor chip, storage control system and method | |
| CN1967421A (en) | Dynamic forward-looking processing method of small program segment and implementing device | |
| CN1896981A (en) | Bus control system and a method thereof | |
| CN1804799A (en) | SCM online loading and updating method and system | |
| CN1277182C (en) | Programmable logic controller with auxiliary processing unit | |
| CN1942854A (en) | Screen transition control device | |
| CN1755661A (en) | Information processing apparatus and method and program | |
| CN1287259C (en) | Device and method for operating multiple I2C sub device in communication equipment | |
| CN1172986A (en) | Real-time control system | |
| CN1138213C (en) | Microcomputer | |
| CN1146796C (en) | Stack-type register stack and its control method | |
| CN1120395C (en) | Servo system controller | |
| CN1324421C (en) | Method and apparatus for central processor frequency conversion and central processor fan speed change | |
| CN1598797A (en) | Real-time processor system and control method | |
| CN1960194A (en) | Sorting device | |
| CN101046745A (en) | Method, device for controlling relation between control piece on interface and control piece display system | |
| CN1636185A (en) | Logic computing system and method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Assignee: Zhongda Photoelectric Industry (Wujiang) Co.,Ltd. Assignor: Delta Optoelectronics Inc. Contract fulfillment period: 2008.1.1 to 2013.12.31 contract change Contract record no.: 2009990000377 Denomination of invention: Programmable logic controller with auxiliary processing unit Granted publication date: 20060927 License type: Exclusive license Record date: 2009.4.28 |
|
| LIC | Patent licence contract for exploitation submitted for record |
Free format text: EXCLUSIVE LICENSE; TIME LIMIT OF IMPLEMENTING CONTACT: 2008.1.1 TO 2013.12.31; CHANGE OF CONTRACT Name of requester: ZHONGDA OPTICAL INDUSTRY (WUJIANG) CO., LTD. Effective date: 20090428 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20060927 Termination date: 20150904 |
|
| EXPY | Termination of patent right or utility model |